Methods for correcting stacking errors and methods for fabricating semiconductor devices

Abstract

This disclosure provides a method for correcting overlay errors. The method includes generating a first overlay error based on a first overlay mark, wherein the first overlay error indicates a misalignment between a lower pattern and an upper pattern of the first overlay mark; and generating a second overlay error based on a second overlay mark in response to detecting an anomaly in the first overlay error, and determining, based on the second overlay error, whether the anomaly in the first overlay error is caused by the misalignment between the lower pattern and the upper pattern.

Description

[0001] Cross-referencing

[0002] This application claims priority to U.S. Patent Applications Nos. 17 / 568,041 and 17 / 568,118 (i.e., priority date "January 4, 2022"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a method for correcting overlay errors and a method for fabricating semiconductor devices. Background Technology

[0004] With the development of the semiconductor industry, reducing overlay error between photoresist patterns and underlying patterns in photolithography operations has become increasingly important. Various factors, such as the asymmetrical shape of the measurement structure, make accurate measurement of overlay error more difficult, thus requiring new overlay marking and methods for more precise measurement.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0006] One aspect of this disclosure provides an overlay correction mark. The mark includes a first pattern and a second pattern. The first pattern is disposed on a first surface of a substrate. The second pattern is disposed on a second surface of the substrate, the second surface of the substrate being opposite to the first surface of the substrate. The first pattern overlaps at least a portion of the second pattern, and the first pattern and the second pattern together define a first overlay error.

[0007] Another aspect of this disclosure provides an overlay correction mark. The mark includes a first overlay mark and a second overlay mark. The first overlay mark includes a first pattern and a second pattern disposed on a first surface of a substrate. The first overlay mark is used to generate a first overlay error. The second overlay mark includes a third pattern disposed on a second surface of the substrate and a fourth pattern disposed on the first surface of the substrate. The first surface of the substrate is opposite to the second surface of the substrate. The second overlay mark is used to generate a second overlay error and to correct the first overlay error.

[0008] Another aspect of this disclosure provides a method for correcting overlay errors. The method includes generating a first overlay error based on a first overlay mark, wherein the first overlay error indicates a misalignment between a lower pattern and an upper pattern of the first overlay mark; and generating a second overlay error based on a second overlay mark in response to detecting an anomaly in the first overlay error, and determining, based on the second overlay error, whether the anomaly in the first overlay error is caused by the misalignment between the lower and upper patterns.

[0009] Another aspect of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate having a first surface and a second surface opposite thereto, forming a first pattern on the first surface of the substrate, forming a second pattern on the second surface of the substrate, forming an intermediate structure covering the second pattern, forming a third pattern on the second surface of the substrate, wherein the second pattern and the third pattern together define a first overlay error, and forming a fourth pattern on the second surface of the substrate, wherein the first pattern and the fourth pattern together define a second overlay error.

[0010] Embodiments of this disclosure provide overlay markers for measuring overlay error. Two overlay markers can be used to determine whether an anomaly in the overlay error is caused by misalignment between the current and previous layers, or by wafer warping. The two measurement steps using the two overlay markers prevent inaccurate adjustments of the exposure equipment. Therefore, the uptime of the exposure equipment can be increased.

[0011] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0012] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0013] Figure 1 This is a top view illustrating a wafer of some embodiments of this disclosure.

[0014] Figure 2 This is an enlarged view illustrating some embodiments of this disclosure. Figure 1 The dotted areas in the middle.

[0015] Figure 3 This is a top view illustrating the superimposed labels of some embodiments of this disclosure.

[0016] Figure 3A These are examples illustrating some embodiments of this disclosure. Figure 3 A sectional view of line A-A'.

[0017] Figure 3B These are examples illustrating some embodiments of this disclosure. Figure 3 A sectional view of line B-B'.

[0018] Figure 4 This is a top view illustrating the superimposed labels of some embodiments of this disclosure.

[0019] Figure 4A These are examples illustrating some embodiments of this disclosure. Figure 4 A cross-sectional view of the C-C' line.

[0020] Figure 5 This is a cross-sectional view illustrating stacked reference numerals for some embodiments of this disclosure.

[0021] Figure 6 This is a cross-sectional view illustrating stacked reference numerals for some embodiments of this disclosure.

[0022] Figure 7 This is a cross-sectional view illustrating stacked reference numerals for some embodiments of this disclosure.

[0023] Figure 8 This is a cross-sectional view illustrating stacked reference numerals for some embodiments of this disclosure.

[0024] Figure 9 This is a block diagram illustrating a semiconductor fabrication system according to some embodiments of the present disclosure.

[0025] Figure 10 This is a flowchart illustrating methods for preparing overlay markers in various aspects of this disclosure.

[0026] Figure 11 This is a flowchart illustrating methods for correcting overlay errors in various aspects of this disclosure.

[0027] Figure 12 This is a diagram illustrating the hardware of a semiconductor fabrication system according to various aspects of this disclosure.

[0028] Explanation of reference numerals in the attached figures:

[0029] 10: Wafers

[0030] 21: Overlay Marker

[0031] 22: Overlay Marker

[0032] 30: Cutting track

[0033] 40: Chip

[0034] 100: Base

[0035] 100s1: Surface

[0036] 100s2: Surface

[0037] 110: Overlay Marker

[0038] 111: Pattern

[0039] 112: Pattern

[0040] 120a: Overlay mark

[0041] 120b: Overlay mark

[0042] 120c: Overlay mark

[0043] 121a: Pattern

[0044] 121b: Pattern

[0045] 121c: Pattern

[0046] 122: Pattern

[0047] 122': Features

[0048] 130: Intermediate Structure

[0049] 140: Mask

[0050] 150: Virtual Layer

[0051] 160a: Overlay mark

[0052] 160b: Overlay mark

[0053] 161a: Pattern

[0054] 161b: Pattern

[0055] 162: Pattern

[0056] 170: Intermediate Structure

[0057] 180: Mask

[0058] 300: Semiconductor Fabrication System

[0059] 310: Manufacturing equipment

[0060] 320-1,…,320-N: Manufacturing equipment

[0061] 330: Manufacturing equipment

[0062] 340-1,…,340-N: Manufacturing equipment

[0063] 350: Exposure equipment

[0064] 360: Overlay Measurement Equipment

[0065] 370: Overlay (OVL) Correction System

[0066] 380: Network

[0067] 390: Controller

[0068] 400: Preparation method

[0069] 410: Operation

[0070] 420: Operation

[0071] 430: Operation

[0072] 440: Operation

[0073] 450: Operation

[0074] 500: Methods

[0075] 510: Operation

[0076] 520: Operation

[0077] 530: Operation

[0078] 540: Operation

[0079] 550: Operation

[0080] 560: Operation

[0081] 570: Operation

[0082] 600: Semiconductor Fabrication System

[0083] 601: Processor

[0084] 603: Computer-readable storage media

[0085] 605: Bus

[0086] 607: Input and Output (I / O) Interface

[0087] 609: Network Interface

[0088] 610: User Interface

[0089] A-A': line

[0090] B-B': Line

[0091] C-C': Line

[0092] X: Direction

[0093] Y: direction

[0094] Z: Direction Detailed Implementation

[0095] Embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that this is not intended to limit the scope of the disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as commonly done by one of ordinary skill in the art to which this disclosure relates. Reference numerals may be repeated throughout the embodiments, but this is not intended to apply a feature of one embodiment to another, even if they share the same reference numerals.

[0096] It should be understood that although the terms first, second, third, etc., can be used to describe various elements, components, regions, layers, or portions, these elements, components, regions, layers, or portions are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer, or portion from another. Therefore, the first element, component, region, layer, or portion discussed below can be referred to as the second element, component, region, layer, or portion without departing from the teachings of the concept of the invention.

[0097] The terminology used herein is for describing particular embodiments only and is not intended to limit one to the concepts of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include multiple forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprising" and "including" as used in this specification indicate the presence of the stated feature, integer, step, operation, element, or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0098] Figure 1 This is a top view illustrating wafer 10, representing various aspects of this disclosure. Figure 2 yes Figure 1 A magnified view of the midpoint-shaped area.

[0099] like Figure 1 and Figure 2As shown, wafer 10 is sawn into multiple chips 40 along dicing 30. Each chip 40 may include a semiconductor element, which may include active and / or passive elements. Active elements may include a memory chip (e.g., a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.), a power management chip (e.g., a power management integrated circuit (PMIC) chip), a logic chip (e.g., a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, etc.), a radio frequency (RF) chip, a sensor chip, a microelectromechanical system (MEMS) chip, a signal processing chip (e.g., a digital signal processing (DSP) chip), a front-end chip (e.g., an analog front-end (AFE) chip), or other active elements. Passive elements may include a capacitor, a resistor, an inductor, a fuse, or other passive elements.

[0100] like Figure 2 As shown, overlay marks 21 and 22 may be disposed on wafer 10. In some embodiments, overlay marks 21 or 22 may be located on dicing 30. Overlay marks 21 or 22 may be disposed at the corner of the edge of each chip 40. In some embodiments, overlay marks 21 or 22 may be located inside chip 40. In some embodiments, overlay mark 21 may be used to measure whether an opening of a current layer, such as a photoresist layer, is precisely aligned with a previous layer in a semiconductor process. In some embodiments, overlay mark 21 may be used to generate a first overlay error between the current layer (or upper layer) and the previous layer (or lower layer). In some embodiments, overlay mark 22 may be used to generate a second overlay between two patterns (e.g., current pattern and reference pattern) on two opposite sides of wafer 10. In some embodiments, overlay mark 22 may be used to correct the first overlay error generated from overlay mark 21. In some embodiments, overlay mark 22 may be used to determine whether an anomaly (or abnormality) in the first overlay error generated from overlay mark 21 is caused by misalignment of the current layer and the previous layer. In some embodiments, overlay marker 22 may be used to determine whether an anomaly in the first overlay error is caused by wafer warpage. In some embodiments, overlay markers 21 and 22 may be used together to determine the degree of warpage of wafer 10. In some embodiments, overlay markers 21 and 22 may be used together to determine whether an anomaly in the first overlay error generated from overlay marker 21 is caused by wafer warpage.

[0101] Figure 3 This is a top view illustrating the stacking marks 110 for aligning different layers on a substrate 100, representing various aspects of this disclosure. (See figure) Figure 3 As shown, a semiconductor device structure, such as a wafer, may include stacked markings 110 on a substrate 100. In some embodiments, Figure 2 The stacking mark 21 shown may include and Figure 3 The overlapping mark 110 is similar to or the same pattern or structure.

[0102] Substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate. Substrate 100 may include an elemental semiconductor, including silicon or germanium in single-crystal, polycrystalline, or amorphous form; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy with a gradient Ge characteristic, wherein the composition of Si and Ge changes from the ratio at one location of the gradient SiGe characteristic to the ratio at another location. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically tensioned by another material in contact with the SiGe alloy. In some embodiments, substrate 100 may have a multilayer structure, or substrate 100 may include a multilayer compound semiconductor structure.

[0103] Overlay marks 110 may include patterns 111 and 112 on substrate 100. Pattern 111 may be a pattern of a preceding layer. Pattern 112 may be a pattern of a current layer. The preceding layer (or lower layer) may be located at a different horizontal level than the current layer (or upper layer). Each pattern 111 (or pattern 112) may be located in one of four orthogonal destination regions, two of which are used to measure overlay error in the X direction and two of which are used to measure overlay error in the Y direction.

[0104] When measuring a stacking error using a stacking mark (such as stacking mark 110), the deviation in the X direction is measured along a straight line in the X direction of stacking mark 110. The deviation in the Y direction is further measured along a straight line in the Y direction of stacking mark 110. A single stacking mark, including patterns 111 and 112, can be used to measure the deviation in the X and Y directions between two layers on a substrate. Therefore, the accuracy of alignment between the current layer and the preceding layer can be determined based on the deviations in the X and Y directions. The stacking error may include the deviation in the X direction (ΔX), the deviation in the Y direction (ΔY), or a combination of both.

[0105] Figure 3A It is along Figure 3 A sectional view taken along line A-A'.

[0106] like Figure 3 and Figure 3A As shown, substrate 100 may have surface 100s1 and surface 100s2 opposite to surface 100s1. Surface 100s2 of substrate 100 may be an active surface on which an input and output terminal is disposed. Surface 100s1 of substrate 100 may be a back surface. Pattern 111 may be disposed on surface 100s1 of substrate 100. Pattern 111 may be disposed within or below intermediate structure 130. In some embodiments, pattern 111 may include the same material as an isolation structure. In some embodiments, pattern 111 may be disposed at the same elevation as the isolation structure. The isolation structure may include, for example, shallow trench isolation (STI), field oxidation (FOX), localized oxidation of silicon (LOCOS) features, and / or other suitable isolation elements. The isolation structure may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxy-nitride, fluorinated silicate (FSG), a low-k dielectric material, combinations thereof, and / or other suitable materials.

[0107] In some embodiments, pattern 111 may include the same material as a gate structure. The gate structure may be sacrificial, for example, a dymmy gate structure. In some embodiments, pattern 111 may be disposed at the same elevation as the gate structure. In some embodiments, pattern 111 may include a dielectric layer of the same material as a gate dielectric layer and a conductive layer of the same material as a gate electrode layer.

[0108] In some embodiments, the gate dielectric layer may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or combinations thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-k dielectric material. The high-k material may have a dielectric constant (k value) greater than 4. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. Other suitable materials are also within the scope of this disclosure.

[0109] In some embodiments, the gate electrode layer may include a polysilicon layer. In some embodiments, the gate electrode layer may be fabricated using a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, the gate electrode layer may include a work function layer. The work function layer may be fabricated using a metallic material, and the metallic material may include metals with N-work function or metals with P-work function. N-work function metals include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations thereof. P-work function metals include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof. Other suitable materials are also within the scope of this disclosure. The gate electrode layer may be formed by low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced CVD (PECVD).

[0110] In some embodiments, pattern 111 may include the same material as a conductive via, which may be disposed on a conductive wire, such as a first metal layer (M1 layer). In this embodiment, pattern 111 may include a barrier layer and a conductive layer surrounded by the barrier layer. The barrier layer may include a metal nitride or other suitable material. The conductive layer may include a metal, such as W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, Cr, alloy, or other suitable material. In this embodiment, pattern 111 may be formed by a suitable deposition process, such as sputtering or physical vapor deposition (PVD).

[0111] Intermediate structure 130 may include one or more intermediate layers made of an insulating material, such as silicon oxide or silicon nitride. In some embodiments, intermediate structure 130 may include a conductive layer, such as a metal layer or alloy layer. In some embodiments, one or more intermediate layers may be formed by a suitable film deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). After the intermediate layer is formed, a thermal operation, such as rapid thermal annealing, may be performed. In other embodiments, a planarization operation, such as chemical mechanical polishing (CMP), may be performed. In other embodiments, a removal operation, such as an etching process, may be performed. The etching process may include, for example, a dry etching process or a wet etching process. It is understood that additional operations may be provided before, during, and after the above processes, and some of the above operations may be replaced or omitted for other embodiments of the method. The order of operations / processes may be interchanged.

[0112] Figure 3B It is along Figure 3A sectional view taken along line B-B'.

[0113] like Figure 3 and Figure 3B As shown, pattern 112 is disposed on intermediate structure 130. Pattern 112 may be disposed on or above surface 100s2 of substrate 100. In some embodiments, pattern 112 may be a plurality of openings defined by mask 140. Mask 140 may be formed on intermediate structure 130 and will be removed in a subsequent process. Mask 140 may include a positive or negative photoresist (such as a polymer), or a hard mask (such as silicon nitride or silicon oxynitride). The layer including mask 140 and pattern 112 may be patterned using a suitable photolithography method, for example, forming a photoresist layer on intermediate structure 130, exposing the photoresist layer to form a pattern through a mask, or baking and developing the photoresist to form mask 140 and pattern 112. Mask 140 can then be used to define the pattern into intermediate structure 130, so that the portion of intermediate structure 130 exposed by the photoresist layer can be removed.

[0114] Figure 4 This is a top view illustrating the stacked reference numeral 120a of some embodiments of this disclosure. (See figure) Figure 4 As shown, a semiconductor device structure, such as a wafer, may include stacked markings 120a on a substrate 100. In some embodiments, Figure 2 The stacked mark 22 shown may include and Figure 4 The overlapping mark 120a shown has a similar or identical pattern or structure.

[0115] Overlay mark 120a may include patterns 121a and 122. In some embodiments, patterns 121a and 122 may be disposed on two opposing surfaces of substrate 100. In some embodiments, the outlines of pattern 121a and pattern 122 are equiformable in a plan view. In some embodiments, the outlines of pattern 121a and pattern 122 are symmetrical with respect to the XY plane. In some embodiments, the shapes of pattern 121a and pattern 122 are substantially the same. In some embodiments, the dimensions of pattern 121a and pattern 122 are substantially the same. In some embodiments, pattern 121a overlaps at least a portion of pattern 122 along the Z direction. In some embodiments, each of patterns 121a and 122 may consist of a single continuous pattern. In some embodiments, the single continuous pattern may have any outline or shape. In this embodiment, pattern 121a may also be referred to as a reference pattern. In this disclosure, the term "equiformable" may refer to two patterns of the same size and / or shape.

[0116] When measuring an overlay error using an overlay mark, such as overlay mark 120a, the deviation in the X direction is measured along a straight line in the X direction of overlay mark 120a. The deviation in the Y direction is further measured along a straight line in the Y direction of overlay mark 120a. Therefore, whether patterns 121a and 122 are precisely aligned can be determined based on the deviations in the X and Y directions. The overlay error may include the deviation in the X direction (ΔX), the deviation in the Y direction (ΔY), or a combination of both.

[0117] Figure 4A These are examples illustrating some embodiments of this disclosure. Figure 4 A cross-sectional view of the C-C' line.

[0118] In some embodiments, pattern 121a may be disposed on surface 100s1 of substrate 100. In some embodiments, pattern 121a may include a layer protruding from surface 100s1 of substrate 100, such as a dummy layer. In some embodiments, the material of pattern 121a may include a polycrystalline silicon layer. In some embodiments, the fabrication technique of pattern 121a may be a metal, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. Pattern 121a may be formed by LPCVD, PECVD, sputtering, or other suitable processes. In some embodiments, pattern 121a may include a material that can be distinguished from the material of substrate 100 by an optical image. In some embodiments, pattern 121a may include a material that can be distinguished from silicon oxide by an optical image.

[0119] In some embodiments, pattern 122 may be disposed on or above surface 100s2 of substrate 100. In some embodiments, pattern 122 may be disposed on intermediate structure 130. In some embodiments, pattern 122 may be an opening or groove defined by mask 140. Pattern 122 may be patterned using suitable photolithography, for example, forming a photoresist layer over intermediate structure 130, exposing the photoresist layer through a mask, or baking and developing the photoresist to form mask pattern 122. In some embodiments, patterns 112 and 122 may be located at the same horizontal level. In some embodiments, patterns 112 and 122 may be formed simultaneously. That is, patterns 112 and 122 may be formed by the same process and by the same semiconductor manufacturing equipment. In some embodiments, the outline of pattern 122 may be different from the outline of pattern 112.

[0120] In some embodiments, a first overlay error can be generated using overlay marker 110, and the misalignment between the current layer and the preceding layer can be measured by measuring the positions of patterns 121a and 122. In some embodiments, the first overlay error may be an anomaly caused by the misalignment between the current layer and the preceding layer. In some embodiments, the first overlay error is an anomaly caused by reasons other than the misalignment between the current layer and the preceding layer. For example, wafer warping can cause an anomaly in the first overlay error. In this case, the anomaly in the first overlay error is not caused by the misalignment between the current layer and the preceding layer, and if the exposure equipment is adjusted solely based on the first overlay error, the adjusted exposure equipment will cause misalignment of the next wafer due to inaccurate or inappropriate adjustments.

[0121] A second overlay error can be generated using overlay marker 120a. In some embodiments, overlay marker 120a can be used to correct the first overlay error based on the second overlay error. In some embodiments, overlay marker 120a can be used to determine whether an anomaly in the first overlay is caused by wafer warpage rather than by misalignment between the current and previous layers. If no warpage occurs, the optical image of pattern 121a is overlaid on the image of pattern 122. When wafer warpage occurs, a displacement will occur between patterns 121a and 122. In some embodiments, the second overlay error can increase with the degree of warpage. Therefore, the second overlay error can be considered as an indicator of wafer warpage. In some embodiments, when the second overlay error exceeds a predetermined value, it can be determined that the anomaly in the first overlay error is caused by a warpage problem rather than misalignment. Therefore, the exposure apparatus can avoid inaccurate adjustments to the first and second overlay errors. Furthermore, both the first and second overlay errors can be obtained by an overlay measurement device. In this embodiment, it is not necessary to transfer the wafer with the first stacking error to a warp measurement device, such as patterned wafer geometry (PWG) metrology, thus improving the fabrication cycle time of the semiconductor device structure.

[0122] Figure 5 This is a cross-sectional view illustrating the superimposed reference numeral 120b of some embodiments of this disclosure. Figure 5 The overlapping mark 120b shown can be used with Figure 4A Similar to the overlay mark 120a shown, except that the overlay mark 120b may include pattern 121b.

[0123] In some embodiments, pattern 121b may be defined by a groove in surface 100s1 of substrate 100. In some embodiments, pattern 121b may be formed by etching on surface 100s1 of substrate 100. In some embodiments, the groove of substrate 100 may be filled with other materials, such as dielectric or conductive materials.

[0124] In this embodiment, the overlay marker 120b can be used to determine whether an anomaly in the first overlay is caused by wafer warping rather than by misalignment between the current and previous layers. Therefore, the exposure equipment can be unaffected by inaccurate or inappropriate adjustments due to the first and second overlay errors.

[0125] Figure 6 This is a cross-sectional view illustrating the superimposed reference numeral 120c of some embodiments of this disclosure. Figure 6 The overlapping mark 120c shown can be similar to Figure 4A The overlapping mark 120a shown is different in that the overlapping mark 120c may include pattern 121c.

[0126] In some embodiments, a dummy layer 150 may be formed on the surface 100s1 of the substrate 100. In some embodiments, a pattern 121c may be defined by a groove in the dummy layer 150. In some embodiments, the pattern 121c may be formed by etching on the dummy layer 150. In some embodiments, the groove in the dummy layer 150 may be filled with other materials. In some embodiments, the dummy layer 150 may include a polysilicon layer. In some embodiments, the dummy layer 150 may be a metal, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, a portion of the surface 100s1 of the substrate 100 may be exposed by the dummy layer 150. In some embodiments, the groove in the dummy layer 150 may be a blind via.

[0127] In this embodiment, the overlay marker 120c can be used to determine whether an anomaly in the first overlay is caused by wafer warping rather than by misalignment between the current and previous layers. Therefore, the exposure equipment can be unaffected by inaccurate or inappropriate adjustments due to the first and second overlay errors.

[0128] Figure 7 This is a cross-sectional view, illustrating the superimposed reference numeral 160a of some embodiments of this disclosure. Figure 7 The semiconductor device structure shown is similar to Figure 4A The semiconductor devices shown have similar structures, but differ in that... Figure 7 The semiconductor device structure may also include stacked markings 160a.

[0129] A third stacking error can be generated using stacking mark 160a. Stacking mark 160a can be used to determine whether an anomaly in a stacking error caused by another pair of mating layers and a preceding layer is caused by warping on the wafer. Although not shown, it should be noted that the other pair of mating layers and the preceding layer can be located on and within the intermediate structure 170, respectively. Stacking mark 160a can be used to determine whether an anomaly in the stacking error is caused by misalignment of the aforementioned mating layer and preceding layer.

[0130] Overlay mark 160a may include patterns 161a and 162, which may be used together to generate a third overlay error. In some embodiments, pattern 161a may be disposed on surface 100s1 of substrate 100. In some embodiments, pattern 161a and pattern 121a may be located on the same horizontal plane. In some embodiments, the material of pattern 161a may be the same as that of pattern 121a and made by the same process. In some embodiments, the outline of pattern 161a may be the same as the outline of pattern 121a. In some embodiments, the outline of pattern 161a may be different from the outline of pattern 121a. In some embodiments, pattern 161a may not overlap with pattern 121a in the Z direction.

[0131] In some embodiments, pattern 162 may be disposed on or above surface 100s2 of substrate 100. In some embodiments, pattern 162 may be located at a different position than the horizontal plane of feature 122'. Pattern 162 may be disposed on intermediate structure 170. Intermediate structure 170 may include one or more dielectric layers and conductive features disposed within the dielectric layers. Intermediate structure 170 may cover feature 122'. Feature 122' may be formed by filling an opening defined by pattern 122 with conductive or dielectric material. Feature 122' may have the same pattern as pattern 122. In some embodiments, pattern 162 may be an opening or a recess defined by mask 180. Mask 180 may be formed on intermediate structure 170 and will be removed in a subsequent process. Mask 180 may include a positive or negative photoresist. Mask 180 may be used to define a pattern in intermediate structure 170 such that portions of intermediate structure 170 exposed by the photoresist layer can be removed.

[0132] In some embodiments, in a plan view, the outlines of pattern 162 and pattern 161a are identical in shape. In some embodiments, the outlines of pattern 161a and pattern 162 are symmetrical with respect to the XY plane. In some embodiments, the shapes of pattern 161a and pattern 162 are substantially the same. In some embodiments, the dimensions of pattern 161a and pattern 162 are substantially the same. In some embodiments, pattern 161a overlaps at least a portion of pattern 162 along the Z-axis.

[0133] In this embodiment, the overlay marker 160a can be used to estimate wafer warpage, the stage of which is related to... Figure 4A The stage of warpage estimation using overlay marker 120a differs from the previous method. In this embodiment, overlay marker 160a can be used to determine whether anomalies in the overlay are caused by wafer warpage, rather than by misalignment between the current and previous layers. Therefore, the exposure equipment can be unaffected by inaccurate adjustments due to third-layer overlay errors.

[0134] Figure 8This is a cross-sectional view illustrating stacked reference numerals for some embodiments of this disclosure. Figure 8 The semiconductor device structure shown can be similar to Figure 7 The semiconductor device structure shown differs in that it may also include stacked markings 160b.

[0135] A third overlay error can be generated using overlay marker 160b. Overlay marker 160b can be used to determine whether anomalies in the overlay errors generated from another pair of layers and the preceding layer are caused by wafer warpage. Overlay marker 160b can be used to estimate wafer warpage at another stage, which is related to... Figure 4A The stage of warping is estimated using overlay marker 120a, as shown.

[0136] Overlay mark 160b may include patterns 161b and 162, which may be used together to generate a third overlay error. In some embodiments, pattern 161b may be disposed on surface 100s1 of substrate 100. In some embodiments, pattern 161b and pattern 121c may be located on different horizontal levels. In some embodiments, pattern 121c may be defined by a groove in dummy layer 150. In some embodiments, the groove in dummy layer 150 may be filled with other materials, such as dielectric or conductive materials. In some embodiments, pattern 161b may be another dummy layer or a groove of another dummy layer disposed on dummy layer 150. For example, the material of pattern 161b may include a polysilicon layer, a metal layer, or an alloy layer, and may be formed by LPCVD, PECVD, sputtering, or other suitable processes.

[0137] although Figure 8 It is explained that the horizontal plane of pattern 161b is lower than the horizontal plane of pattern 121c, but this disclosure is not intended to be limiting. In some other embodiments, the horizontal plane of pattern 161b may be higher than the horizontal plane of pattern 121c. In some embodiments, pattern 161b may not overlap with pattern 121c in the Z direction.

[0138] In this embodiment, the overlay marker 160b can be used to determine whether an overlay anomaly is caused by wafer warping rather than misalignment between the current and previous layers. Therefore, the exposure equipment can be unaffected by inaccurate or inappropriate adjustments due to third-layer overlay errors.

[0139] Figure 9 This is a block diagram illustrating a semiconductor fabrication system 300 according to some embodiments of the present disclosure.

[0140] The semiconductor fabrication system 300 may include fabrication equipment 310, 320-1, ..., and 320-N, 330, 340-1, ..., and 340-N, exposure equipment 350, and overlay measurement equipment 360. An overlay correction system 370 may be included in or integrated within the overlay measurement equipment 360. The fabrication equipment 310, 320-1, ..., and 320-N, 330, 340-1, ..., and 340-N, exposure equipment 350, and overlay measurement equipment 360 may be signal-coupled to a controller 390 via a network 380. In some embodiments, the overlay correction system 370 may be a standalone system, signal-coupled to the overlay measurement equipment 360 via network 380.

[0141] Manufacturing equipment 310 can be used to form reference patterns, such as... Figure 4A , Figure 5 , Figure 6 , Figure 7 or Figure 8 The patterns 121a, 121b, 121c, 160a, or 160b are shown in the figures. The manufacturing apparatus 310 can be used to form patterns on the back surface of the wafer as part of the overlay markings.

[0142] Manufacturing equipment 320-1, ..., and 320-N can be used in the front layer, for example Figure 3A An element or feature is formed between the pattern 111 shown and the substrate. Each of the manufacturing equipment 320-1, ..., and 320-N can be used to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process, or other processes.

[0143] Manufacturing equipment 330 can be used to form patterns in a front layer, for example Figure 5 The pattern 111 shown is illustrated. In some embodiments, the manufacturing apparatus 330 can be used to form an isolation structure, a gate structure, a conductive via, or other layers. The pattern of the front layer may include a dielectric material, a semiconductor material, or a conductive material.

[0144] Manufacturing equipment 340-1, ..., and 340-N can be used to form an intermediate structure, for example... Figure 4A The intermediate structure 130 shown. Each of the manufacturing equipment 340-1, ..., and 340-N can be used to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process, or other processes.

[0145] Exposure equipment 350 can be used to form a pattern on a single layer, such as Figure 3B and Figure 4A The patterns 112 and 122 are displayed respectively.

[0146] In some embodiments, an optical image of the patterns of the front layer and the current layer can be obtained using the overlay measurement device 360, and a first overlay error can be generated based on the optical images of the patterns of the front layer and the current layer (e.g., patterns 111 and 112). In some embodiments, a second overlay error can be generated using the overlay measurement device 360 ​​based on a reference pattern and a pattern in the current layer (e.g., patterns 121 and 122).

[0147] The overlay correction system 370 may include correction parameters for generating corrected first and second overlay errors. The overlay correction system 370 may include, for example, a computer or server. In some embodiments, each of the corrected first and second overlay errors may be generated or calculated by program code or a programming language. For example, the corrected first overlay error may be determined by a first overlay error obtained from the overlay measurement device 360 ​​and the correction parameters of the overlay correction system 370. In some embodiments, a deviation in the X direction (ΔX), a deviation in the Y direction (ΔY), or a combination thereof, may be generated from the correction parameters. Each deviation in the X direction (ΔX), the deviation in the Y direction (ΔY), or a combination thereof, may be expressed by a formula that includes the correction parameters as variables. In some embodiments, the overlay correction system 370 may receive optical image information from a pattern (or reference pattern) of the previous layer and a pattern of the current layer, and then generate an X-direction deviation (ΔX), a Y-direction deviation (ΔY), or a combination thereof, to compensate for the first and second overlay errors obtained from the overlay measurement device 360.

[0148] Network 380 can be the Internet or an internal network using network communication protocols such as Transmission Control Protocol (TCP). Through network 380, each manufacturing device 310, 320-1, ..., 320-N, 330, 340-1, ..., 340-N, exposure device 350, and stacked measurement device 360 ​​can download or upload work-in-process (WIP) information about wafers or manufacturing equipment from controller 390.

[0149] The controller 390 may include a processor, such as a central processing unit (CPU). In some embodiments, the controller 390 may be used to generate instructions on whether to adjust the exposure apparatus 350 based on a first overlay error and a second overlay error.

[0150] although Figure 9 No other manufacturing equipment is shown preceding manufacturing equipment 310, but this exemplary embodiment is not intended to be limiting. In other exemplary embodiments, various manufacturing equipment may be arranged preceding manufacturing equipment 310 and may be used to perform various processes depending on design requirements.

[0151] In an exemplary embodiment, wafer 301 is transferred to manufacturing equipment 310 to initiate a series of different processes. Wafer 301 may form at least one layer of material through various stages of the process. The exemplary embodiment is not intended to limit the processes of wafer 301. In other exemplary embodiments, wafer 301 may include various layers, or any stage between the start and finish of a product, prior to being transferred to manufacturing equipment 310. In an exemplary embodiment, wafer 301 may be processed sequentially by manufacturing equipment 310, 320-1, ..., and 320-N, 330, 340-1, ..., and 340-N, exposure equipment 350, and stacked measurement equipment 360.

[0152] Figure 10 This is a flowchart illustrating preparation method 400 for the overlay markings of various aspects of this disclosure.

[0153] Fabrication method 400 begins with operation 410, in which a substrate is provided. The substrate may have a first surface and a second surface opposite to the first surface. The first surface may also be referred to as the back surface. The second surface may also be referred to as the active surface, on which active features, such as a gate structure or a wire connected to input and output terminals, are formed.

[0154] The fabrication method 400 continues with operation 420, wherein a first pattern is formed on a first surface of the substrate. In some embodiments, the first pattern may be a polysilicon layer on the first surface of the substrate. In some embodiments, the first pattern may be a groove on the first surface of the substrate. In some embodiments, the first pattern may be a groove in a polysilicon layer formed on the first surface of the substrate. In some embodiments, the fabrication method 400 may include forming a polysilicon layer on the first surface of the substrate and then patterning the polysilicon layer to form the first pattern. In some embodiments, the remainder of the polysilicon layer may be used to define the first pattern. In some embodiments, a groove or an opening in the polysilicon layer may be used to define the first pattern. In some embodiments, the fabrication method 400 may include removing a portion of the substrate from the first surface of the substrate to form a groove as the first pattern. The first pattern may be, for example, formed by... Figure 9 The manufacturing equipment 310 shown is formed.

[0155] Preparation method 400 continues to operation 430, wherein a second pattern is formed on a second surface of the substrate. The second pattern may include the same material as the isolation feature, gate structure, or conductive via. The second pattern can be formed by a process used to form the isolation feature, gate structure, or conductive via. For example, the second pattern may be made of… Figure 9 The manufacturing equipment 330 shown is formed.

[0156] The fabrication method 400 continues with operation 440, wherein an intermediate structure is formed to cover the second pattern. The intermediate structure may include one or more intermediate layers made of an insulating material, such as silicon oxide or silicon nitride. The intermediate structure may include conductive features formed in a dielectric layer. In some embodiments, the intermediate structure may be formed by CVD, PVG, ALD, dry etching, wet etching, CMP, or photolithography processes. The intermediate structure may be formed by, for example... Figure 9 The manufacturing equipment 340-1, ..., and 340-N shown are formed.

[0157] The fabrication method 400 continues with operation 450, wherein a third pattern is formed to be perpendicularly aligned with the second pattern, and a fourth pattern is formed to be perpendicularly aligned with the first pattern. In some embodiments, the third and fourth patterns may be openings in a mask, such as a photoresist layer. In some embodiments, operation 450 may include, for example, forming a photoresist layer on an intermediate structure, exposing the photoresist layer to a pattern through a mask, baking and developing the photoresist to form the mask third and fourth patterns. The third and fourth patterns may at least be formed by... Figure 9 The exposure device 350 shown is formed.

[0158] The second and third patterns can be used together to generate a first overlay error for measuring the offset between the preceding and current layers. The first and fourth patterns can be used collaboratively to generate a second overlay error to determine whether an anomaly in the first overlay error is caused by misalignment between the preceding and current layers. The first, second, third, and fourth patterns can be used together to measure the degree of wafer warpage.

[0159] Figure 11 This is a flowchart illustrating the method 500 for overlay correction of various aspects of this disclosure.

[0160] The method begins with operation 510, in which a first overlay mark and a second overlay mark are provided. The first overlay mark may include... Figure 3 The overlay mark 110 shown may include a first pattern (e.g., pattern 111) on a front layer and a second pattern (e.g., pattern 112) on a current layer. The second overlay mark may include... Figure 4 The overlay mark 120 is shown. The second overlay mark may include a third pattern (e.g., pattern 121) and a fourth pattern (e.g., pattern 122) of the layer. In some embodiments, the second and fourth patterns may be formed by an exposure device (e.g., exposure device 350).

[0161] The method continues with operation 520, wherein a first overlay error is generated based on a first overlay mark, and a second overlay error is generated based on a second overlay mark. In some embodiments, an optical image can be obtained from an overlay measuring device (e.g., overlay measuring device 360). The overlay error can be generated based on the optical image. The first overlay error can be calculated based on a first pattern and a second pattern. The second overlay error can be calculated based on a third pattern and a fourth pattern. In some embodiments, operation 520 may further include correcting the first and second overlay errors by an overlay correction system (e.g., overlay system 370).

[0162] The method continues with operation 530, in which a first determination is performed to determine whether a first overlay error is abnormal. In some embodiments, the overlay measurement device may transmit a signal of the first overlay error via a network (e.g., network 380) to a controller (e.g., controller 390), and the controller may compare the first overlay error with a target first overlay error. In some embodiments, the target first overlay error may be predetermined based on semiconductor process requirements. In some embodiments, the controller may include a determination module (not shown) to perform operation 530. In some embodiments, when the first overlay error exceeds the target first overlay error, it may be determined that the first overlay error is abnormal.

[0163] Next, based on the first determination of operation 530, operation 540 or operation 550 is performed. In some embodiments, when there is no abnormality in the first overlay error, the next exposure process can be performed using the exposure equipment without adjusting the exposure equipment, as shown in operation 540.

[0164] In some embodiments, when the first overlay error is abnormal, a second measurement is performed to determine whether the second overlay error is abnormal, as shown in operation 550. In some embodiments, the overlay measurement device may send a signal of the second overlay error to the controller, which may then compare the second overlay error with a target second overlay error. In some embodiments, the target second overlay error may be predetermined based on semiconductor process requirements. In some embodiments, a determination module of the controller may perform operation 550. In some embodiments, when the second overlay error exceeds the target second overlay error, it may be determined that the second overlay error is abnormal.

[0165] Next, based on the determination in operation 550, operation 560 or operation 570 is performed. In some embodiments, when the second stacking error is not abnormal, it can be determined that wafer warpage did not cause the first stacking error to be abnormal. In this case, the exposure equipment can be adjusted and then used to perform the next exposure process, as shown in operation 560.

[0166] In some embodiments, when the second stacking error is abnormal, it can be determined that wafer warping caused the abnormality of the first stacking error. The next exposure process can be performed using the exposure equipment without adjusting the exposure equipment, as shown in operation 570.

[0167] In some embodiments, the anomaly of the first overlay error is not caused by misalignment of the preceding and current layers, but by wafer warping. If the exposure apparatus is adjusted solely based on the first overlay error, the next wafer will suffer from misalignment of the current and preceding layers due to inaccurate adjustment of the exposure apparatus. To avoid this, a second overlay error can be used to determine whether the anomaly in the first overlay error is caused by wafer warping rather than misalignment of the preceding and current layers. By measuring the two overlay marks in two steps, inaccurate adjustment of the exposure apparatus can be prevented. Therefore, the uptime of the exposure apparatus can be improved.

[0168] Figure 10 and Figure 11 The process described herein can be implemented in controller 390, or in a computing system that organizes wafer fabrication by controlling each or part of the manufacturing equipment in the facility. Figure 12 This is a diagram illustrating the hardware of a semiconductor fabrication system 600 according to various aspects of this disclosure. System 600 includes one or more hardware processors 601 and a non-transitory computer-readable storage medium 603 encoded with, i.e., storing, program code (i.e., a set of executable instructions). The computer-readable storage medium 603 may also be encoded with instructions for interfacing with manufacturing equipment used to produce semiconductor equipment. Processor 601 is electrically connected to computer-readable storage medium 603 via bus 605. Processor 601 is also electrically coupled to input and output (I / O) interface 607 via bus 605. Network interface 609 is also electrically connected to processor 601 via bus 605. The network interface is connected to a network, thus enabling processor 601 and computer-readable storage medium 603 to be connected to external components via network 380. Processor 601 is configured to execute computer program code encoded in computer-readable storage medium 605, thereby enabling system 600 to perform operations such as... Figure 10 and Figure 11 Some or all of the operations described in the method shown.

[0169] In some exemplary embodiments, processor 601 is, but is not limited to, a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit. Various circuits or units are within the scope of this disclosure.

[0170] In some exemplary embodiments, the computer-readable storage medium 603 is, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 603 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random access memory (RAM), a read-only memory (ROM), a hard disk, and / or an optical disc. In one or more exemplary embodiments using an optical disc, the computer-readable storage medium 603 also includes an optical disc-read-only memory (CD-ROM), an optical disc-read / write (CD-R / W), and / or a digital video optical disc (DVD).

[0171] In some exemplary embodiments, storage medium 603 stores storage configured to enable system 600 to perform Figure 10 and Figure 11 The computer program code for the method shown. In one or more exemplary embodiments, storage medium 601 also stores the execution... Figure 10 and Figure 11 The information required for the methods described herein, as well as the information generated during the execution of these methods and / or the execution thereof. Figure 10 and Figure 11 The method described herein is a set of executable instructions for operation. In some exemplary embodiments, a user interface 610, such as a graphical user interface (GUI), may be provided to the user so that the user can operate on the system 600.

[0172] In some exemplary embodiments, storage medium 603 stores instructions for interfacing with an external machine. These instructions enable processor 601 to generate instructions readable by the external machine for efficient execution during analysis. Figure 10 and Figure 11 The method described in the text.

[0173] System 600 includes an input and output (I / O) interface 607. The I / O interface 607 is connected to external circuitry. In some exemplary embodiments, the I / O interface 607 may include, but is not limited to, a keyboard, keypad, mouse, trackball, tracepad, touchscreen, and / or cursor arrow keys, for transmitting information and commands to processor 601.

[0174] In some exemplary embodiments, the I / O interface 607 may include a display, such as a cathode ray tube (CRT), a liquid crystal display (LCD), a speaker, etc. For example, the display shows information.

[0175] System 600 may also include a network interface 609 coupled to processor 601. Network interface 609 allows system 600 to communicate with network 380, through which one or more other computer systems are connected. For example, system 600 may connect via network interface 609 to manufacturing equipment 310, 320-1, ..., 320-N, 330, 340-1, ..., and 340-N, exposure equipment 350, and stacked measurement equipment 360.

[0176] One aspect of this disclosure provides an overlay correction mark. The mark includes a first pattern and a second pattern. The first pattern is disposed on a first surface of a substrate. The second pattern is disposed on a second surface of the substrate, the second surface of the substrate being opposite to the first surface of the substrate. The first pattern overlaps at least a portion of the second pattern, and the first pattern and the second pattern together define a first overlay error.

[0177] Another aspect of this disclosure provides an overlay correction mark. The mark includes a first overlay mark and a second overlay mark. The first overlay mark includes a first pattern and a second pattern disposed on a first surface of a substrate. The first overlay mark is used to generate a first overlay error. The second overlay mark includes a third pattern disposed on a second surface of the substrate and a fourth pattern disposed on the first surface of the substrate. The first surface of the substrate is opposite to the second surface of the substrate. The second overlay mark is used to generate a second overlay error and to correct the first overlay error.

[0178] Another aspect of this disclosure provides a method for correcting overlay errors. The method includes generating a first overlay error based on a first overlay mark, wherein the first overlay error indicates a misalignment between a lower pattern and an upper pattern of the first overlay mark; and, in response to detecting an anomaly in the first overlay error, generating a second overlay error based on a second overlay mark, and determining, based on the second overlay error, whether the anomaly in the first overlay error is caused by the misalignment of the lower pattern and the upper pattern.

[0179] Another aspect of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate having a first surface and an opposing second surface; forming a first pattern on the first surface of the substrate; forming a second pattern on the second surface of the substrate; forming an intermediate structure covering the second pattern; forming a third pattern on the second surface of the substrate; wherein the second pattern and the third pattern together define a first overlay error; and forming a semiconductor device on the substrate.

[0180] A fourth pattern is formed on the second surface of the bottom, wherein the first pattern and the fourth pattern together define a second overlay error.

[0181] Embodiments of this disclosure provide overlay markers for measuring overlay error. Two overlay markers can be used to determine whether an anomaly in the overlay error is caused by misalignment between the current and previous layers, or by wafer warping. The two measurement steps using the two overlay markers prevent inaccurate adjustments of the exposure equipment. Therefore, the uptime of the exposure equipment can be increased.

[0182] 0 Although this disclosure and its advantages have been detailed, it should be understood that other changes, substitutions, and modifications may be made.

[0183] Alternatives may be made without departing from the concept and scope of this disclosure as defined by the published claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0184] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the disclosed claims of this disclosure.

Claims

1. A method for correcting overlay error, comprising: A first overlay error is generated based on a first overlay mark, wherein the first overlay error indicates a misalignment between a lower pattern and an upper pattern of the first overlay mark; as well as In response to an anomaly in detecting this first overlay error: A second overlay error is generated based on the displacement between a first pattern and a second pattern of a second overlay mark; The first pattern is disposed on a first surface of a substrate, the second pattern is disposed on a second surface of the substrate, and the first surface of the substrate is opposite to the second surface of the substrate; as well as Based on the second overlay error, determine whether the anomaly of the first overlay error is caused by the misalignment between the lower pattern and the upper pattern.

2. The correction method as claimed in claim 1, wherein the second pattern and the upper pattern are located on the same horizontal level.

3. The correction method as claimed in claim 1, wherein the second pattern at least overlaps with the first pattern.

4. The correction method as claimed in claim 1, wherein the contour of the first pattern and the contour of the second pattern are homomorphic in a plan view.

5. The correction method as claimed in claim 1, wherein the lower pattern and the upper pattern do not overlap.

6. The correction method as described in claim 1, further comprising: Determine whether the second overlay error is abnormal, and determine whether the lower pattern and the upper pattern are misaligned.

7. The correction method of claim 1, wherein the first overlay error and the second overlay error are shared to determine whether the anomaly of the first overlay error is caused by wafer warping.

8. A method for fabricating a semiconductor element, comprising: A substrate is provided having a first surface and a second surface opposite thereto; A first pattern is formed on the first surface of the substrate; A second pattern is formed on the second surface of the substrate; An intermediate structure is formed to cover the second pattern; A third pattern is formed on the second surface of the substrate, wherein the second pattern and the third pattern together define a first overlay error; and A fourth pattern is formed on the second surface of the substrate, wherein the displacement between the first pattern and the fourth pattern together defines a second overlay error.

9. The preparation method according to claim 8, wherein a contour of the first pattern and a contour of the fourth pattern are identical.

10. The preparation method of claim 8, wherein forming the first pattern comprises: A layer is formed on the first surface of the substrate; as well as The layer is patterned to form a first pattern.

11. The preparation method of claim 8, wherein forming the first pattern comprises: A portion of the substrate is removed to form a groove recessed from the first surface of the substrate, wherein the groove serves as the first pattern.

12. The preparation method of claim 8, wherein forming the first pattern comprises: A layer is formed on the first surface of the substrate; as well as A portion of the layer is removed to form a groove, which serves as the first pattern.

Images