A networkable high-precision data acquisition monitoring system and method

Abstract

The application relates to a networkable high-precision data acquisition monitoring system and method, which is constructed based on a PDA host computer, a switch, a main device and multiple slave devices, and meanwhile, the devices adopt a DSP+FPGA+ARM architecture to respectively perform original data acquisition, secondary data acquisition and timing control and transmission control of Ethernet communication, the file memory mapping technology and a reasonable multithreading scheduling method are used in the data acquisition monitoring method, the high-load problem of the PDA host computer software caused by high-speed data acquisition is solved, the high-precision data synchronization scheme of the system is used to solve the data asynchronization problem of the devices after networking with different running periods, and the networkable high-precision data acquisition monitoring is realized.

Description

Technical Field

[0001] This invention belongs to the field of data acquisition and analysis, and in particular to a networkable high-precision data acquisition and monitoring system and method. Background Technology

[0002] Process data acquisition (PDA) devices are primarily used to display internal process data, store and replay historical data from production equipment, meeting the needs of real-time monitoring and management of field equipment status, system debugging, and fault diagnosis and analysis. This facilitates equipment maintenance management, rapid debugging, and reduces fault handling time. Because modern electric drive systems have very short dynamic response times, the real-time requirements for related information equipment are high. For example, with a torque response time of 5–10 ms, PDA devices need to have a sampling period of <= 1 ms; otherwise, the recorded signal waveforms will be distorted, making observation and analysis impossible. Simultaneously, they require high-speed synchronous acquisition capabilities from multiple devices and multiple signal channels to accurately analyze and compare the physical relationships between various signals.

[0003] PDA data acquisition software systems not only need to address the high program load caused by high-speed acquisition, but also the issue of synchronizing multiple signals from different devices. Since different devices have varying response times and clock references, it is crucial to resolve data asynchrony issues when connecting multiple devices and ensure no error accumulation occurs after prolonged software operation. Currently, some methods exist for handling data synchronization, but most are hardware-based, lacking a comprehensive, high-precision data synchronization and acquisition solution. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and propose a networkable high-precision data acquisition and monitoring system and method that can solve the problems of high program load caused by high-speed acquisition and high-precision data synchronization of multiple networked devices.

[0005] The technical problem solved by this invention is achieved through the following technical solution:

[0006] A networkable high-precision data acquisition and monitoring system includes a PDA host computer, a switch, a master device, and multiple slave devices. The PDA host computer is connected to the switch via a network cable, and the switch is connected to the master device and multiple slave devices via network cables. The PDA host computer is used for parameter setting, start / stop control, data reception, storage, and plotting, while the master device and multiple slave devices are used for data acquisition.

[0007] Furthermore, both the master device and the slave device include an FPGA and a DSP and an ARM connected to it. The ARM is connected to a switch via a network cable for Ethernet communication transmission control, the DSP is used for raw data acquisition, and the FPGA is used for secondary data acquisition and timing control. The TX port in the FPGA of the preceding device is connected to the RX port in the FPGA of the following device to realize the high-precision synchronous data acquisition function of multiple devices.

[0008] Furthermore, the FPGA, ARM, and DSP communicate via a parallel port. The FPGA and DSP share a 33-word parallel port space, with 32 words used for the DSP to write raw data and 1 word for the DSP to write a flag bit. The FPGA and ARM share a 1026-word parallel port space, with two 512-word blocks used for the FPGA to write secondary acquisition data, 1 word for the ARM to write the sampling period, and 1 word for the FPGA to write the packet number. The ARM and DSP share a 112-word parallel port space for protocol communication.

[0009] A data acquisition and monitoring method for a networkable high-precision data acquisition and monitoring system includes a PDA host computer processing method and a multi-device high-precision synchronous acquisition method.

[0010] Moreover, the PDA host computer processing method is as follows: file memory mapping and multi-threaded processing are performed. The PDA host computer threads include: data receiving thread, intermediate buffer thread, drawing refresh thread, main thread and file compression thread. The data receiving thread is used to receive data packets uploaded by the device and store the data in the array buffer.

[0011] The intermediate cache thread is used to copy data from the array cache to the memory-mapped file, while simultaneously moving the uncopied data in the array cache forward and processing the new data in the memory-mapped file.

[0012] The plotting refresh thread is used to retrieve the raw data corresponding to the curve from the memory-mapped file according to the time range displayed on the oscilloscope, compare the data according to the upper limit of the number of curve points, and finally add the result to the plotting buffer to draw the waveform.

[0013] The main thread is used for user operations and automatic file saving;

[0014] The file compression thread is used to compress the original data file, and then deletes the original file after completion.

[0015] Furthermore, the specific implementation method for performing file memory mapping and multi-threaded processing of threads is as follows:

[0016] (1) Adopt the array cache + memory-mapped file mode to synchronize data reception with drawing refresh, file saving or user operation;

[0017] (2) The data receiving thread is only used to store data in the array cache, and the intermediate cache thread processes the data; the data storage is put into the main thread, and the file compression is put into the sub-thread.

[0018] (3) The data receiving thread has the highest execution frequency and does not have a sleep function set; the minimum single-path copy size of the intermediate buffer thread is S, the data volume corresponds to a duration between 500 and 1000 ms, and the sleep time is set between 100 and 500 ms. in This indicates rounding down, S is the data copy limit, and T is the data sampling period; the sleep time of the drawing refresh thread is set between 500 and 1000 ms.

[0019] (4) Use critical sections to prevent simultaneous access to shared data such as array caches and memory-mapped files; use flags to control user operations, allowing the next operation to proceed after the previous one has finished.

[0020] Furthermore, the multi-device high-precision synchronous acquisition method includes the following steps:

[0021] Step 1: The device is powered on, and the ARM sends the sampling period to the FPGA. The sampling period is 0.

[0022] Step 2: Use the PDA host computer to establish a connection with the master device and multiple slave devices, and set the sampling parameters and a uniform sampling period for each device;

[0023] Step 3: Start the oscilloscope. The PDA host computer polls all devices and sends sampling parameters and sampling period. The ARM receives the sampling parameters and sampling period, checks the configuration information, and if the check is correct, informs the DSP of the sampling parameters, informs the FPGA of the sampling period, and replies to the host computer. The host computer delays for 500ms after receiving the replies from all devices.

[0024] Step 4: After the DSP parses the sampling parameters, it informs the FPGA that the configuration is complete. Then, the DSP writes the raw data to the parallel port address DNF according to its operating cycle.

[0025] Step 5: After receiving the signal from the DSP, the FPGA waits for the master device signal. The master device starts fiber optic communication after a 100ms delay. The master device FPGA sends fiber optic signals according to the sampling period. During the entire sampling process, the master device FPGA takes the transmitted signal as the standard and the slave device FPGA takes the received signal as the standard. Data is read from the parallel port address DNF and written into the oscilloscope buffer.

[0026] Step 6: The data in one oscilloscope buffer is a packet of data. Each packet of data has a corresponding packet number. The packet number information is contained in the fiber optic protocol. The packet number of the data of each device at the same time must be the same. After the FPGA fills one oscilloscope buffer, it increments the packet number by 1. Each time the ARM is interrupted, it determines whether to read the data based on the packet number.

[0027] Step 7: After the PDA host computer finishes its delay, it broadcasts an oscilloscope start command. The broadcast command reaches each device simultaneously. After receiving the command, the ARM starts uploading. The ARM reads the packet number and the data in an oscilloscope buffer, encapsulates it according to the protocol, and sends it to the host computer.

[0028] Step 8: The host computer processes the data;

[0029] Step 9: The PDA host computer sends a stop sampling command. The ARM sets the sampling period to zero. The FPGA detects this and stops sampling, and resets the packet number to zero, thus ending the sampling process.

[0030] Furthermore, step 8 includes the following steps:

[0031] Step 8.1: The PDA host computer ensures that the packet number of the first packet data is consistent. If N is the maximum value of the first packet number of all devices, when the packet number of the latest packet data of all devices is not less than N, the packet number is aligned and all data with packet numbers less than N is discarded.

[0032] Step 8.2: The host computer performs packet loss processing. When the host computer detects that the data packet number sent by a certain device is not continuous, it skips the length corresponding to the lost data and saves the data in the correct position.

[0033] Step 8.3: At midnight every day, the program resets the PC time corresponding to the data.

[0034] The advantages and positive effects of this invention are:

[0035] 1. This invention constructs a networkable high-precision data acquisition and monitoring system based on a PDA host computer, a switch, a master device, and multiple slave devices. The devices employ a DSP+FPGA+ARM architecture to perform raw data acquisition, secondary data acquisition, timing control, and Ethernet communication transmission control. This invention utilizes file memory mapping technology and a reasonable multi-threaded scheduling method in its data acquisition and monitoring approach to solve the high load problem on the PDA host computer software caused by high-speed data acquisition. Furthermore, the system's high-precision data synchronization scheme solves the data asynchrony problem after networking devices with different operating cycles, thereby realizing a networkable high-precision data acquisition and monitoring function.

[0036] 2. This invention supports a network of up to 255 devices, with a maximum of 32 channels per device and up to 480 channels across all devices for simultaneous monitoring, and a custom sampling period of 1 to 20 ms.

[0037] 3. This invention uses multi-threading technology and file memory mapping technology to ensure that the program can quickly receive, store and access data, thus ensuring the smooth and stable operation of the program under high load caused by high-speed acquisition.

[0038] 4. This invention does not require a DA box, an oscilloscope, or expensive monitoring software, effectively reducing the overall cost of the product, enhancing the core competitiveness of independently developed products, and facilitating the promotion and application of the product. Attached Figure Description

[0039] Figure 1 This is a system structure block diagram of the present invention;

[0040] Figure 2 This is a schematic diagram showing the communication scheme and space allocation between the FPGA, ARM, and DSP in the device of the present invention.

[0041] Figure 3 This is a schematic diagram of the multi-threaded processing of the present invention;

[0042] Figure 4 This is a waveform diagram of the actual data collected by multiple devices according to the present invention;

[0043] Figure 5 This is a flowchart of the multi-device high-precision synchronous acquisition method of the present invention. Detailed Implementation

[0044] The present invention will be further described in detail below with reference to the accompanying drawings.

[0045] A networkable high-precision data acquisition and monitoring system, such as Figure 1 As shown, it includes a PDA host computer, a switch, a master device, and multiple slave devices. The PDA host computer uses UDP communication via Ethernet to connect to the switch through a network cable. The switch connects to the master device and multiple slave devices through network cables, supporting a maximum of 255 devices connected simultaneously. The PDA host computer is used for parameter setting, start / stop control, data reception, storage, and plotting, while the master device and multiple slave devices are used for data acquisition.

[0046] The system consists of only one master device and the rest are slave devices. The FPGAs of multiple devices are connected in series via high-speed optical fiber, starting from the master device. Fiber optic communication features high speed, high accuracy, and strong anti-interference capabilities. Precise clock control is employed, with a master-slave clock deviation of less than 200ns and a communication bit error rate of less than 10E-10.

[0047] Both the master and slave devices include DSP, FPGA, and ARM. The ARM is connected to the switch via a network cable. The TX port of the FPGA in the preceding device is connected to the RX port of the FPGA in the following device. The DSP is used for raw data acquisition, the FPGA is used for secondary data acquisition and timing control, and the ARM is used for Ethernet communication transmission control.

[0048] like Figure 2 As shown, the FPGA, ARM and DSP communicate via parallel port. The oscilloscope buffer (1024 words), buffer full flag (1 word), and sampling period (1 word) are shared by the FPGA and ARM. The communication protocol (112 words) is shared by the ARM and DSP. The oscilloscope data preparation flag (1 word) and DNF (32 words) are shared by the FPGA and DSP.

[0049] A data acquisition and monitoring method for a networkable high-precision data acquisition and monitoring system includes a PDA host computer processing method and a multi-device high-precision synchronous acquisition method.

[0050] When the PDA host computer software is acquiring data at high speed (with 480 channels and a sampling period of 1ms, the maximum load is about 940KB / s), how can it arrange multiple tasks such as data reception, data storage, curve display, file storage, and user operation to ensure that the data acquisition, storage, and display are correct and error-free, that the user experience is smooth, and that the software can run stably for a long time?

[0051] To address the aforementioned problems, this invention employs file memory mapping and multi-threaded processing. The file memory mapping technology maps a file to the process address space, allowing data within the file to be accessed using memory read / write instructions, thereby significantly improving file read / write speed.

[0052] The threads used in the system's data processing include: data receiving thread, intermediate buffer thread, drawing refresh thread, main thread, and file compression thread.

[0053] The data receiving thread is used to receive data packets uploaded by the device and store the data in an array cache.

[0054] The intermediate cache thread is used to copy data from the array cache to the memory-mapped file, while also moving the uncopied data in the array cache forward and processing the new data in the memory-mapped file, such as calculating virtual channels.

[0055] The plotting refresh thread is used to retrieve the raw data corresponding to the curve from the memory-mapped file according to the time range displayed on the oscilloscope, compare the data according to the upper limit of the number of curve points, and finally add the result to the plotting buffer to draw the waveform.

[0056] The main thread is used for user operations and automatic file saving. User operations are designed conventionally, with the human-computer interaction handled in the main thread. During data acquisition, users can mainly perform graphical operations, including waveform scaling, dragging, setting ranges, and cursor positioning. Automatic file saving occurs when the amount of data in the memory-mapped file reaches a set value. The system writes the data and channel attribute information to the file and checks the remaining disk space in the storage path. If space is insufficient, old files are automatically deleted to ensure the program runs automatically for a long time.

[0057] The file compression thread is used to compress the original data file using RAR, and then deletes the original file after completion.

[0058] For a program to run efficiently, it is necessary to allocate tasks to each thread appropriately and to perform thread scheduling and synchronization effectively, such as... Figure 3 As shown, the specific implementation method for file memory mapping and multi-threaded processing is as follows:

[0059] (1) The mode of using two cache areas (array cache + memory-mapped file) allows data reception and drawing refresh, file saving or user operation to be executed simultaneously without affecting each other.

[0060] (2) Both the data receiving thread and the intermediate buffer thread are threads that perform raw data processing. However, the data receiving thread is executed very frequently (when T = 1ms, the device uploads 1 packet of data every 16ms, that is, if there are n devices in the network, the host computer executes the data receiving thread once every 16 / n ms on average). Therefore, the data receiving thread is only responsible for storing the data in the array buffer, and all further data processing is handled by the intermediate buffer thread.

[0061] File storage is a critical task, so it is placed in the main thread; while file compression not only takes a long time to process, but its purpose is only to save disk space, so it is placed in a sub-thread.

[0062] (3) By reasonably arranging the sleep time of threads, the system resources can be saved and the running efficiency can be maximized. For example, if the data receiving thread has the highest execution frequency, no sleep time is set; the minimum copy amount of a single intermediate cache thread is S (the data volume corresponds to a duration between 500 and 1000 ms), so the sleep time is set between 100 and 500 ms; the drawing refresh thread has the lowest priority, and the drawing data comes from a memory-mapped file, so the sleep time should not be less than the sleep time of the intermediate cache thread, so the sleep time is set between 500 and 1000 ms.

[0063] (4) Use critical sections to prevent simultaneous access to shared data such as array caches and memory-mapped files; use flags to control user operations, allowing the next operation to proceed only after the previous one has finished, thus preventing the program from running into an unknown state (because some user operations can cause the start / end of a thread).

[0064] like Figure 5 As shown, the multi-device high-precision synchronous acquisition method includes the following steps:

[0065] Step 1: Power on the device and the ARM sends the sampling period to the FPGA. The sampling period is 0.

[0066] Step 2: Use the PDA host computer to establish a connection with each device and set the sampling parameters and a uniform sampling period (1-20ms) for each device.

[0067] Step 3: Click Start. The PDA host computer polls all devices, sending sampling parameters and sampling period. The ARM receives the data, and if it checks and finds no errors, it informs the DSP of the sampling parameters, informs the FPGA of the sampling period, and replies to the host computer. After receiving replies from all devices, the host computer delays for 500ms (if the master device is the last one polled, allow sufficient time for its 100ms delay).

[0068] Step 4: After the DSP parses the sampling parameters, it informs the FPGA that the configuration is complete. Then, the DSP writes the raw data to the parallel port address DNF according to its operating cycle (the operating cycle of the DSP may be different for different devices).

[0069] Step 5: After receiving the signal from the DSP, the FPGA waits for the master device's signal. The master device initiates fiber optic communication after a 100ms delay. The master FPGA sends fiber optic signals according to the sampling period. Throughout the sampling process, the master FPGA prioritizes the transmitted signal, while the slave FPGA prioritizes the received signal. Data is read from the parallel port address DNF and written to the oscilloscope buffer. Figure 2 Note that the oscilloscope buffer has two sections. When the ARM reads data from region 1, the FPGA writes data to region 2, and the two regions are read and written alternately.

[0070] Step 6: A data packet in an oscilloscope buffer is a data unit, and each data packet has a corresponding packet number (0-65535). The packet number information is contained in the fiber optic protocol, so the packet number of data from different devices at the same time must be the same. After the FPGA fills an oscilloscope buffer, it increments the packet number by 1. Each time the ARM receives an interrupt (6ms cycle), it determines whether to read data based on the packet number.

[0071] Step 7: After the PDA host computer finishes its delay, it broadcasts a start command for the oscilloscope. Theoretically, the broadcast command reaches all devices simultaneously. Upon receiving it, the ARM starts uploading; that is, the ARM reads the packet number and data from an oscilloscope buffer, encapsulates it according to the protocol, and sends it to the host computer.

[0072] Step 8: The host computer processes the data.

[0073] Step 8.1: Due to the different ARM response times of various devices, the packet number of the first packet data may differ between devices. Therefore, after the oscilloscope is started, the host computer should ensure that the packet number of the first packet data is consistent.

[0074] Let N be the maximum value of the first packet number of all devices. Then, when the packet number of the latest packet data from all devices is not less than N, a packet number alignment operation can be performed, which simply involves discarding all data with packet numbers less than N. This alignment operation only needs to be performed once after the oscilloscope is started.

[0075] Step 8.2: The host computer performs packet loss handling. Ideally, the packet number of the data packets received by the PDA host computer from the device should change continuously from 0 to 65535 (the next packet after 65535 returns to 0). However, due to uncertainties such as electromagnetic interference, data packets may be lost. Therefore, the host computer adds a packet loss handling mechanism. When the host computer detects that the packet number of a data packet sent by a device is not continuous, it must skip the length corresponding to the lost data and save the data at the correct position. This ensures that the data is always synchronized.

[0076] Step 8.3, Time Calibration: The time of the first sampling point is deduced from the time the host computer receives the data packet. The times of subsequent sampling points are calculated based on the sampling period T, i.e., the time of the m-th sampling point = the time of the first point + (m-1)*T. This means the data time is actually set by the FPGA clock. Therefore, the time error between the FPGA and the host computer may gradually accumulate (theoretically, the error is approximately ±4 seconds / day, and the test result is approximately ±1 second / day). Therefore, at midnight every day, the program resets the PC time corresponding to the data to avoid discrepancies between the data time and the host computer time after prolonged operation.

[0077] Step 9: The PDA host computer sends a stop sampling command. The ARM sets the sampling period to zero. The FPGA detects this and stops sampling, and resets the packet number to zero, thus ending the sampling process.

[0078] According to the above data synchronization process, the FPGAs of different devices write data to the same buffer location based on the synchronization sampling signal, and the ARM assembles and transmits the data transparently. The host computer then stores the data according to the packet number, achieving high-precision data synchronization between different devices. Figure 4As shown in the actual data collection results from multiple devices, this invention controls the time error of data from different devices to be no more than 1 millisecond.

[0079] It should be emphasized that the embodiments described in this invention are illustrative rather than limiting. Therefore, this invention includes, but is not limited to, the embodiments described in the specific implementation. Any other implementations derived by those skilled in the art based on the technical solutions of this invention are also within the scope of protection of this invention.

Claims

1. A data acquisition and monitoring method for a networkable high-precision data acquisition and monitoring system, characterized in that: The system used includes a PDA host computer, a switch, a master device, and multiple slave devices. The PDA host computer is connected to the switch via a network cable, and the switch is connected to the master device and multiple slave devices via network cables. The PDA host computer is used for parameter setting, start / stop control, data reception, storage, and plotting, while the master device and multiple slave devices are used for data acquisition. Both the master device and the slave device include an FPGA and a DSP and an ARM connected to it. The ARM is connected to the switch via a network cable for Ethernet communication transmission control. The DSP is used for raw data acquisition. The FPGA is used for secondary data acquisition and timing control. The TX port in the FPGA of the preceding device is connected to the RX port in the FPGA of the following device to realize the high-precision synchronous data acquisition function of multiple devices. The FPGA, ARM, and DSP communicate via a parallel port. The FPGA and DSP share a 33-word parallel port space, with 32 words used for the DSP to write raw data and 1 word for the DSP to write a flag bit. The FPGA and ARM share a 1026-word parallel port space, with two 512-word blocks used for the FPGA to write secondary acquisition data, 1 word for the ARM to write the sampling period, and 1 word for the FPGA to write the packet number. The ARM and DSP share a 112-word parallel port space for protocol communication. This includes PDA host computer processing methods and multi-device high-precision synchronous acquisition methods; The PDA host computer processing method is as follows: file memory mapping and multi-threaded processing are performed. The PDA host computer threads include: data receiving thread, intermediate buffer thread, drawing refresh thread, main thread and file compression thread. The data receiving thread is used to receive data packets uploaded by the device and store the data in the array buffer. The intermediate cache thread is used to copy data from the array cache to the memory-mapped file, while simultaneously moving the uncopied data in the array cache forward and processing the new data in the memory-mapped file. The plotting refresh thread is used to retrieve the raw data corresponding to the curve from the memory-mapped file according to the time range displayed on the oscilloscope, compare the data according to the upper limit of the number of curve points, and finally add the result to the plotting buffer to draw the waveform. The main thread is used for user operations and automatic file saving; The file compression thread is used to compress the original data file, and then deletes the original file after completion. The specific implementation method for performing file memory mapping and multi-threaded processing is as follows: (1) Adopt the array cache + memory-mapped file mode to synchronize data reception with drawing refresh, file saving or user operation; (2) The data receiving thread is only used to store data in the array cache, and the intermediate cache thread processes the data; the data storage is put into the main thread, and the file compression is put into the sub-thread. (3) The data receiving thread has the highest execution frequency and does not have a sleep function set; the minimum single-path copy size of the intermediate buffer thread is S, the data volume corresponds to a duration between 500 and 1000 ms, and the sleep time is set between 100 and 500 ms. in This indicates rounding down, S is the data copy limit, and T is the data sampling period; the sleep time of the drawing refresh thread is set between 500 and 1000 ms. (4) Use critical sections to prevent simultaneous access to array caches and memory-mapped files; use flags to control user operations, allowing the next operation to proceed only after the previous one has finished.

2. The acquisition and monitoring method of a networkable high-precision data acquisition and monitoring system according to claim 1, characterized in that: The multi-device high-precision synchronous acquisition method includes the following steps: Step 1: The device is powered on, and the ARM sends the sampling period to the FPGA. The sampling period is 0. Step 2: Use the PDA host computer to establish a connection with the master device and multiple slave devices, and set the sampling parameters and a uniform sampling period for each device; Step 3: Start the oscilloscope. The PDA host computer polls all devices and sends sampling parameters and sampling period. The ARM receives the sampling parameters and sampling period, checks the configuration information, and if the check is correct, informs the DSP of the sampling parameters, informs the FPGA of the sampling period, and replies to the host computer. The host computer delays for 500ms after receiving the replies from all devices. Step 4: After the DSP parses the sampling parameters, it informs the FPGA that the configuration is complete. Then, the DSP writes the raw data to the parallel port address DNF according to its operating cycle. Step 5: After receiving the signal from the DSP, the FPGA waits for the master device signal. The master device starts fiber optic communication after a 100ms delay. The master device FPGA sends fiber optic signals according to the sampling period. During the entire sampling process, the master device FPGA takes the transmitted signal as the standard and the slave device FPGA takes the received signal as the standard. Data is read from the parallel port address DNF and written into the oscilloscope buffer. Step 6: The data in one oscilloscope buffer is a packet of data. Each packet of data has a corresponding packet number. The packet number information is contained in the fiber optic protocol. The packet number of the data of each device at the same time must be the same. After the FPGA fills one oscilloscope buffer, it increments the packet number by 1. Each time the ARM is interrupted, it determines whether to read the data based on the packet number. Step 7: After the PDA host computer finishes its delay, it broadcasts an oscilloscope start command. The broadcast command reaches each device simultaneously. After receiving the command, the ARM starts uploading. The ARM reads the packet number and the data in an oscilloscope buffer, encapsulates it according to the protocol, and sends it to the host computer. Step 8: The PDA host computer processes the data; Step 9: The PDA host computer sends a stop sampling command. The ARM sets the sampling period to zero. The FPGA detects this and stops sampling, and resets the packet number to zero, thus ending the sampling process.

3. The acquisition and monitoring method of a networkable high-precision data acquisition and monitoring system according to claim 2, characterized in that: Step 8 includes the following steps: Step 8.1: The PDA host computer ensures that the packet number of the first packet data is consistent. If N is the maximum value of the first packet number of all devices, when the packet number of the latest packet data of all devices is not less than N, the packet number is aligned and all data with packet numbers less than N is discarded. Step 8.2: The host computer performs packet loss processing. When the host computer detects that the data packet number sent by a certain device is not continuous, it skips the length corresponding to the lost data and saves the data in the correct position. Step 8.3: At midnight every day, the program resets the PC time corresponding to the data.

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