Method and device for determining topography defects in a simulation model of a semiconductor patterning process

CN116402778BActive Publication Date: 2026-06-09INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
Filing Date
2023-03-30
Publication Date
2026-06-09

AI Technical Summary

Technical Problem

Existing technologies have low efficiency in detecting and predicting morphological defects in semiconductor fabrication processes, resulting in insufficient process reliability and stability. Furthermore, experimental design methods are time-consuming and costly.

Method used

By using a semiconductor patterned process simulation model, the initial substrate structure and process condition data are obtained, simulation calculations are performed to determine the site rate of the surface contour, and the site rate is corrected inside the defect structure to output the morphological defect prediction results.

Benefits of technology

It enables efficient and accurate prediction of morphological defects, helps process development avoid substrate structure design defects, and improves the reliability and stability of the process.

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Abstract

The application discloses a method and device for determining a topographic defect in a semiconductor patterning process simulation model, and relates to the field of semiconductor device patterning process simulation. The method comprises the following steps: determining the position relationship between a plurality of sites and a corresponding defect structure in initial substrate structure data based on a profile site rate; in the case that the site is inside the defect structure, correcting the surface profile site rate of the site to obtain a corresponding corrected target surface profile site rate, and completing the correction of the process simulation model; and inputting current substrate structure data into the corrected process simulation model to output a corresponding topographic defect prediction result. The method can simulate and predict the topographic defect on any substrate structure in the process, determine whether a defect will occur on a new substrate structure, and how the defect topography is formed, thereby helping process development and avoiding substrate structure design defects.
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Description

Technical Field

[0001] This invention relates to the field of semiconductor device patterning process simulation, and in particular to a method and apparatus for determining morphological defects in a semiconductor patterning process simulation model. Background Technology

[0002] Patterning processes in semiconductor fabrication typically include thin film growth and deposition, etching, and photolithography. Various morphological defects can arise due to substrate surface defects, internal voids during film deposition or etching, and inappropriate process conditions. For example, in some etching reactions, a large amount of solid polymer in the byproducts cannot be removed quickly enough. As the reaction continues, these byproducts accumulate on the surface of the target material, hindering subsequent etching and causing a sharp decrease in the etching rate near the polymer accumulation area, thus blocking subsequent etching reactions. Similarly, during thin film deposition, the high adhesion coefficients of various vapor precursors can lead to poor conformal properties when depositing on non-planar substrates such as trenches or steps. As deposition progresses, voids often form within high aspect ratio structures. These morphological defects affect the execution of subsequent processes and the final device quality, and must be avoided as much as possible during the process.

[0003] Currently, the process industry mainly uses experimental design method to optimize existing processes and develop new processes. However, this process requires a large number of experiments, is very time-consuming and has high R&D costs. The industry urgently needs a more efficient way to develop processes. Existing experimental design method cannot efficiently, easily and stably detect and predict morphological defects, which reduces the reliability and stability of semiconductor imaging processes. Summary of the Invention

[0004] The purpose of this invention is to provide a method and apparatus for determining morphological defects in semiconductor patterned process simulation models. This addresses the problem that the current process industry mainly uses experimental design methods to optimize existing processes and develop new processes. However, this process requires a large number of experiments, is very time-consuming, and has high R&D costs. The industry urgently needs a more efficient way to develop processes. Existing experimental design methods cannot efficiently, easily, and stably detect and predict morphological defects, which reduces the reliability and stability of semiconductor patterned processes.

[0005] In a first aspect, the present invention provides a method for determining topographic defects in a semiconductor patterned process simulation model, the method comprising:

[0006] Acquire initial substrate structure data and initial process condition data;

[0007] The initial substrate structure data and initial process condition data of the process simulation model are used to perform simulation calculations to determine the rate of each surface profile site within each time step under the preset substrate structure and preset process conditions.

[0008] The positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data is determined based on the contour site rate.

[0009] When the location is inside the defect structure, the surface profile location rate of the location is corrected to obtain the corresponding corrected target surface profile location rate, thus completing the correction of the process simulation model.

[0010] The current substrate structure data is input into the modified process simulation model, and the corresponding morphological defect prediction results are output.

[0011] With the above technical solution, the method for determining morphological defects in a semiconductor patterned process simulation model provided in this application can acquire initial substrate structure data and initial process condition data; perform simulation calculations using the initial substrate structure data and initial process condition data in the process simulation model to determine the velocity of each surface contour site within each time step under the preset substrate structure and preset process conditions; determine the positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data based on the contour site velocity; when the site is inside the defect structure, correct the surface contour site velocity of the site to obtain the corresponding corrected target surface contour site velocity, thus completing the correction of the process simulation model; input the current substrate structure data into the corrected process simulation model and output the corresponding morphological defect prediction results. This method can simulate and predict morphological defects on any substrate structure during the process, determine whether defects will occur on the new structure substrate, and what the defect morphology will be, thereby helping process development and avoiding substrate structure design defects.

[0012] In one possible implementation, determining the positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data based on the contour site rate includes:

[0013] Edge extraction is performed on the initial substrate structure data and the surface contour site velocity to obtain the site coordinate matrix;

[0014] Traverse each point in the point coordinate matrix and determine the minimum distance between the two adjacent points before and after each current point;

[0015] The minimum spacing value is used to determine the spacing value between each current site and its two adjacent sites before and after it.

[0016] By traversing multiple sites, the positional relationship between the multiple sites and the defect structure is determined based on the site spacing value and the minimum spacing value corresponding to each site.

[0017] In one possible implementation, traversing each point in the point coordinate matrix and determining the minimum distance between two adjacent points for each current point includes:

[0018] Traverse each of the sites in a preset order to determine the first target site before each current site and the second target site after each current site;

[0019] Determine multiple target spacing values ​​between the first target site and the second target site;

[0020] The minimum value among the multiple target spacing values ​​is determined as the minimum spacing value between the two adjacent front and rear sites.

[0021] In one possible implementation, determining the site spacing value between each current site and its two adjacent sites based on the minimum spacing value includes:

[0022] The site spacing values ​​between the current site and the first and second target sites corresponding to the minimum spacing value are determined respectively.

[0023] In one possible implementation, the step of traversing multiple sites and determining the positional relationship between the multiple sites and the defect structure based on the site spacing value corresponding to each site and the minimum spacing value includes:

[0024] By traversing multiple sites, and based on the site spacing value and the minimum spacing value corresponding to each site, and in combination with a preset defect opening threshold, the positional relationship between the multiple sites and the defect structure is determined.

[0025] In one possible implementation, the step of traversing multiple sites and determining the positional relationship between the multiple sites and the defect structure based on the site spacing value corresponding to each site and the minimum spacing value includes:

[0026] By traversing multiple sites, and based on the site spacing value and the minimum spacing value corresponding to each site, the positional relationship between the multiple sites and the defect structure is determined by combining the preset macroscopic particle mean free path parameter.

[0027] In one possible implementation, when the site is located inside the defect structure, the surface profile site rate of the site is corrected to obtain the corresponding corrected target surface profile site rate, thereby completing the correction of the process simulation model, including:

[0028] When the location is inside the defect structure, the surface profile location rate of the location is corrected based on the rate correction relationship to obtain the corresponding corrected target surface profile location rate, thus completing the correction of the process simulation model.

[0029] In one possible implementation, after determining the positional relationship between the corresponding plurality of sites and the corresponding defect structures in the initial substrate structure data based on the contour site rate, the method further includes:

[0030] When the site is not located inside the defect structure, the surface profile site rate of the corresponding site is maintained as the current surface profile site rate.

[0031] In one possible implementation, the initial substrate structure data refers to the data corresponding to the micro-nano scale structure formed in the preceding process for subsequent deposition or etching processes;

[0032] The initial process condition data refers to the equipment process condition data required to perform deposition or etching.

[0033] Secondly, the present invention also provides a device for determining morphological defects in a semiconductor patterned process simulation model, the device comprising:

[0034] The acquisition module is used to acquire initial substrate structure data and initial process condition data;

[0035] The first determining module is used to perform simulation calculations using the initial substrate structure data and the initial process condition data from the process simulation model to determine the rate of each surface profile site within each time step under the preset substrate structure and preset process conditions.

[0036] The second determining module is used to determine the positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data based on the contour site rate.

[0037] The correction module is used to correct the surface profile site rate of the site when the site is inside the defect structure, so as to obtain the corresponding corrected target surface profile site rate and complete the correction of the process simulation model.

[0038] The output module is used to input the current substrate structure data into the corrected process simulation model and output the corresponding morphology defect prediction results.

[0039] In one possible implementation, the second determining module includes:

[0040] An edge extraction submodule is used to extract edges from the initial substrate structure data and the surface contour site rate to obtain a site coordinate matrix.

[0041] The first determining submodule is used to traverse each site in the site coordinate matrix and determine the minimum distance between the two adjacent sites before and after each current site.

[0042] The second determining submodule is used to determine the site spacing value between each current site and its two adjacent sites based on the minimum spacing value;

[0043] The third determining submodule is used to traverse multiple sites and determine the positional relationship between multiple sites and the defect structure based on the site spacing value and the minimum spacing value corresponding to each site.

[0044] In one possible implementation, the first determining submodule includes:

[0045] The first determining unit is configured to traverse each of the sites in a preset order and determine a first target site before each current site and a second target site after each current site.

[0046] The second determining unit is used to determine multiple target spacing values ​​between the first target site and the second target site;

[0047] The third determining unit is used to determine the minimum value among the plurality of target spacing values ​​as the minimum spacing value between the two adjacent front and rear sites.

[0048] In one possible implementation, the second determining submodule includes:

[0049] The fourth determining unit is used to determine the site spacing value between the current site and the first target site and the second target site corresponding to the minimum spacing value.

[0050] In one possible implementation, the third determining submodule includes:

[0051] The fifth determining unit is used to traverse multiple sites and, based on the site spacing value and the minimum spacing value corresponding to each site, determine the positional relationship between the multiple sites and the defect structure in combination with a preset defect opening threshold.

[0052] In one possible implementation, the third determining submodule includes:

[0053] The sixth determining unit is used to traverse multiple sites and, based on the site spacing value and the minimum spacing value corresponding to each site, determine the positional relationship between the multiple sites and the defect structure in combination with the preset macroscopic particle mean free path parameter.

[0054] In one possible implementation, the correction module includes:

[0055] The correction submodule is used to correct the surface contour site rate of the site based on the rate correction relationship when the site is inside the defect structure, so as to obtain the corresponding corrected target surface contour site rate and complete the correction of the process simulation model.

[0056] In one possible implementation, the device further includes:

[0057] A holding module is configured to maintain the surface profile site rate of the corresponding site at the current surface profile site rate when the site is not located inside the defect structure.

[0058] In one possible implementation, the initial substrate structure data refers to the data corresponding to the micro-nano scale structure formed in the preceding process for subsequent deposition or etching processes;

[0059] The initial process condition data refers to the equipment process condition data required to perform deposition or etching.

[0060] The beneficial effects of the topography defect determination device in the semiconductor patterned process simulation model provided in the second aspect are the same as those of the topography defect determination method in the semiconductor patterned process simulation model described in the first aspect or any possible implementation of the first aspect, and will not be repeated here. Attached Figure Description

[0061] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0062] Figure 1 This paper illustrates a flowchart of a method for determining morphological defects in a semiconductor graphical process simulation model provided in an embodiment of this application.

[0063] Figure 2 This paper illustrates a flowchart of another method for determining morphological defects in a semiconductor graphical process simulation model provided in an embodiment of this application.

[0064] Figure 3This illustration shows a structural diagram of an embodiment of the present application for predicting whether a trench substrate structure with different tilt angles will develop void defects.

[0065] Figure 4 This paper presents a schematic diagram of a device for determining morphological defects in a semiconductor graphical process simulation model provided in an embodiment of this application. Detailed Implementation

[0066] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0067] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0068] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0069] Patterning processes in semiconductor fabrication typically include thin film growth and deposition, etching, and photolithography. Various morphological defects can arise due to substrate surface defects, internal voids during film deposition or etching, and inappropriate process conditions. For example, in some etching reactions, a large amount of solid polymer in the byproducts cannot be removed quickly enough. As the reaction continues, these byproducts accumulate on the surface of the target material, hindering subsequent etching and causing a sharp decrease in the etching rate near the polymer accumulation area, thus blocking subsequent etching reactions. Similarly, during thin film deposition, the high adhesion coefficients of various vapor precursors can lead to poor conformal properties when depositing on non-planar substrates such as trenches or steps. As deposition progresses, voids often form within high aspect ratio structures. These morphological defects affect the execution of subsequent processes and the final device quality, and must be avoided as much as possible during the process.

[0070] Currently, the process industry mainly uses experimental design method to optimize existing processes and develop new processes. However, this process requires a large number of experiments, is very time-consuming and has high R&D costs. The industry urgently needs a more efficient way to develop processes. Existing experimental design method cannot efficiently, easily and stably detect and predict morphological defects, which reduces the reliability and stability of semiconductor imaging processes.

[0071] Therefore, modeling and simulating specific processes to assist in process development has gradually become a mainstream approach. From the perspective of large-scale manufacturing process development, the morphology simulation of feature dimensions at the micro-nano scale and the evolution behavior of structural contours during process development are areas of great interest to process engineers. In particular, the identification and prediction of morphological defects in the process model during contour evolution are especially important.

[0072] Figure 1 This document illustrates a flowchart of a method for determining morphological defects in a semiconductor graphical process simulation model, as provided in an embodiment of this application. Figure 1 As shown, the method for determining morphological defects in the semiconductor patterned process simulation model includes:

[0073] Step 101: Obtain initial substrate structure data and initial process condition data.

[0074] The initial substrate structure data refers to the data corresponding to the micro-nano scale structure formed in the preceding process for subsequent deposition or etching processes; the initial process condition data refers to the equipment process condition data required to perform deposition or etching.

[0075] After obtaining the initial substrate structure data and initial process condition data, proceed to step 102.

[0076] Step 102: Perform simulation calculations using the initial substrate structure data and the initial process condition data from the process simulation model to determine the rate of each surface profile site within each time step under the preset substrate structure and preset process conditions.

[0077] In this application, initial substrate structure data and initial process condition data can be substituted into the process simulation model. Through simulation calculation, the simulation results of deposition morphology or etching morphology contours at each time step under preset substrate structure and preset process conditions can be obtained. Specifically, it is expressed as the velocity of each surface contour site. If it is a deposition process, it is expressed as the deposition rate; if it is an etching process, it is expressed as the etching rate, denoted as R. i After performing simulation calculations using the initial substrate structure data and initial process condition data from the process simulation model to determine the rate of each surface profile site within each time step under the preset substrate structure and preset process conditions, step 103 is executed.

[0078] Step 103: Determine the positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data based on the contour site rate.

[0079] The specific implementation process of step 103 above may include the following sub-steps:

[0080] Sub-step S1: Extract the edges from the initial substrate structure data and the surface contour site velocity to obtain the site coordinate matrix;

[0081] Sub-step S2: Traverse each point in the point coordinate matrix and determine the minimum distance between the two adjacent points before and after each current point;

[0082] Sub-step S3: Determine the site spacing value between each current site and its two adjacent sites based on the minimum spacing value;

[0083] Sub-step S4: Traverse multiple sites, and determine the positional relationship between multiple sites and the defect structure based on the site spacing value and the minimum spacing value corresponding to each site.

[0084] After determining the positional relationship between the corresponding sites and the corresponding defect structures in the initial substrate structure data based on the contour site rate, step 104 is executed.

[0085] Step 104: When the site is inside the defect structure, the surface profile site rate of the site is corrected to obtain the corresponding corrected target surface profile site rate, thus completing the correction of the process simulation model.

[0086] In this application, when the site is located inside the defect structure, the surface contour site rate of the site is corrected based on the rate correction relationship to obtain the corresponding corrected target surface contour site rate, thereby completing the correction of the process simulation model.

[0087] When the site is located inside the defect structure, the surface profile site rate of the site is corrected to obtain the corresponding corrected target surface profile site rate. After the correction of the process simulation model is completed, step 105 is executed.

[0088] Step 105: Input the current substrate structure data into the corrected process simulation model and output the corresponding morphology defect prediction results.

[0089] In summary, the method for determining morphological defects in a semiconductor patterned process simulation model provided in this application can acquire initial substrate structure data and initial process condition data; perform simulation calculations using the initial substrate structure data and initial process condition data in the process simulation model to determine the velocity of each surface contour site within each time step under the preset substrate structure and preset process conditions; determine the positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data based on the contour site velocities; when a site is located inside the defect structure, correct the surface contour site velocity of the site to obtain the corresponding corrected target surface contour site velocity, thus completing the correction of the process simulation model; input the current substrate structure data into the corrected process simulation model and output the corresponding morphological defect prediction results. This method can simulate and predict morphological defects on any substrate structure during the process, determine whether defects will occur on the new structure substrate, and what the defect morphology will be, thereby assisting in process development and avoiding substrate structure design defects.

[0090] Figure 2 This document illustrates a flowchart of another method for determining morphological defects in a semiconductor graphical process simulation model provided in an embodiment of this application. Figure 2 As shown, the methods for determining morphological defects in semiconductor graphical process simulation models include:

[0091] Step 201: Obtain initial substrate structure data and initial process condition data.

[0092] Optionally, the initial substrate structure data refers to the data corresponding to the micro-nano scale structure formed in the preceding process for subsequent deposition or etching processes; the initial process condition data refers to the equipment process condition data required to perform deposition or etching.

[0093] The initial substrate structure data can be data corresponding to a user-defined substrate structure, or it can be contour data of an electronic characterization image extracted from actual process results, such as scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, etc., including but not limited to image structures of integrated circuit microelectronic devices, optoelectronic devices, microelectromechanical systems devices, etc. at a certain step or process during manufacturing.

[0094] The process conditions may include the type of reactant gas source, the flow rate of reactant gas, the flow rate of inert protective gas, the operating pressure of the equipment, the substrate temperature, the RF power supply power and the bias power, etc., and the embodiments of this application do not specifically limit these.

[0095] After obtaining the initial substrate structure data and initial process condition data, proceed to step 202.

[0096] Step 202: Perform simulation calculations using the initial substrate structure data and the initial process condition data from the process simulation model to determine the rate of each surface profile site within each time step under the preset substrate structure and preset process conditions.

[0097] In this application, initial substrate structure data and initial process condition data can be substituted into the process simulation model. Through simulation calculation, the simulation results of deposition morphology or etching morphology contours at each time step under preset substrate structure and preset process conditions can be obtained. Specifically, it is expressed as the velocity of each surface contour site. If it is a deposition process, it is expressed as the deposition rate; if it is an etching process, it is expressed as the etching rate, denoted as R. i .

[0098] After performing simulation calculations using the initial substrate structure data and the initial process condition data from the process simulation model to determine the rate of each surface profile site within each time step under the preset substrate structure and preset process conditions, step 203 is executed.

[0099] Step 203: Extract the edges from the initial substrate structure data and the surface contour site velocity to obtain the site coordinate matrix.

[0100] In this application, edge extraction can be performed on the substrate contour and surface contour site velocity corresponding to the substrate structure data to form a site coordinate matrix [X, Y]. The site coordinate matrix is ​​numbered according to the ascending or descending order of the X or Y coordinate values ​​or a certain regularity. This application does not specifically limit this.

[0101] Step 204: Traverse each site in the site coordinate matrix and determine the minimum distance between the two adjacent sites before and after each current site.

[0102] The specific implementation process of step 204 above may include the following sub-steps:

[0103] Sub-step A1: Traverse each of the sites in a preset order to determine the first target site before each current site and the second target site after each current site.

[0104] In this application embodiment, the preset order is not specifically limited, and can be specifically set according to the specific application scenario.

[0105] In this application, each point i can be traversed in a certain regular order. Specifically, for each point i, the points before point i are traversed first, denoted as j, which is the first target point. Then, the points after point i are traversed, denoted as k, which is the second target point.

[0106] Sub-step A2: Determine multiple target spacing values ​​between the first target site and the second target site.

[0107] In this application, the distance between points j and k can be calculated and denoted as D. jk .

[0108] Sub-step A3: Determine the minimum value among the multiple target spacing values ​​as the minimum spacing value between the two adjacent front and rear sites.

[0109] Clearly, for each traversed point i, there exist multiple D. jk Value, D jk The minimum value among the values ​​is denoted as the minimum spacing value D. min .

[0110] Step 205: Determine the site spacing value between each current site and its two adjacent sites based on the minimum spacing value.

[0111] In this application, the site spacing value between the current site and the first target site and the second target site corresponding to the minimum spacing value can be determined respectively.

[0112] Specifically, for the current minimum spacing value D min For points j and k, calculate the distances between point i and points j and k, respectively, and denot them as D. ij and D ik .

[0113] Step 206: Traverse multiple sites and determine the positional relationship between multiple sites and the defect structure based on the site spacing value and the minimum spacing value corresponding to each site.

[0114] Optionally, in this application, for nanometer-level sites, multiple sites can be traversed, and the positional relationship between multiple sites and the defect structure can be determined based on the site spacing value and the minimum spacing value corresponding to each site, combined with a preset defect opening threshold.

[0115] Optionally, for micrometer-level sites, multiple sites can be traversed, and the positional relationship between multiple sites and the defect structure can be determined based on the site spacing value and the minimum spacing value corresponding to each site, combined with a preset macroscopic particle mean free path parameter.

[0116] In this application, no specific limitations are made on the preset defect opening threshold and the preset macroscopic particle mean free path parameter; they can be set according to the actual application scenario.

[0117] Step 207: When the site is inside the defect structure, the surface contour site rate of the site is corrected based on the rate correction relationship to obtain the corresponding corrected target surface contour site rate, thus completing the correction of the process simulation model.

[0118] It should be noted that, when the site is not located inside the defect structure, the surface profile site rate of the corresponding site can be maintained at the current surface profile site rate.

[0119] In this application, the rate correction relationship may include the following rate correction formula:

[0120]

[0121] Where, d dec-thre It is the bottleneck width threshold at which the velocity decreases within the hole, while d zero-thre It is the bottleneck width threshold at which the velocity within the hole drops to zero. m and n are semi-empirical coefficients, both greater than 0, and d... min R is the minimum bottleneck width value. i-normal It is the rate of the pre-corrected surface profile site, R i The corrected target surface profile site rate.

[0122] In this application, the entire surface contour point matrix [X, Y] can be traversed to obtain the rate correction information for each point. The number of correction points is less than or equal to the number of surface contour points. In other words, defect identification requires discrimination and correction of each point on the surface contour to obtain the correction rate R for each point.ii .

[0123] Step 208: Input the current substrate structure data into the corrected process simulation model and output the corresponding morphology defect prediction results.

[0124] In this application, the new substrate structure data can be substituted into the modified process simulation model, and the new simulation results can be output to complete the defect prediction of the new substrate structure data.

[0125] Taking trench substrate deposition process as an example, Figure 3 This illustration shows a structural diagram of an embodiment of the present application providing a method for predicting whether a trench substrate structure with different tilt angles will develop void defects. Figure 3 (a) is the trench substrate structure with a tilt angle of 85 degrees. Figure 3 (b) is the trench substrate structure with a tilt angle of 80 degrees. Figure 3 (c) shows the trench substrate structure with a tilt angle of 75 degrees. It can be seen that the effect is best at 85 degrees.

[0126] This application discloses a method for identifying morphological defects that occur during process simulation in semiconductor patterning manufacturing processes, specifically thin film deposition or etching processes. This method is a process model correction method. Based on the method described in this application, morphological defects on any substrate structure during the process can be simulated and predicted to determine whether defects will occur on a new substrate structure and what the morphology of the defects will be, thereby assisting in process development and avoiding substrate structure design defects.

[0127] In summary, the method for determining morphological defects in a semiconductor patterned process simulation model provided in this application can acquire initial substrate structure data and initial process condition data; perform simulation calculations using the initial substrate structure data and initial process condition data in the process simulation model to determine the velocity of each surface contour site within each time step under the preset substrate structure and preset process conditions; determine the positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data based on the contour site velocities; when a site is located inside the defect structure, correct the surface contour site velocity of the site to obtain the corresponding corrected target surface contour site velocity, thus completing the correction of the process simulation model; input the current substrate structure data into the corrected process simulation model and output the corresponding morphological defect prediction results. This method can simulate and predict morphological defects on any substrate structure during the process, determine whether defects will occur on the new structure substrate, and what the defect morphology will be, thereby assisting in process development and avoiding substrate structure design defects.

[0128] Figure 4This illustration shows a schematic diagram of a morphology defect determination device in a semiconductor graphical process simulation model provided in an embodiment of this application. Figure 4 As shown, the morphology defect determination device 300 in the semiconductor graphical process simulation model includes:

[0129] The acquisition module 301 is used to acquire initial substrate structure data and initial process condition data;

[0130] The first determining module 302 is used to perform simulation calculations using the initial substrate structure data and the initial process condition data from the process simulation model to determine the rate of each surface contour site within each time step under the preset substrate structure and preset process conditions.

[0131] The second determining module 303 is used to determine the positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data based on the contour site rate.

[0132] The correction module 304 is used to correct the surface profile site rate of the site when the site is inside the defect structure, so as to obtain the corresponding corrected target surface profile site rate and complete the correction of the process simulation model.

[0133] The output module 305 is used to input the current substrate structure data into the corrected process simulation model and output the corresponding morphology defect prediction results.

[0134] In one possible implementation, the second determining module includes:

[0135] An edge extraction submodule is used to extract edges from the initial substrate structure data and the surface contour site rate to obtain a site coordinate matrix.

[0136] The first determining submodule is used to traverse each site in the site coordinate matrix and determine the minimum distance between the two adjacent sites before and after each current site.

[0137] The second determining submodule is used to determine the site spacing value between each current site and its two adjacent sites based on the minimum spacing value;

[0138] The third determining submodule is used to traverse multiple sites and determine the positional relationship between multiple sites and the defect structure based on the site spacing value and the minimum spacing value corresponding to each site.

[0139] In one possible implementation, the first determining submodule includes:

[0140] The first determining unit is configured to traverse each of the sites in a preset order and determine a first target site before each current site and a second target site after each current site.

[0141] The second determining unit is used to determine multiple target spacing values ​​between the first target site and the second target site;

[0142] The third determining unit is used to determine the minimum value among the plurality of target spacing values ​​as the minimum spacing value between the two adjacent front and rear sites.

[0143] In one possible implementation, the second determining submodule includes:

[0144] The fourth determining unit is used to determine the site spacing value between the current site and the first target site and the second target site corresponding to the minimum spacing value.

[0145] In one possible implementation, the third determining submodule includes:

[0146] The fifth determining unit is used to traverse multiple sites and, based on the site spacing value and the minimum spacing value corresponding to each site, determine the positional relationship between the multiple sites and the defect structure in combination with a preset defect opening threshold.

[0147] In one possible implementation, the third determining submodule includes:

[0148] The sixth determining unit is used to traverse multiple sites and, based on the site spacing value and the minimum spacing value corresponding to each site, determine the positional relationship between the multiple sites and the defect structure in combination with the preset macroscopic particle mean free path parameter.

[0149] In one possible implementation, the correction module includes:

[0150] The correction submodule is used to correct the surface contour site rate of the site based on the rate correction relationship when the site is inside the defect structure, so as to obtain the corresponding corrected target surface contour site rate and complete the correction of the process simulation model.

[0151] In one possible implementation, the device further includes:

[0152] A holding module is configured to maintain the surface profile site rate of the corresponding site at the current surface profile site rate when the site is not located inside the defect structure.

[0153] In one possible implementation, the initial substrate structure data refers to the data corresponding to the micro-nano scale structure formed in the preceding process for subsequent deposition or etching processes;

[0154] The initial process condition data refers to the equipment process condition data required to perform deposition or etching.

[0155] The morphology defect determination device in the semiconductor patterned process simulation model provided in this application embodiment can acquire initial substrate structure data and initial process condition data; perform simulation calculations using the initial substrate structure data and initial process condition data in the process simulation model to determine the velocity of each surface contour site within each time step under the preset substrate structure and preset process conditions; determine the positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data based on the contour site velocities; when a site is inside the defect structure, correct the surface contour site velocity of the site to obtain the corresponding corrected target surface contour site velocity, thus completing the correction of the process simulation model; input the current substrate structure data into the corrected process simulation model and output the corresponding morphology defect prediction results. This device can simulate and predict morphology defects on any substrate structure during the process, determine whether defects will occur on the new structure substrate, and what the defect morphology will be, thereby assisting in process development and avoiding substrate structure design defects.

[0156] This invention provides a device for determining morphological defects in a semiconductor graphical process simulation model, which can achieve, for example... Figures 1 to 2 To avoid repetition, the method for extending the etching rate in any of the etching simulation models shown will not be described again here.

[0157] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0158] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A method for determining morphological defects in a semiconductor graphical process simulation model, characterized in that, The method includes: Acquire initial substrate structure data and initial process condition data; The initial substrate structure data and the initial process condition data are simulated and calculated using a process simulation model to determine the rate of each surface profile site within each time step under the preset substrate structure and preset process conditions. Determining the positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data based on the contour site rate includes: performing edge extraction on the initial substrate structure data and the surface contour site rate to obtain a site coordinate matrix; traversing each site in the site coordinate matrix and determining the minimum spacing value between two adjacent sites for each current site; determining the site spacing value between each current site and two adjacent sites based on the minimum spacing value; traversing multiple sites and determining the positional relationship between multiple sites and the defect structure based on the site spacing value and the minimum spacing value for each site; wherein, the step of traversing multiple sites and determining the positional relationship between multiple sites and the defect structure based on the site spacing value and the minimum spacing value for each site includes: traversing multiple sites and determining the positional relationship between multiple sites and the defect structure based on the site spacing value and the minimum spacing value for each site, combined with a preset defect opening threshold; When the location is inside the defect structure, the surface profile location rate of the location is corrected to obtain the corresponding corrected target surface profile location rate, thus completing the correction of the process simulation model. The current substrate structure data is input into the modified process simulation model, and the corresponding morphological defect prediction results are output.

2. The method according to claim 1, characterized in that, The process of traversing each point in the point coordinate matrix and determining the minimum distance between the two adjacent points before and after each current point includes: Traverse each of the sites in a preset order to determine the first target site before each current site and the second target site after each current site; Determine multiple target spacing values ​​between the first target site and the second target site; The minimum value among the multiple target spacing values ​​is determined as the minimum spacing value between the two adjacent front and rear sites.

3. The method according to claim 2, characterized in that, The step of determining the site spacing value between each current site and its two adjacent sites based on the minimum spacing value includes: The site spacing values ​​between the current site and the first target site and the second target site corresponding to the minimum spacing value are determined respectively.

4. The method according to claim 1, characterized in that, The step of traversing multiple sites and determining the positional relationship between the multiple sites and the defect structure based on the site spacing value and the minimum spacing value corresponding to each site includes: By traversing multiple sites, and based on the site spacing value and the minimum spacing value corresponding to each site, the positional relationship between the multiple sites and the defect structure is determined by combining the preset macroscopic particle mean free path parameter.

5. The method according to claim 1, characterized in that, When the location is inside the defect structure, the surface profile location rate of the location is corrected to obtain the corresponding corrected target surface profile location rate, thus completing the correction of the process simulation model, including: When the location is inside the defect structure, the surface profile location rate of the location is corrected based on the rate correction relationship to obtain the corresponding corrected target surface profile location rate, thus completing the correction of the process simulation model.

6. The method according to claim 1, characterized in that, After determining the positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data based on the contour site rate, the method further includes: When the site is not located inside the defect structure, the surface profile site rate of the corresponding site is maintained as the current surface profile site rate.

7. The method according to claim 1, characterized in that, The initial substrate structure data refers to the data corresponding to the micro-nano scale structure formed in the preceding process for subsequent deposition or etching processes. The initial process condition data refers to the equipment process condition data required to perform deposition or etching.

8. A device for determining morphological defects in a semiconductor graphical process simulation model, characterized in that, The device includes: The acquisition module is used to acquire initial substrate structure data and initial process condition data; The first determining module is used to perform simulation calculations using the initial substrate structure data and the initial process condition data from the process simulation model to determine the rate of each surface profile site within each time step under the preset substrate structure and preset process conditions. The second determining module is used to determine the positional relationship between multiple sites and corresponding defect structures in the initial substrate structure data based on the contour site rate; including: performing edge extraction on the initial substrate structure data and the surface contour site rate to obtain a site coordinate matrix; traversing each site in the site coordinate matrix and determining the minimum spacing value between two adjacent sites for each current site; determining the site spacing value between each current site and two adjacent sites based on the minimum spacing value; traversing multiple sites and determining the positional relationship between multiple sites and the defect structure based on the site spacing value and the minimum spacing value corresponding to each site; wherein, the step of traversing multiple sites and determining the positional relationship between multiple sites and the defect structure based on the site spacing value and the minimum spacing value corresponding to each site includes: traversing multiple sites and determining the positional relationship between multiple sites and the defect structure based on the site spacing value and the minimum spacing value corresponding to each site, combined with a preset defect opening threshold; The correction module is used to correct the surface profile site rate of the site when the site is inside the defect structure, so as to obtain the corresponding corrected target surface profile site rate and complete the correction of the process simulation model. The output module is used to input the current substrate structure data into the corrected process simulation model and output the corresponding morphology defect prediction results.