Data driver and display apparatus including the same

Abstract

The present invention relates to a data driver and a display apparatus including the same. The present disclosure provides a display apparatus including a display panel configured to display an image, a gate driver connected to gate lines of the display panel, and a data driver connected to data lines of the display panel. The data driver provides copies of red, green, and blue data signals except for a white data signal in an externally input digital data signal having a 4:2:0 format, and converts the white, red, green, and blue data signals and the copied red, green, and blue data signals, thereby outputting an analog data voltage having a 4:4:4 format.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2021-0190365, filed on December 28, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This disclosure relates to data drives and display devices that include such data drives. Background Technology

[0003] With the development of information technology, the market for display devices, which serve as a medium for interconnecting users and information, is expanding. Consequently, the use of display devices such as light-emitting diode (LED) displays, quantum dot (QDD) displays, and liquid crystal displays (LCDs) is increasing.

[0004] The display device mentioned above includes: a display panel including subpixels; a driver configured to output drive signals for driving the display panel; and a power supply configured to generate power to be supplied to the display panel or the driver.

[0005] When drive signals (e.g., scan signals and data signals) are supplied to subpixels formed in the display panel of the aforementioned display device, selected subpixels transmit light or emit light directly, and thus the display device can display an image. Summary of the Invention

[0006] Therefore, this disclosure relates to a data driver and a display device including the data driver, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0007] The purpose of this disclosure is to provide a data driver and a display device including the data driver, which not only enables the realization of images based on standard type data signals with a 4:4:4 format, but also minimizes image quality degradation caused by loss of chroma components during the realization of images based on custom type data signals with a 4:2:0 format.

[0008] Additional advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon studying the following, or may be learned from practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0009] To achieve these objectives and other advantages and for the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a display panel configured to display an image; a gate driver connected to a gate line of the display panel; and a data driver connected to a data line of the display panel, wherein the data driver provides copies of red, green, and blue data signals (excluding a white data signal) in an externally input digital data signal having a 4:2:0 format, and converts the white, red, green, and blue data signals, as well as the copied red, green, and blue data signals, to output an analog data voltage having a 4:4:4 format.

[0010] The data driver may include a data selector configured to selectively copy red, green, and blue data signals, excluding white data signals, according to the format of an externally input data signal.

[0011] The data selector can perform a data signal copying operation when an external input digital data signal has a 4:2:0 format, and can choose not to perform a data signal copying operation when an external input digital data signal has a 4:4:4 format.

[0012] The data driver may further include: a first latch configured to sample red data signals, white data signals, green data signals, and blue data signals output through the data selector on a row basis, as well as copied red data signals, copied green data signals, and copied blue data signals; a second latch configured to sample white data signals output through the first latch on a row basis; and a third latch configured to hold red data signals, green data signals, and blue data signals output through the first latch, as well as copied red data signals, copied green data signals, copied blue data signals, and white data signals output through the second latch.

[0013] When the external input has a digital data signal in 4:2:0 format, the second latch can sample only the white data signal under the control of the data selector.

[0014] The data driver can output white data voltage in one horizontal time period, and can output red data voltage, green data voltage and blue data voltage in two horizontal time periods.

[0015] The red, white, green, and blue data voltages can be charged in the red, white, green, and blue sub-pixels of the display panel, respectively, during the falling edge of the gate signal applied to the gate line.

[0016] The display panel may include: at least one white sub-pixel configured to store a white data voltage during the falling edge of a first gate signal applied through a first gate line; at least one red sub-pixel, at least one green sub-pixel, and at least one blue sub-pixel configured to store a red data voltage, a green data voltage, and a blue data voltage respectively during the falling edge of a second gate signal applied through a second gate line disposed adjacent to the first gate line, and at least one white sub-pixel, at least one red sub-pixel, at least one green sub-pixel, and at least one blue sub-pixel are disposed on the same horizontal line.

[0017] In another aspect of this disclosure, a data driver is provided, comprising: a data selector configured to selectively copy red, green, and blue data signals (excluding white data signals) according to the format of an externally input data signal; a first latch configured to sample, on a row basis, the red, white, green, and blue data signals output through the data selector, as well as the copied red, green, and blue data signals; a second latch configured to sample, on a row basis, the white data signal output through the first latch; a third latch configured to hold, on a row basis, the red, green, and blue data signals output through the first latch, the copied red, green, and blue data signals, and the white data signal output through the second latch; and an output unit configured to convert the data signal output through the third latch into a data voltage having an analog form and output the data voltage.

[0018] The data selector can perform a data signal copying operation when an external input digital data signal has a 4:2:0 format, and can choose not to perform a data signal copying operation when an external input digital data signal has a 4:4:4 format.

[0019] According to exemplary embodiments of this disclosure, the following effects are achieved: not only are images based on standard type data signals with a 4:4:4 format realized, but also image quality degradation caused by loss of chroma components is minimized during the realization of images based on custom type data signals with a 4:2:0 format. Furthermore, when data signals compressed in a chroma subsampling manner are implemented in ultra-high resolution environments of UHD or higher, limitations such as image quality degradation are minimized. Attached Figure Description

[0020] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0021] Figure 1 It is a schematic block diagram illustrating a light-emitting display device;

[0022] Figure 2 It is shown schematically. Figure 1 The diagram of the sub-pixels shown;

[0023] Figure 3 and Figure 4 This is a view illustrating the configuration of the gate-type gate driver within the panel;

[0024] Figure 5 This is a view showing an example of the setup of an in-panel gate-type gate driver;

[0025] Figure 6 and Figure 7 This is a diagram illustrating the pixels set in the display panel and examples of pixel settings;

[0026] Figure 8 It is a graph showing the difference in data volume between the data signal format and the data signal based on the data signal format;

[0027] Figure 9 It is a diagram illustrating the driving conditions based on the format of the input data signal;

[0028] Figure 10 and Figure 11 This is a diagram illustrating a data signal compensation concept according to an exemplary embodiment of the present disclosure;

[0029] Figure 12 This is a diagram illustrating a display panel according to an exemplary embodiment of the present disclosure;

[0030] Figure 13 This is a diagram illustrating a method for applying a data voltage and a gate signal according to an exemplary embodiment of the present disclosure;

[0031] Figure 14 This is a diagram that briefly illustrates the configuration of a data driver according to an exemplary embodiment of this disclosure; and

[0032] Figures 15 to 17 This is a diagram illustrating the process associated with the copying of data signals based on some data signals stored in a latch, according to an exemplary embodiment of this disclosure. Detailed Implementation

[0033] The display device according to the exemplary embodiments of this disclosure can be implemented as a television set, image player, personal computer (PC), home theater, automotive electronics, smartphone, etc., but is not limited thereto. The display device according to the exemplary embodiments of this disclosure can be implemented as a light-emitting display (LED) device, a quantum dot display (QDD) device, a liquid crystal display (LCD) device, etc. However, for ease of description, the following description will be given in conjunction with, for example, a light-emitting display device configured to directly emit light based on inorganic light-emitting diodes or organic light-emitting diodes.

[0034] Figure 1 It is a block diagram schematically showing a light-emitting display device. Figure 2 It is shown schematically. Figure 1 The diagram shows the sub-pixels.

[0035] like Figure 1 and Figure 2 As shown, the light-emitting display device may include an image supplier 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, a power supply 180, etc.

[0036] The image supply unit 110 (SET or main system) can output various drive signals as well as image data signals supplied from external sources or stored in its internal memory. The image supply unit 110 can supply data signals and various drive signals to the timing controller 120.

[0037] The timing controller 120 can output a gate timing control signal GDC for controlling the operating timing of the gate driver 130, a data timing control signal DDC for controlling the operating timing of the data driver 140, and various synchronization signals (vertical synchronization signal Vsync and horizontal synchronization signal Hsync). The timing controller 120 can supply the data signal DATA supplied from the image supply 110 together with the data timing signal DDC to the data driver 140. The timing controller 120 can be in the form of an integrated circuit (IC) and therefore can be mounted on a printed circuit board, but is not limited thereto.

[0038] The gate driver 130 can output a gate signal (or gate voltage) in response to a gate timing control signal GDC or the like supplied from the timing controller 120. The gate driver 130 can supply gate signals to sub-pixels included in the display panel 150 via gate lines GL1 to GLm. The gate driver 130 can be in the form of an IC, or it can be directly formed on the display panel 150 as an in-panel gate, but is not limited thereto.

[0039] The data driver 140 can sample and latch the data signal DATA in response to a data timing control signal DDC or the like supplied from the timing controller 120. It can convert the resulting digital data signal into an analog data voltage based on a gamma reference voltage and output this data voltage. The data driver 140 can supply data voltage to sub-pixels included in the display panel 150 via data lines DL1 to DLn. The data driver 140 can be in the form of an IC and therefore can be mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

[0040] Power supply 180 can generate a first power supply with a high-level voltage and a second power supply with a low-level voltage based on an external input voltage supplied from outside, and can output the first power supply and the second power supply through a first power line EVDD and a second power line EVSS. Power supply 180 can not only generate and output the first power supply and the second power supply, but also generate and output voltages required to drive gate driver 130 (e.g., gate voltage including gate high voltage and gate low voltage), voltages required to drive data driver 140 (drain voltage and drain voltage including half-drain voltage), etc.

[0041] The display panel 150 can display images corresponding to drive signals including gate signals and data voltages, first power, second power, etc. The sub-pixels of the display panel 150 can emit light directly. The display panel 150 can be manufactured based on a substrate with rigidity or ductility, such as glass, silicon, polyimide, etc. The light-emitting sub-pixels can be composed of red sub-pixels, green sub-pixels, and blue sub-pixels, or composed of red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels.

[0042] For example, a sub-pixel SP may include pixel circuitry connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and includes switching transistors, driving transistors, capacitors, organic light-emitting diodes (OLEDs), etc. Sub-pixel SPs used in light-emitting display devices have complex circuit configurations because they emit light directly. Furthermore, there are various compensation circuits configured not only to compensate for the degradation of the emitting OLEDs, but also to compensate for the degradation of the driving transistors configured to supply the driving current required to drive the OLEDs. However, for ease of explanation, the sub-pixel SP is simply shown in block form.

[0043] Meanwhile, in the above description, the timing controller 120, gate driver 130, data driver 140, etc., have been described as having separate configurations. However, depending on the implementation type of the light-emitting display device, one or more of the timing controller 120, gate driver 130, and data driver 140 may be integrated into a single IC.

[0044] Figure 3 and Figure 4 This is a view illustrating the configuration of the gate-type gate driver within the panel. Figure 5 This is a view showing an example setup of an in-panel gate-type gate driver.

[0045] like Figure 3 As shown, the in-panel gate-type gate driver may include a shift register 131 and a level shifter 135. The level shifter 135 can generate a clock signal Clks, a start signal Vst, etc., based on the signals and voltages output from the timing controller 120 and the power supply 180. The clock signal Clks can be generated under the condition that the clock signal Clks has J different phases (J is an integer of 2 or greater), such as 2-phase, 4-phase, 8-phase, etc.

[0046] The shift register 131 can operate based on signals Clks and Vst output from the level shifter 135, and can output gate signals Gate[1] to Gate[m] that enable or disable transistors formed on the display panel. The shift register 131 can be formed on the display panel in the form of a thin film as an in-panel gate.

[0047] like Figure 3 and Figure 4 As shown, unlike shift register 131, level shifter 135 can be formed independently as an IC or can be internally included in power supply 180. However, this configuration is merely illustrative, and exemplary embodiments of this disclosure are not limited thereto.

[0048] like Figure 5 As shown, gate drivers 130a and 130b, which output gate signals in the in-panel gate-type gate driver, can be disposed in the non-display area NA of the display panel 150. Although gate drivers 130a and 130b have been shown as being disposed in the left and right non-display areas NA of the display panel 150, they can also be disposed in the upper and lower non-display areas NA of the display panel 150, or in the display area AA of the display panel 150.

[0049] Figure 6 and Figure 7 This is a diagram illustrating the pixels set in the display panel of a light-emitting display device and an example of pixel settings.

[0050] like Figure 6 As shown, the light-emitting display device can display images based on a display panel 150 comprising pixels (PIX) arranged in a matrix. A single pixel (PIX) disposed in the display panel 150 may include a red subpixel SPr, a white subpixel SPw, a green subpixel SPg, and a blue subpixel SPb.

[0051] like Figure 7 As shown in (a) to 7(d), the order in which the red subpixel SPr, green subpixel SPg, blue subpixel SPb, and white subpixel SPw are set can vary depending on the implementation type of the display panel.

[0052] Figure 8 It is a graph showing the difference in data volume between the data signal format and the data signal based on the data signal format. Figure 9 It is a diagram illustrating the driving conditions based on the format of the input data signal.

[0053] like Figure 8 As shown, the data signal YCbCr used to display an image can be composed of a luminance component Y (luminance) and chrominance components Cb and Cr (chrominance). The data signal YCbCr of the original image generated through image generation can have a 4:4:4 format.

[0054] However, in broadcast and video media, to reduce data transmission capacity, some signal components can be discarded from the original video data signal YCbCr, thus formatting the data signal YCbCr into a 4:2:0 format, and the resulting data signal can then be transmitted. As mentioned above, the method of reducing only the chromaticity components Cb and Cr (chromaticity) while still retaining the luminance component Y (luminance) is called "chromaticity subsampling".

[0055] Figure 8An example of chroma subsampling is shown, in which the original image's data signal YCbCr is compressed and sampled from a 4:4:4 format to a 4:2:0 (or 4:2:2) format, such that the ratio of the luminance value Y, the first hue value Cb, and the second hue value Cr included in the data signal YCbCr changes from 4:4:4 to 4:2:0 (or 4:2:2). From Figure 8 It is evident that although the data volume of the YCbCr data signal in 4:4:4 format is 100%, when the YCbCr data signal is downsampled to 4:2:0 format, the data volume of the YCbCr data signal can be reduced to 50%. Since the reduction in image data processing capability can be achieved through image downsampling, many advantages associated with the portion of the signal processed at both the image transmitting and receiving sides can be provided.

[0056] like Figure 9 As shown, the data signal can be input to the image provider 110 (SET) in 4K resolution, 120Hz drive frequency, 10 data bits, and 4:4:4 format, or in 4K resolution, 240Hz drive frequency, 10 data bits, and 4:4:4 format. Referring to the data signal output from the image provider 110 to the timing controller 120 (TCON), it can be seen that although the 4:4:4 and 4:2:0 format data signals are output with 12 data bits in both formats, the 4:4:4 format data signal can be recognized as standard, while the 4:2:0 format data signal can be recognized as custom.

[0057] Therefore, display devices such as light-emitting display devices can render images based on formats such as 4:4:4 and 4:2:0. However, when data signals compressed using chroma subsampling are implemented in UHD or higher ultra-high resolution environments, image quality degradation may occur due to the loss of chroma components, resulting in blurring of parts of the image or characters. Therefore, it is necessary to eliminate this problem.

[0058] Figure 10 and Figure 11 This is a diagram illustrating a data signal compensation concept according to an exemplary embodiment of the present disclosure.

[0059] like Figure 10 and Figure 11As shown, according to an exemplary embodiment of this disclosure, when a data signal compressed in 4:2:0 format using chroma subsampling is input to the timing controller 120 from an external source, the timing controller 120 can perform image processing on the input data signal and output the resulting data signal to the data driver 140. Furthermore, the data driver 140 can compensate for the 4:2:0 compressed data signal, and thus can generate a 4:4:4 format data signal, which can then be output. The data driver 140 can digitally compensate for lost chroma components in the data signal and then output the resulting data signal.

[0060] Figure 12 This is a diagram illustrating a display panel according to an exemplary embodiment of the present disclosure. Figure 13 This is a diagram illustrating a method for applying a data voltage and a gate signal according to an exemplary embodiment of the present disclosure.

[0061] like Figure 12 As shown, the pixels included in the display panel according to the exemplary embodiments of this disclosure may have the same setting and connection relationships as the pixel PIX, which will be described below.

[0062] The display panel may include pixels arranged horizontally in the order of red sub-pixel R11, white sub-pixel W11, green sub-pixel G11, and blue sub-pixel B11. A first gate line GL1 may be disposed at the upper end of the pixel and extend horizontally, and a second gate line GL2 may be disposed at the lower end of the pixel and extend horizontally. First data lines DL1 to fourth data lines DL4 may be configured to extend vertically in a direction intersecting the first gate line GL1 and the second gate line GL2.

[0063] The red sub-pixel R11 can be connected to the first data line DL1 and the second gate line GL2. The red sub-pixel R11 can emit light in response to a second gate signal applied to it through the second gate line GL2 based on a first data voltage applied to it through the first data line DL1.

[0064] The white sub-pixel W11 can be connected to the second data line DL2 and the first gate line GL1. The white sub-pixel W11 can emit light in response to a first gate signal applied to it through the first gate line GL1 based on a second data voltage applied to it through the second data line DL2.

[0065] The green sub-pixel G11 can be connected to the third data line DL3 and the second gate line GL2. The green sub-pixel G11 can emit light in response to a second gate signal applied to it via the second gate line GL2 based on a third data voltage applied to it via the third data line DL3.

[0066] The blue sub-pixel B11 can be connected to the fourth data line DL4 and the second gate line GL2. The blue sub-pixel B11 can emit light in response to a second gate signal applied to it via the second gate line GL2 based on a fourth data voltage applied to it via the fourth data line DL4.

[0067] like Figure 12 and Figure 13 As shown, the output formats of data voltages D1, D3, D4, D5, D7, and D8 output from the first data line DL1, the third data line DL3, the fourth data line DL4, the fifth data line DL5, the seventh data line DL7, and the eighth data line DL8 can be different from the output formats of data voltages D2 and D6 output from the second data line DL2 and the sixth data line DL6.

[0068] Each of the first gate signal G1 applied via the first gate line GL1, the second gate signal G2 applied via the second gate line GL2, the third gate signal G3 applied via the third gate line GL3, and the fourth gate signal G4 applied via the fourth gate line GL4 can be applied at a logic high level (including the on-state voltage of the transistor in the pixel) for a duration of 2H. Additionally, these gate signals G1 to G4 can be applied such that adjacent gate signals among G1 to G4 overlap each other for a duration of 1H.

[0069] The following text will provide further details regarding the relationship between the two parties. Figure 13 The data voltages D1 to D8 and gate signals G1 to G4 shown are applied to Figure 12 The description associated with the display panel shown.

[0070] exist Figure 12 In the first horizontal line HL1, it is possible to Figure 13 During the falling edge of the first gate signal G1 shown, the eleventh white data voltage W11 of the white sub-pixel connected to the second data line DL2 and the twelfth white data voltage W12 of the white sub-pixel connected to the sixth data line DL6 are charged. The eleventh white data voltage W11 and the twelfth white data voltage W12 charged in the first horizontal line HL1 can be generated based on the white data signal included in the data signal having a 4:2:0 format.

[0071] exist Figure 12 In the first horizontal line HL1, it is possible to Figure 13During the falling edge of the second gate signal G2 shown, the eleventh red data voltage R11 of the red sub-pixel connected to the first data line DL1, the eleventh green data voltage G11 of the green sub-pixel connected to the third data line DL3, and the eleventh blue data voltage B11 of the blue sub-pixel connected to the fourth data line DL4 are charged. The eleventh red data voltage R11, eleventh green data voltage G11, and eleventh blue data voltage B11 charged in the first data line DL1, third data line DL3, and fourth data line DL4 in the first horizontal line HL1 can be generated based on the red data signal, green data signal, and blue data signal included in the data signal having a 4:2:0 format.

[0072] In the first horizontal line HL1, it is possible to Figure 13 During the falling edge of the second gate signal G2 shown, the eleventh red data voltage R11 connected to the red sub-pixel of the fifth data line DL5, the eleventh green data voltage G11 connected to the green sub-pixel of the seventh data line DL7, and the eleventh blue data voltage B11 connected to the blue sub-pixel of the eighth data line DL8 are charged. The eleventh red data voltage R11, eleventh green data voltage G11, and eleventh blue data voltage B11 charged in the fifth data line DL5, seventh data line DL7, and eighth data line DL8 in the first horizontal line HL1 can be copies (replicated data signals) of the red data signal, green data signal, and blue data signal supplied to the first data line DL1, third data line DL3, and fourth data line DL4, respectively.

[0073] exist Figure 12 In the second horizontal line HL2, it is possible to Figure 13 During the falling edge of the second gate signal G2 shown, the twenty-first white data voltage W21 connected to the white sub-pixel connected to the second data line DL2 and the twenty-second white data voltage W22 connected to the white sub-pixel connected to the sixth data line DL6 are charged. The twenty-first white data voltage W21 and the twenty-second white data voltage W22 charged in the second horizontal line HL2 can be those data voltages that immediately follow the white data signal input used to generate the eleventh white data voltage W11 and the twelfth white data voltage W12 of the first horizontal line HL1.

[0074] exist Figure 12 In the second horizontal line HL2, it is possible to Figure 13During the falling edge of the third gate signal G3 shown, the eleventh red data voltage R11 connected to the red sub-pixel of the first data line DL1, the eleventh green data voltage G11 connected to the green sub-pixel of the third data line DL3, and the eleventh blue data voltage B11 connected to the blue sub-pixel of the fourth data line DL4 are charged. The eleventh red data voltage R11, eleventh green data voltage G11, and eleventh blue data voltage B11 charged in the first data line DL1, third data line DL3, and fourth data line DL4 in the second horizontal line HL2 can be copies (replicated data signals) of the red data signal, green data signal, and blue data signal supplied to the first data line DL1, third data line DL3, and fourth data line DL4 in the first horizontal line HL1.

[0075] In the second horizontal line HL2, it is possible to Figure 13 During the falling edge of the third gate signal G3 shown, the eleventh red data voltage R11 connected to the red sub-pixel of the fifth data line DL5, the eleventh green data voltage G11 connected to the green sub-pixel of the seventh data line DL7, and the eleventh blue data voltage B11 connected to the blue sub-pixel of the eighth data line DL8 are charged. The eleventh red data voltage R11, eleventh green data voltage G11, and eleventh blue data voltage B11 charged in the fifth data line DL5, seventh data line DL7, and eighth data line DL8 in the second horizontal line HL2 can be copies (replicated data signals) of the red data signal, green data signal, and blue data signal supplied to the first data line DL1, third data line DL3, and fourth data line DL4.

[0076] Referring to the above description, it can be seen that the white data voltages (e.g., W11 and W12) are not generated based on the copied data signal, and therefore can be output during one horizontal time (H) of the gate signal (e.g., G1) applied for one row, while the red data voltage R11, green data voltage G11, and blue data voltage B11 are generated based on the copied data signal, and therefore can be output during two horizontal times (H) of the gate signals (e.g., G2 and G3) applied for two rows. In other words, the data signal generated by copying can be output on a multi-row (at least two-row) basis relative to the horizontal line.

[0077] Figure 14 This is a diagram that briefly illustrates the configuration of a data driver according to an exemplary embodiment of this disclosure. Figures 15 to 17 This is a diagram illustrating the process associated with the copying of data signals based on some data signals stored in a latch, according to an exemplary embodiment of this disclosure.

[0078] like Figure 14 As shown, a data driver according to an exemplary embodiment of this disclosure may include a shift register SR, a data selector SEL (444 / 420 selection logic), a first latch LAT1 (sampling), a second latch LAT2 (sampling), a third latch LAT3 (holding), a DA converter DAC, an amplifier AMP, etc. The DA converter DAC and the amplifier AMP can be collectively referred to as the output unit.

[0079] The shift register SR can be used to generate control signals to receive data signals in digital form from the timing controller on a row-by-row basis.

[0080] The data selector SEL, under the control of the shift register SR, can selectively copy (expand) red, green, and blue data signals (excluding white data signals) according to the format of the externally input data signals. The data selector SEL may not perform a copy operation when the data signal has a 4:4:4 format, but it can perform a copy operation when the data signal has a 4:2:0 format.

[0081] The first latch, LAT1, can be used to sample and store the data signal output by the data selector SEL. LAT1 can sample the red, white, green, and blue data signals on a row-by-row basis. LAT1 can be called a sampling latch because it samples the red, white, green, and blue data signals on a row-by-row basis.

[0082] The second latch, LAT2, can be used to sample and store the data signal output from the first latch, LAT1. LAT2 can sample only the white data signal on a row-by-row basis. LAT2 can be called a sampling latch because it samples the white data signal on a row-by-row basis. Under the control of the data selector SEL, LAT2 can be in a non-operating state when the data signal has a 4:4:4 format, but can be in an operating state when the data signal has a 4:2:0 format, sampling only the white data signal. Simultaneously, since LAT2 samples only the white data signal on a row-by-row basis, the red, green, and blue data signals output from the first latch, LAT1, can be input to the third latch, LAT3.

[0083] The third latch, LAT3, can hold the data signals output from the first latch, LAT1, and the second latch, LAT2, and can also output the held data signals. The third latch, LAT3, can hold and then output the data signal corresponding to the source output signal, SOE. The third latch, LAT3, can be called a holding latch because it holds the red, white, green, and blue data signals on a row-by-row basis.

[0084] The DA converter (DAC) can be used to convert a digital data signal output from the third latch (LAT3) into a data voltage in analog form, and then output that data voltage. Additionally, the DA converter (DAC) can convert a digital data signal into a data voltage in analog form based on a gamma reference voltage output from the gamma unit.

[0085] An amplifier (AMP) can be used to amplify data voltages in analog form, converted by a DA converter (DAC), through various output channels, and then output the amplified data voltages. The data voltages output from the amplifier (AMP) can be applied to sub-pixels via data lines.

[0086] like Figures 15 to 17 As shown, when the externally input data signal is in 4:2:0 format, the data selector SEL can perform the following copy operation.

[0087] The data selector SEL can copy the first data signal D1, intended to be output via the first data line DL1, to the fifth data signal D5, so that the first data signal D1 can also be output via the fifth data line DL5. The data selector SEL can also copy the third data signal D3, intended to be output via the third data line DL3, to the seventh data signal D7, so that the third data signal D3 can also be output via the seventh data line DL7. The data selector SEL can also copy the fourth data signal D4, intended to be output via the fourth data line DL4, to the eighth data signal D8, so that the fourth data signal D4 can also be output via the eighth data line DL8.

[0088] In other words, when the data signal is in 4:2:0 format, the data selector SEL can set the path so that the first and fifth data lines are grouped together, the third and seventh data lines are grouped together, and the fourth and eighth data lines are grouped together. The first data signal D1 to the eighth data signal D8 copied by the data selector SEL can be sampled and stored by the first latch LAT1.

[0089] It should also be noted that the second latch LAT2, located downstream of the first latch LAT1, is shown as follows: the white data signals D2' and D6' previously applied to the second latch LAT2 are stored in the second latch LAT2 respectively according to individual sampling operations. In this case, through subsequent output processes, the white data signals D2' and D6' stored in the second latch LAT2 can be... Figure 13 The eleventh white data voltage W11 and the twelfth white data voltage W12 are output, and the white data signals D2 and D6 stored in the first latch LAT1 can be output in the form of... Figure 13 The output is in the form of the twenty-first white data voltage W21 and the twenty-second white data voltage W22.

[0090] and Figure 16 The source output signal SOE (240Hz) corresponds to, Figure 15 The data signal shown can be held by the third latch LAT3 in the form of odd-numbered rows of data including red, green, and blue data signals (RGB) and even-numbered rows of data including white data signal (W), and then the held data signal can be output. Subsequently, the data signal output from the third latch LAT3 can be converted into a data voltage by a DA converter (DAC) or similar device, and then that data voltage can be output.

[0091] Therefore, the data driver according to an exemplary embodiment of this disclosure can digitally compensate for the missing chroma components of the data signal through a copying operation of the selective data signal for the data selector SEL and a latching operation of the white data signal for the second latch LAT, and can then output the compensated data signal.

[0092] Therefore, as Figure 17 As shown, a data signal input in 4:2:0 format can be reconfigured into a 4:4:4 format data signal through a compensation operation performed by the data driver, and therefore, the data voltage to be supplied to the display panel can be provided in an extended state. Thus, image quality degradation problems can be minimized.

[0093] As is apparent from the above description, the exemplary embodiments of this disclosure offer the following advantages: not only are images based on standard type data signals with a 4:4:4 format realized, but also image quality degradation caused by chroma component loss during the realization of images based on custom type data signals with a 4:2:0 format is minimized. Furthermore, when data signals compressed using chroma subsampling are implemented in UHD or higher ultra-high resolution environments, limitations such as image quality degradation are minimized.

[0094] The foregoing description and accompanying drawings have been presented to illustrate the technical concept of this disclosure. Those skilled in the art will understand that various modifications and variations are possible by combining, dividing, substituting, or changing the constituent elements without altering the essential characteristics of this disclosure. Therefore, the foregoing embodiments disclosed herein should be interpreted as illustrative only and not as limiting the principles and scope of this disclosure. It should be understood that the scope of this disclosure is defined by the appended claims, and all equivalent forms thereof fall within the scope of this disclosure.

Claims

1. A display device, comprising: The display panel is configured to display images; A gate driver connected to the gate line of the display panel; as well as The data driver, which is connected to the data cable of the display panel, The data driver provides copies of red, green, and blue data signals (excluding white data signals) from a digital data signal in 4:2:0 format input to the data driver, and converts the white, red, green, and blue data signals, as well as the copied red, green, and blue data signals, to output an analog data voltage in 4:4:4 format. The data driver includes a data selector configured to selectively copy the red, green, and blue data signals, excluding the white data signal, according to the format of the externally input data signal. The data driver further includes: A first latch is configured to sample, on a row basis, the red data signal, white data signal, green data signal, and blue data signal output through the data selector, as well as the copied red data signal, the copied green data signal, and the copied blue data signal. A second latch is configured to sample the white data signal output from the first latch on a row-by-row basis; and A third latch is configured to hold the red data signal, green data signal, and blue data signal output through the first latch, as well as the copied red data signal, the copied green data signal, and the copied blue data signal, and the white data signal output through the second latch.

2. The display device according to claim 1, wherein, The data selector performs a data signal copying operation when an external input digital data signal has a 4:2:0 format, and does not perform a data signal copying operation when an external input digital data signal has a 4:4:4 format.

3. The display device according to claim 1, wherein, When an external input has a digital data signal in 4:2:0 format, the second latch, under the control of the data selector, samples only the white data signal.

4. The display device according to claim 1, wherein, The data driver outputs a white data voltage in one horizontal time period and outputs a red data voltage, a green data voltage, and a blue data voltage in two horizontal time periods.

5. The display device according to claim 4, wherein, The red data voltage, the white data voltage, the green data voltage, and the blue data voltage are charged in the red sub-pixel, white sub-pixel, green sub-pixel, and blue sub-pixel of the display panel, respectively, during the falling edge of the gate signal applied to the gate line.

6. The display device according to claim 1, wherein, The display panel includes: At least one white sub-pixel is configured to store a white data voltage during the falling edge of a first gate signal applied through a first gate line; At least one red sub-pixel, at least one green sub-pixel, and at least one blue sub-pixel, wherein the at least one red sub-pixel, the at least one green sub-pixel, and the at least one blue sub-pixel are respectively configured to store a red data voltage, a green data voltage, and a blue data voltage during the falling edge of a second gate signal applied through a second gate line disposed adjacent to the first gate line; and The at least one white sub-pixel, the at least one red sub-pixel, the at least one green sub-pixel, and the at least one blue sub-pixel are arranged on the same horizontal line.

7. A data driver, comprising: A data selector configured to selectively copy red, green, and blue data signals (excluding white data signals) according to the format of an externally input data signal. A first latch is configured to sample, on a row basis, the red data signal, white data signal, green data signal, and blue data signal output through the data selector, as well as the copied red data signal, the copied green data signal, and the copied blue data signal. The second latch is configured to sample the white data signal output through the first latch on a line basis; A third latch is configured to hold the red data signal, green data signal, and blue data signal output through the first latch, as well as the copied red data signal, the copied green data signal, and the copied blue data signal, and the white data signal output through the second latch. as well as An output unit is configured to convert the data signal output through the third latch into a data voltage in analog form, and output the data voltage. When the data selector receives a digital data signal in 4:2:0 format from an external input, the output unit outputs an analog data voltage in 4:4:4 format.

8. The data driver according to claim 7, wherein, The data selector performs a data signal copying operation when an external input digital data signal has a 4:2:0 format, and does not perform a data signal copying operation when an external input digital data signal has a 4:4:4 format.

Images