Display panel and display device

Abstract

The display panel comprises a display area and a non-display area surrounding the display area; the display area comprises a back gate signal transmission layer and a plurality of pixel units arranged in an array; the pixel unit comprises a pixel driving circuit; at least one transistor in the pixel driving circuit is a vertical double-gate transistor; the back gate of the vertical double-gate transistor is electrically connected with the back gate signal transmission layer; the non-display area is provided with a first back gate signal lead wire; along the column direction of the pixel units, the first back gate signal lead wire is electrically connected with the back gate signal transmission layer through a plurality of connection lines, for receiving a voltage regulating signal and transmitting the voltage regulating signal to the back gate of the vertical double-gate transistor. The display panel can effectively alleviate the problem of display abnormalities caused by the fact that the voltage regulating signals received by the back gates of the vertical double-gate transistors at different positions in the display panel are inconsistent.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display panels, and in particular to a display panel and a display device. BACKGROUND

[0002] In order to overcome the influence of the threshold voltage of the pixel driving circuit transistor in the display panel, the prior art generally adopts the method of additionally setting a back gate to adjust the threshold voltage of the original transistor to form a vertical double-gate transistor. In this setting mode, the original gate can be referred to as a top gate. The specific method is that the power signal (PVDD signal) line is bridged with the back gate signal transmission layer through the display panel top end via hole, the back gate signal transmission layer is electrically connected with the back gate of the vertical double-gate transistor of each row of pixel driving circuit, that is, the power signal line provides a signal for the bottom gate.

[0003] Although this solution can alleviate the influence of the threshold voltage of the transistor to a certain extent, the voltage drop exists in the back gate signal transmission layer in this setting mode, which causes the signals received by the back gates of the vertical double-gate transistors of the pixel driving circuits at different positions in the display area to be inconsistent, and further causes the display of the display panel to be abnormal. SUMMARY

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device.

[0005] In a first aspect, the present disclosure provides a display panel, comprising a display area and a non-display area surrounding the display area;

[0006] The display area comprises a back gate signal transmission layer and a plurality of pixel units arranged in an array; the pixel unit comprises a pixel driving circuit; at least one transistor in the pixel driving circuit is a vertical double-gate transistor; the back gate of the vertical double-gate transistor is electrically connected with the back gate signal transmission layer;

[0007] The non-display area is provided with a first back gate signal lead line; along the column direction of the pixel unit, the first back gate signal lead line is electrically connected with the back gate signal transmission layer through a plurality of connection lines, for receiving a voltage regulating signal and transmitting the voltage regulating signal to the back gate of the vertical double-gate transistor.

[0008] In a second aspect, the present disclosure further provides a display device comprising the display panel according to any one of the first aspect.

[0009] Compared with the prior art, the technical scheme provided by the embodiments of the present disclosure has the following advantages:

[0010] The display area of the display panel provided by the present disclosure comprises a back gate signal transmission layer and a plurality of pixel units arranged in an array, the pixel unit comprises a pixel driving circuit, at least one transistor in the pixel driving circuit is a vertical double-gate transistor, the back gate of the vertical double-gate transistor is electrically connected with the back gate signal transmission layer, and a first back gate signal lead line is arranged in the non-display area, along the column direction of the pixel unit, the first back gate signal lead line is electrically connected with the back gate signal transmission layer through a plurality of connection lines, for receiving a voltage regulating signal and transmitting the voltage regulating signal to the back gate of the vertical double-gate transistor. The first back gate signal lead line is electrically connected with the back gate signal transmission layer through a plurality of connection lines along the column direction of the pixel unit, that is, the first back gate signal lead line can independently provide a voltage regulating signal for the back gates of a plurality of rows of vertical double-gate transistors. The first back gate signal lead line is electrically connected with the back gate signal transmission layer through a plurality of connection lines, which can form a network-like connection, and the resistance of the first back gate signal lead line after being electrically connected with the back gate signal transmission layer through a plurality of connection lines is smaller than the resistance of the original back gate signal transmission layer. Therefore, the difference of the voltage regulating signal transmitted to the back gates of the vertical double-gate transistors in the pixel units at different positions of the display area can be reduced to a certain extent, and the problem that the signals received by the back gates of the vertical double-gate transistors in the pixel driving circuit of each row are inconsistent due to the voltage drop of the back gate signal transmission layer when the voltage regulating signal is provided for the back gates of the vertical double-gate transistors in the pixel units of each row through the bridge connection of the back gate signal transmission layer and the power signal (PVDD signal) line through the via hole at the top end of the display panel is effectively alleviated. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the accompanying drawings required to be used in the embodiments or the prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0013] Figure 1 A display panel structure schematic diagram provided by the present disclosure;

[0014] Figure 2 Another display panel structure schematic diagram provided by the present disclosure;

[0015] Figure 3 Another display panel structure schematic diagram provided by the present disclosure;

[0016] Figure 4 Another display panel structure schematic diagram provided by the present disclosure;

[0017] Figure 5 Yet another display panel structure schematic diagram provided by an embodiment of the present disclosure;

[0018] Figure 6 Yet another display panel structure schematic diagram provided by an embodiment of the present disclosure;

[0019] Figure 7 Yet another display panel structure schematic diagram provided by an embodiment of the present disclosure;

[0020] Figure 8 Yet another display panel structure schematic diagram provided by an embodiment of the present disclosure;

[0021] Figure 9 Yet another display panel structure schematic diagram provided by an embodiment of the present disclosure;

[0022] Figure 10 Yet another display panel structure schematic diagram provided by an embodiment of the present disclosure;

[0023] Figure 11 Yet another display panel structure schematic diagram provided by an embodiment of the present disclosure;

[0024] Figure 12 Yet another display panel structure schematic diagram provided by an embodiment of the present disclosure.

[0025] Reference signs:

[0026] 10, display area; 20, non-display area; 11, back gate signal transmission layer; 12, pixel unit; 21, first back gate signal lead; 22, connection line; 211, first back gate signal lead first part; 212, first back gate signal lead second part; 31, power voltage signal transmission layer; 51, binding area; 511, FPC; 310, via hole; 71, shift register; 23, second back gate signal lead; 100, display panel. DETAILED DESCRIPTION

[0027] In order to enable a person skilled in the art to more clearly understand the above-mentioned purposes, features and advantages of the present disclosure, the schemes of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0028] In the following description, many specific details are set forth in order to fully understand the present disclosure, but the present disclosure can also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some of the embodiments of the present disclosure, not all the embodiments.

[0029] The pixel driving circuit of the pixel unit of the existing display panel includes a large number of thin film transistors. The threshold voltage of the thin film transistor will drift due to the film layer defects caused in the process or the long-time working bias in a single direction, resulting in poor reliability of the thin film transistor and finally affecting the display effect of the display panel. Therefore, at least part of the thin film transistors can be set as vertical double-gate transistors, and the threshold voltage of the vertical double-gate transistor is adjusted by providing an adjusting voltage for the back gate of the vertical double-gate transistor. In the prior art, the display area of the OLED display panel is provided with a power signal (PVDD signal) line, and each pixel driving circuit is connected with the FPC (Flexible Printed Circuit) located at the bottom end of the OLED display panel through the PVDD signal line. The FPC can input the PVDD signal to the pixel driving circuit through the PVDD signal line to control the corresponding OLED light emitting element to emit light. The PVDD signal line is bridged with the back gate signal transmission layer through the display panel top via hole, and the back gate signal transmission layer is electrically connected with the back gate of the vertical double-gate transistor of each row of pixel driving circuits, that is, the signal is provided for the bottom gate through the PVDD signal line to adjust and control the threshold voltage of the vertical double-gate transistor. However, the pixel driving circuits located at different rows are different in distance from the display panel top via hole, and the vertical double-gate transistors of the pixel driving circuits in different rows are electrically connected with the PVDD signal line at the corresponding position of the display panel top via hole through the back gate signal transmission layer. The resistance at a position on the back gate signal transmission layer is positively correlated with the distance between the position and the display panel top via hole (that is, the resistance at the position on the back gate signal transmission layer is greater, the farther the distance between the position and the display panel top via hole is), and therefore the voltage of the PVDD signal transmitted to the back gate of the vertical double-gate transistor of the pixel driving circuit at the position on the back gate signal transmission layer farther from the display panel top via hole is smaller, resulting in a large difference in the signal received by the back gate of the vertical double-gate transistor of the pixel driving circuit at different positions of the display panel, which will cause the display of the display panel to be abnormal.

[0030] To solve the above problems, the display panel and display device provided by the embodiments of the present disclosure are provided.

[0031] The display panel and display device provided by the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0032] Figure 1This is a schematic diagram of a display panel structure provided in an embodiment of the present disclosure. The display panel may include a display area 10 and a non-display area 20 surrounding the display area 10. The display area 10 is used to display images and generally has a plurality of pixel units 12 arranged in an array. Each pixel unit 12 includes a pixel driving circuit. At least one transistor in the pixel driving circuit is a vertical dual-gate transistor. The non-display area 20 is used for peripheral circuits and wiring, and it is generally arranged around the display area 10.

[0033] Display area 10 also includes a back gate signal transmission layer 11. The back gate of the vertical dual-gate transistor is electrically connected to the back gate signal transmission layer 11. A vertical dual-gate transistor is a transistor in which the top gate and back gate are formed on different film layers. The back gate signal transmission layer 11 is a film layer used to transmit adjustment signals to the back gate of the vertical dual-gate transistor. For example, the back gate signal transmission layer 11 can be configured to be on the same film layer as the back gate of the vertical dual-gate transistor. In terms of manufacturing process, the back gate and the back gate signal transmission layer 11 can also be different functional units with different patterns formed after being deposited in the same process and then exposed, developed, etched, etc. That is, the back gate and the back gate signal transmission layer 11 can be made of the same material and on the same film layer, only with different functions to be implemented. Figure 1 For the sake of simplicity, only pixel unit 12 is shown in the illustration. However, it should be understood that the back gate is part of pixel unit 12. Therefore, the back gate signal transmission layer 11 connected to the back gate in the illustration of this embodiment can also be shown as the back gate signal transmission layer 11 connected to pixel unit 12.

[0034] The non-display area 20 is provided with a first back gate signal lead 21; along the pixel unit column direction ( Figure 1 In the X direction, the first back gate signal lead 21 is electrically connected to the back gate signal transmission layer 11 through multiple connecting lines 22. The first back gate signal lead 21 can receive the voltage regulation signal and transmit it to the back gate of the vertical dual-gate transistor in each row of pixel units through multiple connecting lines 22.

[0035] Compared with the prior art, the embodiment of the present disclosure not only or no longer provides a voltage regulating signal for the back gate through the via at the top of the display panel by the original PVDD signal, but also separately leads out a plurality of connection lines 22 for the back gate of the vertical double-gate transistor in each row of pixel units 12 by the first back gate signal lead 21 of the non-display area 20. The first back gate signal lead 21 is electrically connected to the back gate signal transmission layer 11 through the plurality of connection lines 22 to form a network-like connection. Therefore, the electrical resistance of the first back gate signal lead 21 after being electrically connected to the back gate signal transmission layer 11 through the plurality of connection lines 22 is smaller than the electrical resistance of the original back gate signal transmission layer 11. Therefore, compared with providing the voltage regulating signal for the vertical double-gate transistor from the back gate signal transmission layer 11 at the top of the display panel to the next row, the embodiment of the present disclosure can reduce the difference of the voltage regulating signal for the back gate of the vertical double-gate transistor in the pixel units 12 at different positions of the display area to a certain extent, thereby alleviating the problem of display panel display abnormality caused by the voltage difference of the voltage regulating signal obtained by the back gates of different pixel units 12 being too large.

[0036] Figure 1 The pixel unit column direction X is shown, and the first back gate signal lead 21 can be connected to the corresponding gate signal transmission layer 11 of each row of pixel units 12 through the connection line 22 to provide a voltage regulating signal for the back gate of the vertical double-gate transistor of each row of pixel units 12. That is, in some embodiments, the number of connection lines 22 can be equal to the number of rows of pixel units 12, as shown in FIG. 1. Figure 1 That is, in some embodiments, the number of connection lines 22 can be less than the number of rows of pixel units 12, for example, one connection line 22 is arranged every few rows of pixel units 12.

[0037] Figure 2 Another display panel structure provided by the embodiment of the present disclosure is shown in FIG. 2. In some embodiments, the first back gate signal lead 21 includes a first back gate signal lead first part 211 and a first back gate signal lead second part 212. The first back gate signal lead first part 211 and the first back gate signal lead second part 212 are located on opposite sides of the display area 10 and extend along the pixel unit 12 column direction. The first back gate signal lead first part 211 and the first back gate signal lead second part 212 are respectively electrically connected to the back gate signal transmission layer 11 through a plurality of connection lines 22 to receive the voltage regulating signal and transmit it to the back gate of the vertical double-gate transistor of the pixel unit 12.

[0038] In some scenarios, the voltage of the voltage regulating signal obtained by the pixel unit 12 close to the back gate signal lead is different from the voltage of the voltage regulating signal obtained by the pixel unit 12 far from the first back gate signal lead 21. For example, Figure 2The distance between the right side pixel unit 12 and the right side first back gate signal lead first part 211 is relatively close, and the distance between the right side pixel unit 12 and the right side first back gate signal lead first part 211 is relatively far. The resistance at a certain position on the back gate signal transmission layer 11 is positively correlated with the distance between the position and the first back gate signal lead first part 211. Therefore, the greater the distance between the position on the back gate signal transmission layer 11 and the first back gate signal lead first part 211, the greater the resistance at the position, and further, the greater the voltage drop generated by the farther distance between the back gate signal transmission layer 11 and the first back gate signal lead first part 211. That is, for the right side first back gate signal lead first part 211, the voltage of the voltage regulating signal that the right side first back gate signal lead first part 211 can distribute to the left side pixel unit 12 is smaller than the voltage of the voltage regulating signal that the right side first back gate signal lead first part 211 can distribute to the right side pixel unit 12.

[0039] In Figure 2 In a corresponding embodiment, the first back gate signal lead 21 can include a first back gate signal lead first part 211 and a first back gate signal lead second part 212, and the first back gate signal lead first part 211 and the first back gate signal lead second part 212 are respectively located on opposite sides of the display area 10. The first back gate signal lead first part 211 and the first back gate signal lead second part 212 can be connected to the back gate of each row of pixel units 12 through a plurality of connection lines 22. It should be noted that the first back gate signal lead first part 211 and the first back gate signal lead second part 212 both belong to the first back gate signal lead 21, and therefore the first back gate signal lead is not repeatedly illustrated in Figure 2 In this way, the first back gate signal lead first part 211 and the first back gate signal lead second part 212 can simultaneously provide the same voltage regulating signal for the back gate of the pixel unit 12 from the two sides of the display area 10. For the back gate of the pixel unit 12 far from the first back gate signal lead first part 211, the back gate is closer to the first back gate signal lead second part 212. For the back gate of the pixel unit 12 far from the first back gate signal lead second part 212, the back gate is closer to the first back gate signal lead first part 211. That is, for the back gate of a certain pixel unit 12, there is always a first back gate signal lead 21 close to the back gate. Therefore, the problem of the voltage of the voltage regulating signal obtained by the back gate of a certain pixel unit 12 in each row being low due to the distance between the back gate and the first back gate signal lead 21 being far is further alleviated. That is, through the above arrangement, the problem of the display panel displaying abnormally due to the voltage difference of the voltage regulating signal obtained by the back gates of different pixel units 12 being too large is further alleviated.

[0040] Figure 3 In some embodiments, the first back gate signal lead 21 is arranged around the display area 10.

[0041] Exemplarily, the first back gate signal lead line 21 can be arranged around the display area 10, and after being arranged around the display area 10, the first back gate signal lead line 21 can be connected to both ends of each row of pixel units 12 through a plurality of connection lines 22, and at the same time, provide a voltage regulating signal to each row of pixel units 12 from both ends of each row of pixel units 12. Based on this arrangement, for the back gate of any pixel unit 12, if it is away from the first back gate signal lead line 21 on the left side, it is close to the first back gate signal lead line 21 on the right side; that is, for the back gate of a certain pixel unit 12, it can actually be considered to always be close to the first back gate signal lead line 21, thereby further alleviating the problem that the voltage of the obtained voltage regulating signal of the back gate of a certain pixel unit 12 in each row is low due to the distance from the first back gate signal lead line 21. That is, through the above arrangement, the problem of inconsistent voltage of the voltage regulating signal obtained by the back gate of each pixel unit 12 can be further alleviated, thereby further alleviating the problem of display panel display abnormality caused by too large voltage difference of the voltage regulating signal obtained by the back gates of different pixel units 12.

[0042] Figure 4 Another display panel structure schematic diagram provided by the embodiments of the present disclosure is provided, and in some embodiments, the display area 10 further includes a power voltage signal transmission layer 31; the power voltage signal transmission layer 31 is electrically connected with the back gate signal transmission layer 11 through a via hole 310.

[0043] Exemplarily, the first back gate signal lead line 21 and the power voltage signal transmission layer 31 can be used to provide a voltage regulating signal to the back gate signal transmission layer 11 from the row direction and the column direction at the same time. Based on this arrangement, the problem of display panel display abnormality caused by too large voltage difference of the voltage regulating signal obtained by the back gates of different pixel units 12 in each row can be alleviated through the power voltage signal transmission layer 31.

[0044] Continuing to refer to Figure 4 In some embodiments, the power voltage signal transmission layer 31 and the first back gate signal lead line 21 extend to the binding area 51 of the non-display area 20 respectively.

[0045] Exemplarily, the binding area 51 can be an area for disposing the FPC 511; based on the above-mentioned disposing of the power voltage signal transmission layer 31 and the first back gate signal lead 21 extending to the non-display area 20 respectively, the power voltage signal transmission layer 31 and the first back gate signal lead 21 can be further connected to the FPC 511 disposed in the binding area 51 respectively. In this way, the power voltage signal transmission layer 31 and the first back gate signal lead 21 can obtain the voltage regulating signal relatively independently, that is, if the power voltage signal transmission layer 31 fails, the first back gate signal lead 21 can continue to obtain the voltage regulating signal, and if the first back gate signal lead 21 fails, the power voltage signal transmission layer 31 can also continue to obtain the voltage regulating signal; therefore, it can be avoided that the first back gate signal lead 21 is affected due to the abnormality of the power voltage signal transmission layer 31, or the power voltage signal transmission layer 31 is affected due to the abnormality of the first back gate signal lead 21, and the stability of signal transmission of the display panel is improved.

[0046] Figure 5 Another display panel structure schematic diagram provided by the embodiment of the present disclosure is provided, in some embodiments, the power voltage signal transmission layer 31 extends to the non-display area 20 and is electrically connected with the first back gate signal lead 21 through the via hole 310.

[0047] Exemplarily, the power voltage signal transmission layer 31 can transmit the voltage regulating signal to the first back gate signal lead 21 through the via hole 310, thereby also achieving the transmission of the voltage regulating signal to the back gate of the pixel unit 12 from the row direction and the column direction respectively through the first back gate signal lead 21 and the power voltage signal transmission layer 31 respectively, under the premise of also alleviating the problem of display abnormality of the display panel caused by the voltage difference of the voltage regulating signal obtained between the back gates of different pixel units 12 being too large, reducing the number of lines connected to the binding area 51, and then simplifying the complexity of the lines of the binding area 51.

[0048] Figure 6 Another display panel structure schematic diagram provided by the embodiment of the present disclosure is provided, in some embodiments, the first back gate signal lead 21 includes a grid-shaped wire.

[0049] Exemplarily, the first back gate signal lead wire 21 can transmit the voltage regulating signal to the back gate of the pixel unit 12 of each row. Since the first back gate signal lead wire 21 also has a certain resistance, that is, as the first back gate signal lead wire 21 extends, the voltage regulating signal at different positions has a certain voltage drop, and the back gate of the pixel unit 12 of different rows will also obtain a lower voltage regulating signal as the distance from the first end of the first back gate signal lead wire 21 is greater. Although the voltage drop caused by the resistance of the first back gate signal lead wire 21 itself is small in terms of actual angle, it still exists. In order to improve this, the embodiment of the present disclosure makes the first back gate signal lead wire 21 into a grid-shaped wire. After making the first back gate signal lead wire 21 into a grid-shaped wire, the resistance of the first back gate signal lead wire 21 itself can be reduced. Since the overall resistance of the first back gate signal lead wire 21 is small after forming the grid-shaped wire, the voltage drop caused by the extension of the first back gate signal lead wire 21 is further reduced, so that the voltage gap of the back gate of the pixel unit 12 of different rows caused by the greater distance from the first end of the first back gate signal lead wire 21 is smaller, that is, the voltage of the voltage regulating signal obtained by the back gate of the pixel unit 12 between different rows is closer. Therefore, the above method can alleviate the voltage drop caused by the extension of the first back gate signal lead wire 21, and further alleviate the problem of display panel display abnormality caused by the voltage difference of the voltage regulating signal obtained by the back gate of the pixel unit 12 of different rows due to the extension of the first back gate signal lead wire 21 caused by the resistance of the first back gate signal lead wire 21 itself.

[0050] In some embodiments, the back gate signal transmission layer 11 includes a grid-shaped wire.

[0051] Exemplarily, the back gate signal transmission layer 11 also has a certain resistance, so that as the back gate signal transmission layer 11 extends, a certain voltage drop will still occur for the back gate of the pixel unit 12 at different positions in the same row. Still taking the first back gate signal lead wire 21 as an example, the voltage drop caused by the extension of the first back gate signal lead wire 21 is reduced, so that the voltage drop caused by the extension of the back gate signal transmission layer 11 is greater, and the voltage gap of the back gate of the pixel unit 12 of different rows caused by the greater distance from the first end of the back gate signal transmission layer 11 is greater, that is, the voltage of the voltage regulating signal obtained by the back gate of the pixel unit 12 between different rows is farther apart. Figure 1Corresponding embodiments are taken as an example, the first back gate signal lead 21 on the right side transmits the voltage regulating signal to each row of corresponding back gate signal transmission layer 11 through the connecting line 22, and each row of back gate signal transmission layer transmits to the back gate of the pixel unit 12 at different positions of the row. Since the voltage regulating signal will produce a certain voltage drop along with the extension of the back gate signal transmission layer 11, it is obvious that the farther away from the back gate of the pixel unit 12 on the right side, the lower the voltage of the voltage regulating signal obtained. That is, the back gates of the pixel units 12 at different positions in each row will cause the voltage of the voltage regulating signal obtained to have differences due to the voltage drop of the back gate signal transmission layer 11 itself. In order to improve the above-mentioned problem, the back gate signal transmission layer 11 can be made into a grid-shaped wire in the embodiment of the present disclosure. Making the back gate signal transmission layer 11 into a grid-shaped wire can reduce the resistance of the back gate signal transmission layer 11 itself. Since the overall resistance of the back gate signal transmission layer 11 becomes smaller after forming the grid-shaped wire, the voltage drop along with the extension of the back gate signal transmission layer 11 is further reduced, so that the voltage difference of the back gates of the pixel units 12 at different positions in each row is smaller as the distance from the first back gate signal lead 21 is greater, that is, the voltage of the voltage regulating signal obtained between the back gates of the pixel units 12 at different positions in each row is closer. Therefore, the above-mentioned method can alleviate the voltage drop caused by the extension of the back gate signal transmission layer 11, and further alleviate the problem of display panel display abnormality caused by the voltage difference between the back gates of the pixel units 12 at different positions in each row due to the resistance of the back gate signal transmission layer 11 itself along with the extension of the back gate signal transmission layer 11.

[0052] In some embodiments, the first back gate signal lead 21 and the back gate signal transmission layer 11 are disposed in the same layer as the back gate of the vertical double-gate transistor.

[0053] Exemplarily, generally speaking, the display panel is stacked by multiple film layers, and each layer of film layer is made by different and multiple process technologies. Returning to the embodiment of the present disclosure, the first back gate signal lead 21 can actually be in any film layer, that is, the first back gate signal lead 21 can be in the same film layer as the back gate of the vertical double-gate transistor, or can not be in the same film layer as the back gate of the vertical double-gate transistor. When the first back gate signal lead 21 is not in the same film layer as the back gate of the vertical double-gate transistor, it is necessary to connect the first back gate signal lead 21 and the back gate of the vertical double-gate transistor through a connecting line 22. Figure 4The power voltage signal transmission layer 31 in the corresponding embodiment or the background art is connected to the back gate signal transmission layer 11 in the same layer as the back gate of the vertical double-gate transistor through the via hole 310, so as to provide a voltage regulating signal for the back gate of the vertical double-gate transistor. This method needs to additionally form a metal layer to form the first back gate signal lead 21, and needs to punch a hole to connect the first back gate signal lead 21 to the back gate signal transmission layer 11 in the same layer as the back gate of the vertical double-gate transistor, which increases the process difficulty, and in addition, with the increase of the number of film layers, the unevenness of the film layers is more prominent.

[0054] In the implementation manner of the embodiment of the present disclosure, the first back gate signal lead 21, the back gate signal transmission layer 11 and the back gate of the vertical double-gate transistor can be arranged in the same layer, and in this scheme, the first back gate signal lead 21, the back gate signal transmission layer 11 and the back gate can be arranged by one-time film plating. That is, the general scheme is as follows: a metal layer is plated on the already completed film layer, and then different patterns are formed through exposure, development, etching and the like. The different patterns actually correspond to the first back gate signal lead 21, the back gate signal transmission layer 11 and the back gate of the vertical double-gate transistor, that is, the three functional units can be completed by one process, so that the complexity of the process technology can be greatly simplified.

[0055] Figure 7 In some embodiments, the first back gate signal lead 21 is located between the display area 10 and the shift register 71 of the non-display area 20.

[0056] In the above embodiment, the first back gate signal lead 21 is generally arranged in the non-display area 20, and therefore, in terms of actual process, the first back gate signal lead 21 needs to be arranged at a reasonable position.

[0057] For example, the first back gate signal lead 21 can be arranged above or below the film layer of the dummy pixel unit of the non-display area 20, wherein the dummy pixel unit is a pixel unit arranged in the non-display area 20 and not used for displaying content, so as to avoid the coupling between the voltage regulating signal in the first back gate signal lead 21 and the signals in other lines to affect other lines.

[0058] Figure 8 In some embodiments, the first back gate signal lead 21 and the shift register 71 of the non-display area 20 at least partially overlap in the direction perpendicular to the display panel.

[0059] Exemplarily, the width of the display panel frame can be L1 when the display panel does not have the first back gate signal lead line 21, and the width of the display panel frame becomes L2 when the first back gate signal lead line 21 is additionally arranged between the shift register 71 of the non-display area 20 and the display area 10. Since the first back gate signal lead line 21 needs to occupy a certain space, L2 is generally greater than L1.

[0060] Therefore, in some other embodiments, the first back gate signal lead line 21 can at least partially overlap with the shift register 71 of the non-display area 20, as shown in the following figure. Figure 8

[0061] Figure 9 In some possible implementation manners, the first back gate signal lead line 21 can bypass the shift register 71 and other transistors of the non-display area 20 in the wiring direction of the non-display area 20, so as to avoid affecting the shift register 71 or other transistors, or avoiding the first back gate signal lead line 21 from playing a role similar to the back gate due to passing under the shift register 71 or other transistors.

[0062] Exemplarily, as a transistor also arranged in the display panel, the vertical double-gate transistor of the display area 10 needs the first back gate signal lead line 21 to provide a voltage adjustment signal for adjustment due to the influence of the threshold voltage, and therefore the vertical double-gate transistor in the shift register circuit of the non-display area 20 also has the same or similar problem, which can also be improved.

[0063] ​Therefore, in some embodiments, the non-display area 20 can also be provided with a second back gate signal lead line 23, which can also be connected to the back gate of the vertical double-gate transistor in the shift register 71 through the plurality of connection lines 22 along the column direction of the pixel unit 12, so as to provide a voltage regulating signal for the back gate of the vertical double-gate transistor in the shift register 71, and eliminate the influence of the threshold voltage of the vertical double-gate transistor in the shift register 71 in the non-display area 20.

[0064] In some possible implementations, the second back gate signal lead line 23 can also be arranged along the column direction of the display panel, that is, the second back gate signal lead line 23 can be parallel to the first back gate signal lead line 21.

[0065] Since the voltage regulating signal is transmitted to the vertical double-gate transistor in the shift register 71 in the non-display area 20 through the second back gate signal lead line 23, the influence of the threshold voltage of the vertical double-gate transistor in the shift register 71 in the non-display area 20 can be eliminated. Figure 1 Similarly, in the corresponding embodiments, the influence of the threshold voltage of the vertical double-gate transistor in the shift register 71 in the non-display area 20 can be eliminated by the method, and the shift register 71 is used to control the display of the display panel, so that the problem of display abnormality of the display panel caused by the threshold voltage of the vertical double-gate transistor in the shift register 71 can be alleviated based on the above scheme.

[0066] In some embodiments, the shift register 71 includes a light-emitting control shift register and / or a scanning control shift register; the light-emitting control shift register is used to provide a light-emitting control signal to the pixel driving circuit; and the scanning control shift register is used to provide a scanning control signal to the pixel driving circuit.

[0067] For example, the shift register 71 in the non-display area 20 can include a light-emitting control shift register, which can be referred to as an Emit shift register in some scenarios, and can also include a scanning control shift register, which can also be referred to as a Scan shift register in some scenarios. Obviously, whether it is a light-emitting control shift register or a scanning control shift register, it can include a vertical double-gate transistor, and further, whether it is a light-emitting control shift register or a scanning control shift register, the threshold voltage can affect the light-emitting control signal or the scanning control signal, and further affect the display of the display panel, causing display abnormality of the display panel.

[0068] Therefore, the second back gate signal lead 23 can be connected to the back gate of the vertical double-gate transistor in the light-emitting control shift register to transmit the voltage-regulated signal to the back gate, or can be connected to the back gate of the vertical double-gate transistor in the scanning control shift register to provide the voltage-regulated signal to the back gate. In this way, the influence of the threshold voltage of the vertical double-gate transistor in the light-emitting control shift register and / or the scanning control shift register can be eliminated through the second back gate signal lead 23, thereby improving the stability of the signal and thereby alleviating the problem of display abnormalities of the display panel.

[0069] Figure 10 In some embodiments, the first back gate signal lead 21 is multiplexed as the second back gate signal lead 23.

[0070] Exemplarily, the first back gate signal lead 21 can be used to provide a voltage-regulated signal to the back gate of the vertical double-gate transistor of the display area 10, and the second back gate signal lead 23 can be used to provide a voltage-regulated signal to the back gate of the vertical double-gate transistor of the non-display area 20. If the voltage-regulated signals to be transmitted by the first back gate signal lead 21 and the second back gate signal lead 23 are the same in some possible scenarios, the first back gate signal lead 21 can be multiplexed as the second back gate signal lead 23, i.e., the voltage-regulated signal can actually be transmitted to the back gate of the vertical double-gate transistor of the pixel unit 12 of the display area 10 and the back gate of the vertical double-gate transistor of the shift register 71 of the non-display area 20 through the first back gate signal lead 21. Based on the above arrangement, the second back gate signal lead can no longer be separately arranged, and the voltage-regulated signal can be transmitted to the back gate of the vertical double-gate transistor of the pixel unit 12 of the display area 10 and the back gate of the vertical double-gate transistor of the shift register 71 of the non-display area 20 only by arranging the first back gate signal lead 21. Therefore, the number of wires in the display panel can be reduced, thereby simplifying the complexity of the wires in the display panel to some extent and improving the process yield.

[0071] In some embodiments, the first back gate signal lead 21 and the second back gate signal lead 23 are connected to different voltage terminals.

[0072] Exemplarily, in some possible scenarios, the first back gate signal lead 21 and the second back gate signal lead 23 are both used to transmit a voltage adjustment signal, but the voltages of the voltage adjustment signals provided by the first back gate signal lead 21 and the second back gate signal lead 23 are different due to different transmission objects. Therefore, in some embodiments, the first back gate signal lead 21 and the second back gate signal lead 23 can be connected to different voltage terminals to respectively transmit different voltage adjustment signals to the back gates of the vertical double-gate transistors of the pixel units 12 of the display area 10 and the back gates of the vertical double-gate transistors of the shift register 71 of the non-display area 20, so as to respectively eliminate the influence of the threshold voltages of the vertical double-gate transistors of the pixel units 12 of the display area 10 and the vertical double-gate transistors of the shift register 71 of the non-display area 20, and thus alleviate the problem of display panel display abnormalities.

[0073] In some embodiments, the second back gate signal lead 23 is arranged in the same layer as the first back gate signal lead 21.

[0074] Exemplarily, the first back gate signal lead 21 and the second back gate signal lead 23 can be arranged in different layers or in the same layer. In one possible implementation of the embodiments of the present disclosure, the second back gate signal lead 23 is arranged in the same layer as the first back gate signal lead 21. In this way, the arrangement of the two functional units can be completed at the same time by the same process when the first back gate signal lead 21 and the second back gate signal lead 23 are manufactured. That is, under the premise of the above arrangement, a metal layer can be plated on the original film layer structure, and then the patterns of the first back gate signal lead 21 and the second back gate signal lead 23 can be manufactured at the same time by processes such as exposure, development and etching, thereby reducing the complexity of the manufacturing process.

[0075] Continuing to refer to Figure 9 In some embodiments, the second back gate signal lead 23 is located between the shift register 71 and the display area 10.

[0076] Exemplarily, the second back gate signal lead 23 can be arranged between the display area 10 and the shift register 71 of the non-display area 20, for example, the second back gate signal lead 23 can be arranged above or below the film layer of the dummy pixel unit of the non-display area 20. The dummy pixel unit is a pixel unit arranged in the non-display area 20 and not used for displaying content, so as to avoid coupling between the voltage adjustment signal in the second back gate signal lead 23 and the signals in other lines to affect other lines.

[0077] Figure 11 In some embodiments, the second back gate signal lead 23 at least partially overlaps the shift register 71 of the non-display area 20 along a direction perpendicular to the display panel.

[0078] Exemplarily, the second back-gate signal lead line 23 apparently occupies a certain space; that is, in terms of the display panel, if the second back-gate signal lead line 23 does not exist, the frame width of the display panel is determined by or at least partially determined by the shift register 71 of the non-display area 20 and the first back-gate signal lead line 21; if the display panel only has the first back-gate signal lead line 21, the shift register 71, and does not have the second back-gate signal lead line 23, the frame width of the display panel can be L2, if the second back-gate signal lead line 23 is additionally added between the shift register 71 of the non-display area 20 and the display area 10, the frame width of the display panel becomes the present L4, it is not difficult to understand that L5 is generally greater than L4.

[0079] Therefore, in some other embodiments, the second back-gate signal lead line 23 can at least partially overlap with the shift register 71 of the non-display area 20, as shown in Figure 11 It is apparent that the overlap between the second back-gate signal lead line 23 and the shift register 71 of the non-display area 20 described in the embodiments of the present disclosure does not mean that the second back-gate signal lead line 23 and the shift register 71 are in contact or connected with each other, but only in the viewing angle perpendicular to the display panel, the observed presentation is that the second back-gate signal lead line 23 overlaps with the shift register 71 of the non-display area 20. In this way, the second back-gate signal lead line 23 can share the same frame width space with the shift register 71, if the corresponding frame width of this scheme is L5, it is apparent that L5 can be less than L4; therefore, the width of the non-display area 20 can be further reduced.

[0080] In some possible implementations, the wiring direction of the second back-gate signal lead line 23 in the non-display area 20 can bypass the shift register 71 of the non-display area 20 and other transistors of the non-display area 20, so as to avoid the influence of the second back-gate signal lead line 23 on the shift register 71 or other transistors, or to avoid the second back-gate signal lead line 23 from generating a back-gate-like effect due to passing under the shift register 71 or other transistors.

[0081] The display device provided by the present disclosure also includes the display panel of any one of the above display panel embodiments. Therefore, the display device has the technical features of the display panel provided by the embodiments of the present disclosure, and can achieve the beneficial effects of the display panel provided by the embodiments of the present disclosure. The same parts can be referred to the above description of the display panel provided by the embodiments of the present disclosure, which will not be described here.

[0082] Exemplarily, Figure 12 A structural schematic diagram of a display device provided by an embodiment of the present disclosure is shown. As Figure 12As shown, the display device provided by the embodiments of the present application includes the display panel 100 provided by any of the embodiments of the present application. Figure 12 The embodiments only take the mobile phone as an example to describe the display device, and it can be understood that the display device provided by the embodiments of the present application can be any electronic product with a display function, including but not limited to the following categories: mobile phone, television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interaction terminal, etc., and the embodiments of the present application do not specially limit this.

[0083] The display device provided by the embodiments of the present application includes the display panel described above, and thus the same technical problems as the display panel embodiments described above can also be solved, and the same technical effects can be achieved, and thus will not be described here.

[0084] It should be noted that in this paper, relationship terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "includes a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0085] The above is only a specific embodiment of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized by, The display area and a non-display area surrounding the display area; The display area comprises a back-gate signal transmission layer and a plurality of pixel units arranged in an array; the pixel unit comprises a pixel driving circuit; at least one transistor in the pixel driving circuit is a vertical double-gate transistor; the back gate of the vertical double-gate transistor is electrically connected with the back-gate signal transmission layer; The non-display area is provided with a first back-gate signal lead line; along the pixel unit column direction, the first back-gate signal lead line is electrically connected with the back-gate signal transmission layer through a plurality of connection lines, for receiving a voltage regulating signal and transmitting to the back gate of the vertical double-gate transistor; The non-display area further comprises a shift register; the shift register comprises a plurality of shift register circuits connected in cascade; at least one transistor in the shift register circuit is a vertical double-gate transistor; The non-display area is provided with a second back-gate signal lead line; along the pixel unit column direction, the second back-gate signal lead line is electrically connected with the back gate of the vertical double-gate transistor of the shift register through a plurality of connection lines, for receiving a voltage regulating signal and transmitting to the back gate of the vertical double-gate transistor of the shift register.

2. The display panel of claim 1, wherein, The first back-gate signal lead line comprises a first back-gate signal lead line first part and a first back-gate signal lead line second part; The first back-gate signal lead line first part and the first back-gate signal lead line second part are located on opposite sides of the display area and extend along the pixel unit column direction; The first back-gate signal lead line first part and the first back-gate signal lead line second part are respectively electrically connected with the back-gate signal transmission layer through a plurality of connection lines, for receiving a voltage regulating signal and transmitting to the back gate of the vertical double-gate transistor.

3. The display panel of claim 1, wherein, The first back-gate signal lead line is arranged around the display area.

4. The display panel of claim 1, wherein, The display area further comprises a power voltage signal transmission layer; The power voltage signal transmission layer is electrically connected with the back-gate signal transmission layer through a via hole.

5. The display panel of claim 4, wherein, The power voltage signal transmission layer and the first back-gate signal lead line respectively extend to the binding area of the non-display area.

6. The display panel of claim 4, wherein, The power voltage signal transmission layer extends to the non-display area and is electrically connected with the first back-gate signal lead line through a via hole.

7. The display panel of claim 1, wherein, The first back-gate signal lead line comprises a grid-shaped conductor.

8. The display panel of claim 1, wherein, The back-gate signal transmission layer comprises a grid-shaped conductor.

9. The display panel of claim 1, wherein, The first back-gate signal lead line and the back-gate signal transmission layer are arranged in the same layer with the back gate of the vertical double-gate transistor.

10. The display panel of claim 1, wherein, The first back-gate signal lead line is located between the display area and the shift register of the non-display area.

11. The display panel of claim 1, wherein, Along the direction perpendicular to the display panel, the first back-gate signal lead line at least partially overlaps with the shift register of the non-display area.

12. The display panel of claim 1, wherein, The shift register comprises a light-emitting control shift register and / or a scanning control shift register; The light-emitting control shift register is used for providing a light-emitting control signal to the pixel driving circuit; the scanning control shift register is used for providing a scanning control signal to the pixel driving circuit.

13. The display panel of claim 1, wherein, The first back-gate signal lead line is multiplexed as the second back-gate signal lead line.

14. The display panel of claim 1, wherein, The first back-gate signal lead line and the second back-gate signal lead line are connected with different voltage ends.

15. The display panel of claim 1, wherein, The second back-gate signal lead line is arranged in the same layer with the first back-gate signal lead line.

16. The display panel of claim 1, wherein, The second back gate signal lead line is located between the shift register and the display area.

17. The display panel of claim 1, wherein, In a direction perpendicular to the display panel, the second back gate signal lead line at least partially overlaps the shift register of the non-display area.

18. A display device comprising: A display panel comprising any of the features of claims 1-17.

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