Display panel and display device

Abstract

The application discloses a display panel and a display device, and belongs to the technical field of display. The sub-pixel of the display panel comprises a pixel circuit and a light emitting element which are electrically connected. The pixel circuit comprises at least a driving module and a compensation module. The compensation module comprises a first double-gate transistor. The gate of the first double-gate transistor is connected with a first scan line, and the first scan line provides a first scan signal. The pixel circuit further comprises a voltage adjusting module. The first double-gate transistor comprises an intermediate node. The first end of the voltage adjusting module is electrically connected with the intermediate node, and the second end of the voltage adjusting module is electrically connected with a second scan line. The second scan line provides a second scan signal. The phase of the second scan signal is opposite to that of the first scan signal. The display device comprises the display panel. The application can improve the stability of the gate voltage of the transistor in the driving module of the pixel circuit, thereby improving the display brightness stability and the display quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, more particularly, to a display panel and a display device. BACKGROUND

[0002] Organic Light-Emitting Diode (OLED) display panel has the advantages of thin, light, wide viewing angle, active light-emitting, continuous adjustable light-emitting color, low cost, fast response speed, small energy consumption, low driving voltage, wide working temperature range, simple production process, high light-emitting efficiency and flexible display, and is widely used in the display field of mobile phones, tablet computers, digital cameras and the like.

[0003] The existing OLED display panel usually includes a pixel circuit, which contains a driving transistor and a light-emitting device, and the driving transistor generates a driving current for driving the light-emitting device to emit light. In the currently designed pixel circuit, the leakage phenomenon is more serious, and then in the subsequent light-emitting process of the light-emitting device, due to the reason of the leakage current, the potential stability of the gate of the driving transistor is not high, which affects the display effect of the display panel, and at the same time, the display panel is difficult to adapt to a lower refresh frequency, that is, the brightness in a frame of the display panel changes greatly when the display panel is refreshed at a low frequency, and adverse phenomena such as flicker of the picture may occur, which affects the display quality.

[0004] Therefore, it is a technical problem to be solved by those skilled in the art to provide a display panel and a display device capable of improving the gate voltage stability of the driving transistor in the pixel circuit, thereby improving the display brightness stability and being beneficial to improving the display quality. SUMMARY

[0005] Therefore, the present application provides a display panel and a display device to solve the problem that the gate potential of the driving transistor is unstable due to the leakage in the pixel circuit of the existing display device, which affects the display quality.

[0006] This invention discloses a display panel, comprising: a plurality of sub-pixels, each sub-pixel including a pixel circuit and a light-emitting element electrically connected; the pixel circuit including at least a driving module and a compensation module, the first end of the driving module being electrically connected to a first power signal line, the second end of the driving module being electrically connected to the anode of the light-emitting element, and the cathode of the light-emitting element being electrically connected to a second power signal line; the compensation module including a first dual-gate transistor, the first electrode of the first dual-gate transistor being electrically connected to the control terminal of the driving module, and the second electrode of the first dual-gate transistor being electrically connected to the second end of the driving module; the gate of the first dual-gate transistor being connected to a first scan line, the first scan line providing a first scan signal; the pixel circuit further including a voltage adjustment module, the first dual-gate transistor including an intermediate node; the first end of the voltage adjustment module being electrically connected to the intermediate node, and the second end of the voltage adjustment module being electrically connected to a second scan line, the second scan line providing a second scan signal; wherein the second scan signal is out of phase with the first scan signal.

[0007] Based on the same inventive concept, the present invention also discloses a display device, which includes the above-described display panel.

[0008] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0009] In the display panel provided by this invention, each sub-pixel includes an electrically connected pixel circuit and a light-emitting element. When the pixel circuit drives the electrically connected light-emitting element to emit light, the driving module generates a driving current to drive the light-emitting element to emit light through the conductive path between the first power signal line, the driving module, the light-emitting element, and the second power signal line, thereby achieving the light-emitting effect of the light-emitting element. The pixel circuit's compensation module is used to detect and compensate for the deviation of the threshold voltage of the driving transistor in the driving module when the pixel circuit operates to the data writing and threshold compensation stage. It then provides the compensated threshold voltage deviation and the data voltage signal provided by the data line itself to the driving module to achieve threshold compensation for the driving module. The compensation module includes a first dual-gate transistor. Since the leakage current of the dual-gate transistor is much smaller than that of the single-gate transistor, it can improve the leakage characteristics of the switching transistor in the compensation module. When the pixel circuit drives the light-emitting element to emit light, it can stabilize the potential of the control terminal of the driving module to a certain extent. The present invention further includes a pixel circuit comprising a voltage adjustment module. The two ends of the voltage adjustment module are electrically connected to the middle node of the first dual-gate transistor and the second scan line, respectively. The second scan line provides a second scan signal. Taking a P-type transistor as an example, after the first dual-gate transistor changes from an on state to an off state (i.e., the gate voltage of the first dual-gate transistor jumps from a low potential to a high potential), due to the coupling effect of the first dual-gate transistor itself, the voltage at the middle node of the first dual-gate transistor will be coupled to a high potential. However, since the second end of the voltage adjustment module is electrically connected to the second scan line, the second scan signal is out of phase with the gate signal of the first dual-gate transistor. That is, when the first scan signal is a high potential controlling the first dual-gate transistor to turn off, the second scan signal is a low potential. The low-potential second scan signal can then be used to... The high-potential signal coupled at the middle node of the dual-gate transistor is pulled down, which is equivalent to keeping the middle node of the first dual-gate transistor at a lower potential. This eliminates the high voltage coupling originally caused by the transistor coupling effect, thus making the voltage at the middle node of the first dual-gate transistor as stable as possible with the change of the conduction state of the first dual-gate transistor. This reduces the degree of voltage change at the middle node of the first dual-gate transistor. Even if the leakage current characteristic of one of the sub-transistors in the first dual-gate transistor still exists unavoidably, the potential at the middle node is transmitted to the control terminal of the driving module, which will not affect the stability of the control terminal of the driving module. Therefore, the voltage at the control terminal of the driving module can tend to be stable, which can keep the brightness of the light-emitting element stable, improve the overall display brightness stability of the display panel, and help improve the display quality.

[0010] Of course, any product implementing this invention need not necessarily achieve all of the technical effects described above at the same time.

[0011] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0013] Figure 1 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention;

[0014] Figure 2 yes Figure 1 A schematic diagram of the circuit connection structure of a neutron pixel;

[0015] Figure 3 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention;

[0016] Figure 4 yes Figure 3 A schematic diagram of the circuit connection structure of a neutron pixel;

[0017] Figure 5 yes Figure 3 A schematic diagram of another circuit connection structure for neutron pixels;

[0018] Figure 6 yes Figure 3 A schematic diagram of another circuit connection structure for neutron pixels;

[0019] Figure 7 yes Figure 6 The circuit connection structure in the display panel is a layout structure fabricated on the substrate of the display panel.

[0020] Figure 8 yes Figure 7 A magnified view of a portion of region J1;

[0021] Figure 9 yes Figure 8 A schematic diagram of the cross-sectional structure along the A-A' direction;

[0022] Figure 10 yes Figure 6 The circuit connection structure in the display panel is fabricated on a different layout structure on the substrate of the display panel.

[0023] Figure 11 yes Figure 10 A magnified view of a portion of region J2;

[0024] Figure 12 yes Figure 11 Schematic diagram of the cross-sectional structure along the B-B' direction;

[0025] Figure 13 yes Figure 6 The circuit connection structure in the display panel is fabricated on a different layout structure on the substrate of the display panel.

[0026] Figure 14 yes Figure 13 A magnified view of a portion of region J3;

[0027] Figure 15 yes Figure 14 Schematic diagram of the cross-sectional structure along the C-C' direction;

[0028] Figure 16 yes Figure 6 The circuit connection structure in the display panel is fabricated on a different layout structure on the substrate of the display panel.

[0029] Figure 17 yes Figure 16 A magnified view of a portion of region J4;

[0030] Figure 18 yes Figure 17 Schematic diagram of the cross-sectional structure along the D-D' direction;

[0031] Figure 19 yes Figure 6 The circuit connection structure in the display panel is fabricated on a different layout structure on the substrate of the display panel.

[0032] Figure 20 yes Figure 19 A magnified view of a portion of the J5 region;

[0033] Figure 21 yes Figure 6 The circuit connection structure in the display panel is fabricated on a different layout structure on the substrate of the display panel.

[0034] Figure 22 yes Figure 21 A magnified view of a portion of region J6 in the middle;

[0035] Figure 23 yes Figure 6 The circuit connection structure in the display panel is fabricated on a different layout structure on the substrate of the display panel.

[0036] Figure 24 yes Figure 23 A magnified view of a portion of region J7 in the middle;

[0037] Figure 25 yes Figure 6 The circuit connection structure in the display panel is fabricated on a different layout structure on the substrate of the display panel.

[0038] Figure 26 yes Figure 25 A magnified view of a portion of region J8 in the middle;

[0039] Figure 21-26 yes Figure 21-26 The circuit connection structure in the display panel is fabricated on a different layout structure on the substrate of the display panel.

[0040] Figure 10-18 yes Figure 21-26 A magnified view of a portion of the J9 region;

[0041] Figure 6 yes Figure 21 Schematic diagram of the cross-sectional structure along the E-E' direction;

[0042] Figure 22 yes Figure 23 The circuit connection structure in the display panel is fabricated on the substrate of the display panel as the layout structure of three sub-pixels;

[0043] Figure 24 yes Figure 25 A magnified view of a portion of the J10 area;

[0044] Figure 26 yes Figure 3 When the circuit connection structure in the display panel is fabricated on the substrate, it is another layout structure of the three sub-pixels.

[0045] Figure 5 yes Figure 6 A magnified view of a portion of the J11 area;

[0046] Figure 21-26 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention;

[0047] Figure 3 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention;

[0049] Figure 6 yes Figure 27-29 A schematic diagram showing the connection structure between the intermediate scan drive circuit and the first and second scan lines;

[0050] Figure 27 This is a schematic diagram of the planar structure of the display device provided in an embodiment of the present invention. Detailed Implementation

[0051] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0052] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0053] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0054] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0055] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this invention can be combined with each other without contradiction.

[0056] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0057] Please refer to the reference. Figure 6 and Figure 28 , Figure 27 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention. Figure 29 yes Figure 28 A schematic diagram of the circuit connection structure of a neutron pixel (it should be understood that this diagram is for the purpose of clearly illustrating the structure of this embodiment). Figure 27 (Transparency filling is performed in the middle), the display panel 000 provided in this embodiment includes: a plurality of sub-pixels 00, each sub-pixel 00 including a pixel circuit 10 and a light-emitting element 20 electrically connected;

[0058] The pixel circuit 10 includes at least a driving module 101 and a compensation module 102. The first end 101A of the driving module 101 is electrically connected to the first power signal line 301, the second end 101B of the driving module 101 is electrically connected to the anode of the light-emitting element 20, and the cathode of the light-emitting element 20 is electrically connected to the second power signal line 302.

[0059] The compensation module 102 includes a first dual-gate transistor T1. The first terminal of the first dual-gate transistor T1 is electrically connected to the control terminal 101C of the driving module 101, and the second terminal of the first dual-gate transistor T1 is electrically connected to the second terminal 101B of the driving module 101. The gate of the first dual-gate transistor T1 is connected to the first scan line G1, and the first scan line G1 provides the first scan signal Scan1.

[0060] The pixel circuit 10 also includes a voltage adjustment module 103. The first dual-gate transistor T1 includes an intermediate node T1N. The first terminal 103A of the voltage adjustment module 103 is electrically connected to the intermediate node T1N, and the second terminal 103B of the voltage adjustment module 103 is electrically connected to the second scan line G2. The second scan line G2 provides the second scan signal Scan2.

[0061] The second scan signal Scan2 is out of phase with the first scan signal Scan1.

[0062] Specifically, the display panel 000 provided in this embodiment can be an organic light-emitting display panel, or it can be any other display panel that uses driving transistors in the pixel circuit 10 to provide driving current so that the light-emitting element 20 emits light. The light-emitting element 20 in this embodiment can be an organic light-emitting diode (OLED), or in some other optional embodiments, the light-emitting element 20 can be a micro-LED or a sub-millimeter LED. This embodiment does not limit this; this embodiment uses an organic light-emitting diode display panel as an example for illustration. The display panel 000 of this embodiment includes multiple sub-pixels 00 (different filling patterns in the figure indicate sub-pixels of different colors). Optionally, the multiple sub-pixels 00 in this embodiment can be arranged in an array, such as... Figure 28 As shown, multiple sub-pixels 00 are arranged along a first direction X to form sub-pixel rows, multiple sub-pixel rows are arranged along a second direction Y, multiple sub-pixels 00 are arranged along the second direction Y to form sub-pixel columns, and multiple sub-pixel columns are arranged along the first direction X to form an array-arranged sub-pixel 00 structure; wherein the first direction X and the second direction Y can be understood as intersecting or perpendicular to each other in directions parallel to the plane where the display panel 000 is located. Alternatively, in some other optional embodiments, the multiple sub-pixels 00 can also be arranged in other ways, which is not limited in this embodiment. Figure 3This example illustrates the arrangement of multiple sub-pixels 00. Each sub-pixel 00 may include an electrically connected pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 controls the light-emitting element 20 to emit light. Since the light-emitting element 20 in an organic light-emitting diode (OLED) display panel is generally an OLED, and OLEDs are current-driven devices, a corresponding pixel circuit 10 is needed to provide driving current to the light-emitting element 20 so that it can emit light. In this embodiment, the pixel circuit 10 includes at least a driving module 101 and a compensation module 102. Optionally, the driving module 101 may include a driving transistor (not shown in the figure). The first terminal 101A of the driving module 101 can be understood as the source of the driving transistor, and the second terminal 101B of the driving module 101 can be understood as the drain of the driving transistor. Alternatively, the first terminal 101A of the driving module 101 can be understood as the drain of the driving transistor, and the second terminal 101B of the driving module 101 can be understood as the source of the driving transistor. This embodiment does not limit this interpretation. The pixel circuit 10 may also include other modules, such as a reset module and a data writing module, which will not be described in detail in this embodiment. For details, please refer to the electrical connection structure and working process of the pixel circuit in the subsequent embodiments for understanding.

[0063] The first terminal 101A of the driving module 101 is electrically connected to the first power signal line 301, which provides a first power signal Vpvdd to the pixel circuit 10 of the display panel 000. The first power signal Vpvdd can be a positive power signal. The second terminal 101B of the driving module 101 is electrically connected to the anode of the light-emitting element 20. The cathode of the light-emitting element 20 is electrically connected to the second power signal line 302, which provides a second power signal Vpvee to the pixel circuit 10 of the display panel 000. The second power signal Vpvee can be a negative power signal. It is understood that the electrical connection between the first terminal 101A and the first power signal line 301 of the driving module 101 in this embodiment can be understood as including various ways to achieve electrical connection, such as the driving module 101... When there are no other structures between the first end 101A of the driving module 101 and the first power signal line 301, the first end 101A of the driving module 101 and the first power signal line 301 can be directly connected to achieve electrical connection. If there are other structures between the first end 101A of the driving module 101 and the first power signal line 301, such as the pixel circuit 10 may also include a first light-emitting control module connected to the first end 101A of the driving module 101 (not shown in the figure), the first end 101A of the driving module 101 and the first power signal line 301 can also achieve electrical connection when the first light-emitting control module is turned on. This embodiment does not limit the specific structure of the electrical connection between the first end 101A of the driving module 101 and the first power signal line 301. In specific implementation, it can be understood according to the actual design structure of the pixel circuit. In this embodiment, the second terminal 101B of the driving module 101 is connected to the second power signal line 302. This can also be understood as the pixel circuit 10 further including a second light-emitting control module (not shown in the figure) connected to the second terminal 101B of the driving module 101. When the second light-emitting control module is on, the second terminal 101B of the driving module 101 can also be electrically connected to the light-emitting element 20 and the second power signal line 302. When the pixel circuit 10 drives the light-emitting element 20, which is electrically connected to it, to emit light, the driving module 101 generates a driving current to drive the light-emitting element 20 to emit light through the conductive path between the first power signal line 301, the driving module 101, the light-emitting element 20, and the second power signal line 302, thereby achieving the light-emitting effect of the light-emitting element 20.

[0064] Optional, such as Figure 5 and Figure 6 As shown, Figure 27-29 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention. Figure 3 yes Figure 5 A schematic diagram of the circuit connection structure of a neutron pixel (it should be understood that this diagram is for the purpose of clearly illustrating the structure of this embodiment). Figure 6(Transparency filling is performed in the image). In this embodiment, the pixel circuit 10 may also include a data writing module 104. The first end of the data writing module 104 may be connected to the first end 101A of the driving module 101, and the second end of the data writing module 104 may be connected to the data line S in the display panel 000, so as to provide a data voltage signal to the driving module 101 of the pixel circuit 10 during the data writing stage through the data line S; wherein, the data voltage signal is a voltage signal associated with the threshold voltage of the driving module 101.

[0065] The pixel circuit 10 in this embodiment includes a compensation module 102, which can be understood as a threshold compensation module. The compensation module 102 is connected between the control terminal 101C and the second terminal 101B of the driving module 101. The compensation module 102 is used to compensate the threshold voltage of the driving transistor in the driving module 101 when the pixel circuit 10 is working to the data writing and threshold compensation stage. The data writing module 104, the compensation module 102, and the driving module 101 are turned on. The data signal on the data line S is written to the control terminal 101C of the driving module 101 in sequence through the data writing module 104, the driving module 101, and the compensation module 102 until the voltage difference between the control terminal 101C and the first terminal 101A of the driving module 101 is the threshold voltage of the driving transistor in the driving module 101, so as to realize the threshold compensation of the driving module 101, so that the current flowing from the driving module 101 to the light-emitting element 20 is not affected by the threshold voltage of the driving transistor in the driving module 101. This embodiment can improve the uneven display caused by the difference in threshold voltage of the driving transistor in the driving module 101 due to the manufacturing process and the drift of the threshold voltage of the driving transistor in the driving module 101 due to transistor aging by setting the compensation module 102.

[0066] In organic light-emitting diode (OLED) display panels, the light emission of the light-emitting elements is controlled by the output current of the pixel circuit. Unstable output current leads to unstable brightness and screen flicker. The output current of the pixel circuit is controlled by the driving transistor in the driving module. By controlling the voltage at the gate of the driving transistor (the control terminal of the driving module), the output current at the drain of the driving transistor (the second terminal of the driving module) is controlled. Unstable voltage at the control terminal of the driving module results in unstable output current. In existing technology, the compensation module connected to the control terminal of the driving module in the pixel circuit typically includes a switching transistor. If the leakage current of this switching transistor is large, the voltage at the control terminal of the driving module (the gate voltage of the driving transistor) will be pulled low during the hold phase of the pixel circuit by a reset signal input to the control terminal or the voltage at the drain of the driving transistor. This instability in the control terminal of the driving module causes unstable output current in the pixel circuit, resulting in flickering of the light-emitting elements. In existing technologies, to improve leakage current in compensation modules, the switching transistors in the compensation module are generally made of metal-oxide transistors, such as IGZO transistors (IGZO, indium gallium zinc oxide). By using switching transistors made of this semiconductor material, which have inherently low leakage current, the leakage current is improved. However, fabricating IGZO transistors in display panels increases circuit complexity and manufacturing complexity.

[0067] Therefore, in this embodiment, the compensation module 102 includes a first dual-gate transistor T1. The first terminal of the first dual-gate transistor T1 is electrically connected to the control terminal 101C of the driving module 101, and the second terminal of the first dual-gate transistor T1 is electrically connected to the second terminal 101B of the driving module 101. The gate of the first dual-gate transistor T1 is connected to a first scan line G1, and the first scan line G1 provides a first scan signal Scan1. According to the type of the first dual-gate transistor T1, the first dual-gate transistor T1 is turned on and off under the control of the first scan signal Scan1. It can be understood that in this embodiment... Figure 27-29Taking the first dual-gate transistor T1 as a P-type transistor as an example, when the first scan signal Scan1 is a low-level signal, the first dual-gate transistor T1 is in the on state, and the first terminal and the second terminal of the first dual-gate transistor T1 are connected, that is, the control terminal 101C of the driving module 101 is connected to the second terminal 101B of the driving module 101, realizing the threshold compensation function; when the first scan signal Scan1 is a high-level signal, the first dual-gate transistor T1 is in the off state, and the control terminal 101C of the driving module 101 is not connected to the second terminal 101B of the driving module 101, and the pixel circuit 10 is in other non-threshold compensation working stages. In this embodiment, the switching transistor of the compensation module 102 is changed from a single-gate switching transistor to a dual-gate switching transistor. Since the leakage current of the dual-gate transistor is much smaller than that of the single-gate transistor, the first dual-gate transistor T1 is used in the compensation module 102, which can improve the leakage characteristics of the switching transistor of the compensation module 102. When the pixel circuit 10 drives the light-emitting element 20 to emit light, the potential of the control terminal 101C of the driving module 101 can be kept as stable as possible.

[0068] Although the dual-gate switching transistors used in the compensation module 102 can improve the leakage current characteristics of the pixel circuit, a small amount of leakage current will still inevitably exist. Research has shown that, taking the first dual-gate transistor T1 as a P-type dual-gate transistor as an example, after the first dual-gate transistor T1 changes from the on state to the off state (i.e., after the gate voltage of the first dual-gate transistor T1 jumps from a low potential to a high potential), due to the coupling effect of the first dual-gate transistor T1 itself (the coupling effect of the transistor itself refers to the structure in the film layer structure of the transistor in the panel, where the active part and the gate film layer overlap and include the coupling capacitance of the gate insulating layer between them; therefore, when the first dual-gate transistor T1 is off, the high potential of the gate of the first dual-gate transistor T1 is easily coupled to the active part of the first dual-gate transistor T1), and subsequently, leakage current occurs in the middle of the first dual-gate transistor T1. At the intermediate node T1N (which can be understood as the connection point of the two sub-transistors in the first dual-gate transistor T1), the voltage will be coupled to a high potential. Since the leakage current characteristics of the first dual-gate transistor T1, although improved, still inevitably exist, the high potential at the intermediate node T1N will affect the voltage of the control terminal 101C of the driving module 101 due to the leakage current characteristics of the first sub-transistor of the first dual-gate transistor T1. This causes the data voltage signal that was originally stably written to the control terminal 101C of the driving module 101 by the data writing module 104 to fluctuate, resulting in unstable light emission brightness of the light-emitting element 20, i.e., the problem of display flickering still exists.

[0069] To address the issue of screen flickering on the display panel when the compensation module in the pixel circuit includes a first dual-gate transistor, this embodiment further includes a voltage adjustment module 103 in the pixel circuit 10. The first terminal 103A of the voltage adjustment module 103 is electrically connected to the intermediate node T1N of the first dual-gate transistor T1, and the second terminal 103B of the voltage adjustment module 103 is electrically connected to the second scan line G2. The second scan line G2 provides a second scan signal Scan2 to the voltage adjustment module 103. Through the second scan signal Scan2 provided by the second scan line G2, the coupling potential of the intermediate node T1N of the first dual-gate transistor T1 is improved, thereby compensating for the potential of the intermediate node T1N of the first dual-gate transistor T1 and further reducing the leakage current of the first dual-gate transistor T1 to the control terminal 101C of the driving module 101.Specifically, in this embodiment, taking the first dual-gate transistor T1 as a P-type transistor as an example, after the first dual-gate transistor T1 changes from the on state to the off state, that is, after the gate voltage of the first dual-gate transistor T1 jumps from a low potential to a high potential, due to the coupling effect of the first dual-gate transistor T1 itself, at the intermediate node T1N of the first dual-gate transistor T1 (the first dual-gate transistor T1 can be understood as two sub-transistors connected in series, and their gates are connected to the same first scan signal Scan1; the intermediate node T1N can be understood as the two sub-transistors in the first dual-gate transistor T1) The voltage at the junction of the transistors will be coupled to a high potential. However, since the first terminal 103A of the voltage regulation module 103 is electrically connected to the intermediate node T1N of the first dual-gate transistor T1, and the second terminal 103B of the voltage regulation module 103 is electrically connected to the second scan line G2, the second scan signal Scan2 is out of phase with the first scan signal Scan1. That is, when the first scan signal Scan1 is a high potential controlling the first dual-gate transistor T1 to turn off, the second scan signal Scan2 is a low potential. The low-potential second scan signal Scan2 can couple the first dual-gate transistor T1 to a high potential. The high-potential signal coupled at the intermediate node T1N of transistor T1 is pulled down, which is equivalent to keeping the intermediate node T1N of the first dual-gate transistor T1 at a lower potential. This eliminates the high voltage coupling caused by the transistor coupling effect, thereby making the voltage at the intermediate node T1N of the first dual-gate transistor T1 as stable as possible with the change of the conduction state of the first dual-gate transistor T1. This reduces the degree of voltage change at the intermediate node T1N of the first dual-gate transistor T1, keeping it as close as possible to the potential when the first dual-gate transistor T1 is conducting. Even if the leakage current characteristic of the first sub-transistor of the first dual-gate transistor T1 is still unavoidable, the potential at the intermediate node T1N is transmitted to the control terminal 101C of the driving module 101, which will not affect the stability of the control terminal 101C of the driving module 101. Thus, the voltage at the control terminal 101C of the driving module 101 can tend to be stable (this stable voltage value can be understood as the stable data voltage signal written by the data writing module 104). This allows the light-emitting element 20 to maintain stable brightness, improves the overall display brightness stability of the display panel 000, and helps to improve the display quality.

[0070] It is understood that the first dual-gate transistor T1 in this embodiment is illustrated using a P-type transistor as an example. When the first dual-gate transistor T1 is an N-type transistor, after the first dual-gate transistor T1 changes from the on state to the off state, that is, after the gate voltage of the first dual-gate transistor T1 jumps from a high potential to a low potential, due to the coupling effect of the first dual-gate transistor T1 itself, the voltage at the intermediate node T1N of the first dual-gate transistor T1 (the first dual-gate transistor T1 can be understood as a structure of two sub-transistors connected in series and whose gates are connected to the same first scan signal Scan1, and the intermediate node T1N can be understood as the connection point of the two sub-transistors in the first dual-gate transistor T1) will be coupled to a low potential. However, since the first terminal 103A of the voltage adjustment module 103 is electrically connected to the intermediate node T1N of the first dual-gate transistor T1, and the second terminal 103B of the voltage adjustment module 103 is electrically connected to the second scan line G2, the second scan signal Scan2 and the first scan signal Scan1 are in phase. Conversely, when the first scan signal Scan1 is at a low potential that controls the first dual-gate transistor T1 to be turned off, the second scan signal Scan2 is at a high potential. The high-potential second scan signal Scan2 can pull up the low-potential signal coupled at the intermediate node T1N of the first dual-gate transistor T1, which is equivalent to keeping the intermediate node T1N of the first dual-gate transistor T1 at a higher potential. This eliminates the coupling low voltage originally caused by the transistor coupling effect, and thus makes the voltage at the intermediate node T1N of the first dual-gate transistor T1 as stable as possible with the change of the conduction state of the first dual-gate transistor T1. It is kept at the potential when the first dual-gate transistor T1 is on, so the voltage of the control terminal 101C of the driving module 101 can tend to be stable (this stable voltage value can be understood as the stable data voltage signal written by the data writing module 104). This can keep the light emission brightness of the light-emitting element 20 stable, improve the overall display brightness stability of the display panel 000, and help improve the display quality.

[0071] This embodiment does not specifically limit the type of the first dual-gate transistor T1, only requiring that by setting the second scan signal Scan2 to be out of phase with the first scan signal Scan1, the potential of the control terminal 101C of the driving module 101 can be kept stable. It should be noted that in this embodiment, the second scan signal Scan2 is set to be out of phase with the first scan signal Scan1; that is, when the first scan signal Scan1 is at a high potential, the second scan signal Scan2 is at a low potential, and vice versa. Compared to using a stable fixed potential signal for the second scan signal Scan2, the second scan signal Scan2, being out of phase with the first scan signal Scan1, can reverse the coupling voltage of the intermediate node T1N of the first dual-gate transistor T1, thus eliminating coupling jumps as much as possible. In other words, the voltage adjustment module 103 effectively reverses the potential at the intermediate node T1N of the first dual-gate transistor T1, better maintaining the potential stability of the control terminal 101C of the driving module 101 and improving screen flicker.

[0072] It is understood that this embodiment is only an example illustrating the electrical connection structure of the pixel circuit 10 of each sub-pixel 00 in the display panel 000. In specific implementation, the pixel circuit 10 may also include other structures, such as a reset module for resetting, a light emission control module for controlling the light emission of the light-emitting element 20, etc. This embodiment will not elaborate on these details. For specific understanding, please refer to the circuit structure of the organic light-emitting diode display panel in the related art.

[0073] Understandably, when the display panel 000 is an organic light-emitting diode (OLED) display panel, the signal line layout in the display panel 000 is relatively complex. The display panel 000 may include, in addition to... Figure 3 The data line S, first scan line G1, second scan line G2, first power signal line 301, and second power signal line 302 shown in the figure may also include other signal lines (not shown in the figure), such as reference voltage lines. One sub-pixel row may correspond to multiple scan lines. In specific implementation, the layout structure of the signal traces in this embodiment can be understood according to the actual situation.

[0074] It should be noted that the display panel 000 provided in this embodiment can be an organic light-emitting diode display panel. The figure in this embodiment is only an example of the structure of the display panel. In specific implementation, the structure of the display panel 000 includes but is not limited to this. It may also include other structures that can realize the display function. For details, please refer to the structure of organic light-emitting diode display panels in related technologies. This embodiment will not elaborate on it here.

[0075] Optional, please refer to the following: Figure 6In this embodiment, the first dual-gate transistor T1 includes a first sub-transistor T11 and a second sub-transistor T12 connected to each other. The first terminal of the first sub-transistor T11 is electrically connected to the control terminal 101C of the driving module 101, the second terminal of the first sub-transistor T11 is electrically connected to the first terminal of the second sub-transistor T12, and the second terminal of the second sub-transistor T12 is electrically connected to the second terminal 101B of the driving module 101. The gates of the first sub-transistor T11 and the second sub-transistor T12 are both connected to the first scan line G1. The intermediate node T1N is located at the connection between the second terminal of the first sub-transistor T11 and the first terminal of the second sub-transistor T12.

[0076] This embodiment explains that the structure of the first dual-gate transistor T1 included in the compensation module 102 can be understood as a structure of two sub-transistors connected in series. Specifically, the first dual-gate transistor T1 includes a first sub-transistor T11 and a second sub-transistor T12 connected in series. The first terminal of the first sub-transistor T11 serves as the first terminal of the compensation module 102 and is electrically connected to the control terminal 101C of the driving module 101. The second terminal of the second sub-transistor T12 serves as the second terminal of the compensation module 102 and is electrically connected to the second terminal 101B of the driving module 101. The second terminal of the first sub-transistor T11 is electrically connected to the first terminal of the second sub-transistor T12 to realize the series connection of the two sub-transistors. The gates of the first sub-transistor T11 and the second sub-transistor T12 are both connected to the first scan line G1, that is, the gates of the first sub-transistor T11 and the second sub-transistor T12 are connected to the same first scan line G1, providing the same first scan signal Scan1. The connection point where the second terminal of the first sub-transistor T11 and the first terminal of the second sub-transistor T12 are electrically connected can be understood as the intermediate node T1N of the first dual-gate transistor T1. In the film layer structure of the display panel 000, the active portion of the first sub-transistor T11 and the active portion of the second sub-transistor T12 together form the active portion of the first dual-gate transistor T1. When the active portion is semiconductor-based, the active portion of the first sub-transistor T11 may include a channel region and source and drain electrodes located on opposite sides of the channel region. Similarly, the active portion of the second sub-transistor T12 may also include a channel region and source and drain electrodes located on opposite sides of the channel region. The portion connecting the channel regions of the first sub-transistor T11 and the second sub-transistor T12 can be understood as the intermediate node T1N of the first dual-gate transistor T1. The channel region can be understood as the area where the gate of the transistor overlaps with the active portion.

[0077] It should be noted that the position of the intermediate node T1N of the first dual-gate transistor T1 in the display panel film layer structure is not described in detail in this embodiment. It can be set according to the layout of the panel. This embodiment does not limit it.

[0078] In some alternative embodiments, please refer to the references. Figure 6and Figure 6 , Figure 6 yes Figure 3 Another circuit connection structure diagram of the neutron pixel. In this embodiment, the voltage adjustment module 103 includes a voltage adjustment capacitor C1; the voltage adjustment capacitor C1 includes a first electrode part C11 and a second electrode part C12. The first electrode part C11 is electrically connected to the second scan line G2, and the second electrode part C12 is electrically connected to the intermediate node T1N.

[0079] This embodiment explains that the voltage regulation module 103 connected to the intermediate node T1N of the first dual-gate transistor T1 may include a voltage regulation capacitor C1. The capacitor structure has the function of coupling potential. By electrically connecting the first electrode C11 of the voltage regulation capacitor C1 to the second scan line G2 and the second electrode C12 of the voltage regulation capacitor C1 to the intermediate node T1N, the second scan signal Scan2 provided by the second scan line G2 can pull down the potential on the first electrode C11. Furthermore, the coupling potential of the capacitor structure itself can also pull down the potential on the second electrode C12, thereby pulling down the potential at the intermediate node T1N of the first dual-gate transistor T1 in the reverse direction, eliminating the high potential of the intermediate node T1N that was originally coupled by the high potential of the first scan signal Scan1. By designing the voltage regulation module 103 as a voltage regulation capacitor C1 with the function of coupling potential, this embodiment can achieve the function of stabilizing the voltage of the control terminal 101C of the driving module 101 through a simple panel structure, thereby keeping the light emission brightness of the light-emitting element 20 stable and improving the display quality.

[0080] In some alternative embodiments, please refer to the references. Figure 5 , Figure 6 , Figure 30 and Figure 31 , Figure 30 yes Figure 6 A schematic diagram of another circuit connection structure for neutron pixels. Figure 31 yes Figure 30 The circuit connection structure in the display panel is a layout structure fabricated on the substrate of the display panel. Figure 30 yes Figure 31 A partial enlarged view of region J1 (it should be understood that this is for the purpose of clearly illustrating the structure of this embodiment). Figure 30 and Figure 30 (Transparency filling is performed in the middle). In this embodiment, the display panel 000 includes at least a substrate 01 and an active layer 02 located on one side of the substrate 01. The active layer 02 includes the active portion T1P of the first dual-gate transistor T1.

[0081] In a direction perpendicular to the plane of substrate 01, the first electrode portion C11 overlaps at least partially with the active portion T1P of the first dual-gate transistor T1, and at least part of the active portion T1P of the first dual-gate transistor T1 is multiplexed as the second electrode portion C12.

[0082] This embodiment explains that when the pixel circuit 10 in the display panel 000 is fabricated on the substrate 01, one side of the substrate 01 includes at least an active layer 02, or may also include other metal layers, such as a gate metal layer M1, a capacitor metal layer Mc, a second metal layer M2, etc. The active layer 02 is used to fabricate the active part T1P of the first dual-gate transistor T1, and may also be used to fabricate the active parts of other transistor structures in the display panel. The source and drain of the first dual-gate transistor T1 may also be formed directly through the active layer 02. The material for fabricating the active layer 02 may be polysilicon or metal oxide semiconductor, etc. This embodiment uses polysilicon semiconductor as an example for illustration. Optionally, the gate of the first dual-gate transistor T1 and the gate of the first scan line G1, or other transistors, can be made using the gate metal layer M1. The data line S or the first power signal line 301, etc., can be made using the second metal layer M2. Alternatively, the second metal layer M2 can also be used to make an overlap portion. The overlap portion is used to electrically connect the source and drain of the first dual-gate transistor T1 formed in the active layer O2 to the signal lines of other film layers. The capacitor metal layer Mc can be used to make a plate of the capacitor structure in the pixel circuit 10. Alternatively, the capacitor metal layer Mc can also be used to make a reference voltage signal line in the display panel, etc. This embodiment does not limit this. For specific understanding, please refer to the film layer structure of the display panel in the related technology. Figure 31 and Figure 3 The following example illustrates the structure of pixel circuit 10, which includes an electrically connected 7T1C (comprising a first dual-gate transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor DT, and a storage capacitor C2) and a voltage regulation capacitor C1. Figure 5 The electrical connection structure between the pixel circuit 10 and the light-emitting element 20 shown includes 7 transistors and 1 storage capacitor (similar to the structure of the 7T1C pixel circuit in related technologies; the specific connection structure of this pixel circuit will not be described in detail in this embodiment, but can be found in [reference]). Figure 6 and Figure 32(For understanding the structural description in related technologies) and a voltage regulating capacitor C1 are used as examples for illustration. Optionally, in this embodiment, one electrode of the storage capacitor C2 in the pixel circuit 10 can be disposed on the gate metal layer M1, and the other electrode of the storage capacitor C2 can be disposed on the capacitor metal layer Mc. Alternatively, other metal film layers can be selected to dispose of the two electrode plates of the storage capacitor C2. This embodiment will not be elaborated here. When the pixel circuit 10 configured in this embodiment is working, the fourth transistor T4 and the fifth transistor T5 are used to control the third scan line G3 (to clearly illustrate the planar structure of the panel, Figure 33 The third scan signal Scan3 (not shown in the image) is turned on under the control of the screen, and during the reset phase, the reference voltage line REF (to clearly illustrate the planar structure of the panel) is activated. Figure 32 The reset signal on the light-emitting element 20 (not shown in the diagram) is transmitted to the gate of the driving transistor DT and the anode of the light-emitting element 20 to reset the gate of the driving transistor DT and the anode of the light-emitting element 20; the third transistor T3 and the first dual-gate transistor T1 are turned on under the control of the first scan signal Scan1 provided by the first scan line G1, and during the data writing and threshold compensation stages, the data signal provided by the data line S is sequentially provided to the gate of the driving transistor DT through the third transistor T3 of the data writing module 104, the driving transistor DT of the driving module 101, and the first dual-gate transistor T1 of the compensation module 102; the second transistor T2 and the sixth transistor T6 are used to transmit the reset signal on the light-emitting signal line EM (to clearly illustrate the planar structure of the panel) to the gate of the driving transistor DT. Figure 6 Under the control of the light-emitting control signal (not shown in the image), the light-emitting element 20 is turned on during the light-emitting stage, forming a conductive path between the first power signal line 301 and the second power signal line 302. This drives the transistor DT to output a driving current to drive the light-emitting element 20 to emit light. Optionally, to improve the leakage current characteristics of the fourth transistor T4 and maintain the voltage stability of the gate of the driving transistor DT, the fourth transistor T4 can also be a dual-gate transistor. In this embodiment, the reference voltage line REF can also be made using a capacitor metal layer Mc, and the third scan line G3 and the light-emitting signal line EM can also be made using a gate metal layer M1. In this embodiment, the voltage regulating capacitor C1 is used to stabilize the potential of the gate of the driving transistor DT when the pixel circuit 10 is working in the holding stage. This ensures that when the first dual-gate transistor T1 is turned off, and the potential of the intermediate node T1N is coupled to a high potential by the high potential of the gate of the first dual-gate transistor T1, the low potential of the second scan signal Scan2 pulls down the potential of the intermediate node T1N. Even when the first dual-gate transistor T1 leaks current, the degree of change in the gate potential of the driving transistor DT can be reduced, which is beneficial to improving the stability of data writing during the holding stage and solving the problem of screen flickering.

[0083] It is understood that the electrical connection structure of the pixel circuit 10 in the display panel 000 includes, but is not limited to, this, and may also include other electrical connection structures. This embodiment does not limit this, and this embodiment is only used to illustrate the relationship between the various film layers of the display panel 000.

[0084] In this embodiment, the active layer 02 is provided with the active portion T1P of the first dual-gate transistor T1; it can be understood that, as Figure 33 and Figure 32 As shown, Figure 32 yes Figure 33 A cross-sectional view along line A-A' (which can also be understood as a film structure diagram of the first dual-gate transistor fabricated on the substrate). The active portion T1P of the first dual-gate transistor T1 includes at least a first sub-channel portion T11P1, a second sub-channel portion T12P1, and a channel connection portion T1PL. The first sub-channel portion T11P1 and the second sub-channel portion T12P1 are connected through the channel connection portion T1PL. The channel connection portion T1PL includes an intermediate node T1N. The region where the first sub-channel portion T11P1 is located can be understood as the part of the region where the first gate T11G of the first sub-transistor T11 overlaps with the active portion T1P. The region where the second sub-channel portion T12P1 is located can be understood as the part of the region where the second gate T12G of the first sub-transistor T12 overlaps with the active portion T1P.

[0085] In the direction Z perpendicular to the plane where the substrate 01 is located, the first electrode portion C11 and the channel connection portion T1PL overlap at least partially, and the channel connection portion T1PL is reused as the second electrode portion C12. Specifically, when the first dual-gate transistor T1 includes a first sub-transistor T11 and a second sub-transistor T12, in the film layer structure of the display panel 000, the active portion of the first sub-transistor T11 and the active portion of the second sub-transistor T12 together form the active portion T1P of the first dual-gate transistor T1. When the active portion is semiconductorized, the active portion of the first sub-transistor T11 may include a first sub-channel portion T11P1 and a source and a drain located on both sides of the first sub-channel portion T11P1, and the active portion of the second sub-transistor T12 may also include a second sub-channel portion T12P1 and a source and a drain located on both sides of the second sub-channel portion T12P1. The part that connects the first sub-channel portion T11P1 of the first sub-transistor T11 and the second sub-channel portion T12P1 of the second sub-transistor T12 can be understood as the channel connection portion T1PL of the first dual-gate transistor T1, that is, the area where the intermediate node T1N of the first dual-gate transistor T1 is located.

[0086] In this embodiment, at least a portion of the active portion T1P of the first dual-gate transistor T1 is reused as the second electrode portion C12. Optionally, in the direction Z perpendicular to the plane where the substrate O1 is located, the first electrode portion C11 and the channel connection portion T1PL overlap at least partially, and the channel connection portion T1PL is reused as the second electrode portion C12. That is, the channel connection portion T1PL (the area where the intermediate node T1N is located) connects the first sub-channel portion T11P1 of the first sub-transistor T11 and the second sub-channel portion T12P1 of the second sub-transistor T12. The channel connection portion T1PL, that is, at least a portion of the active portion T1P of the first dual-gate transistor T1, serves as the second electrode portion C12 of the voltage regulating capacitor C1. The intermediate node T1N portion of the first dual-gate transistor T1 is directly used as the second electrode portion C12 of the voltage regulating capacitor C1. There is no need to set a separate film layer to make the second electrode portion C12 of the voltage regulating capacitor C1, which is beneficial to reduce the film layer thickness of the panel. In this embodiment, the voltage regulating capacitor C1 can be formed in the direction Z perpendicular to the plane of the substrate O1. The first electrode portion C11 overlaps at least partially with the active portion T1P of the first dual-gate transistor T1. Specifically, the first electrode portion C11 located in the capacitor metal layer Mc can be selected to overlap at least partially with the active portion T1P of the first dual-gate transistor T1 at the intermediate node T1N to form the voltage regulating capacitor C1. When the first dual-gate transistor T1 is turned off, the active portion T1P of the first dual-gate transistor T1 is coupled to a high potential by its gate (including the first gate T11G of the first sub-transistor T11 and the second gate T12G of the second sub-transistor T12, provided by the high-potential first scan signal Scan1 via the first scan line G1). Consequently, the potential on the active portion T1P of the first dual-gate transistor T1 is pulled high. At this time, in this embodiment, the first electrode portion C11 is connected to the second scan line G2, which provides a low potential opposite to the first scan signal Scan1. The second scan signal Scan2 is coupled to the active part T1P (i.e., the second electrode C12) of the first dual-gate transistor T1 at the intermediate node T1N through the first electrode part C11. This can pull down the potential of the active part T1P of the first dual-gate transistor T1, so that the first dual-gate transistor T1 has little influence on the potential of the gate of the driving transistor DT when there is a low leakage current. This minimizes the potential change of the gate of the driving transistor DT and helps to improve the display flicker phenomenon of the panel.

[0087] Optional, such as Figure 3 , Figure 6 As shown, the display panel 000 may also include multiple reference voltage lines REF (to clearly illustrate the planar structure of the panel, Figure 5 Not shown in the text, please refer to the following: Figure 6 (For understanding), the reference voltage line REF is used for the reset transistor in pixel circuit 10, such as...Figure 34 When the fourth transistor T4 and the fifth transistor T5 are turned on, a reset signal is provided to the gate of the driving transistor DT and the anode of the light-emitting element 20, thus initializing the gate of the driving transistor DT and the light-emitting element 20. In this embodiment, the first electrode portion C11 of the voltage regulating capacitor C1 is disposed on the same layer as the reference voltage line REF. If the reference voltage line REF is made of a capacitor metal layer Mc, the first electrode portion C11 of the voltage regulating capacitor C1 is also made of a capacitor metal layer Mc. The first electrode portion C11 of the voltage regulating capacitor C1 is made using the film layer inherent in the display panel 000 itself, and forms an overlapping structure with at least part of the active portion T1P of the first dual-gate transistor T1, which serves as the second electrode portion C12. This not only lowers the potential of the intermediate node T1N by coupling the voltage regulating capacitor C1, but also helps to reduce the number of film layers in the panel, thus achieving a thinner panel design.

[0088] In some alternative embodiments, please continue to refer to the references. Figure 34 , Figure 34 In this embodiment, the first dual-gate transistor T1 includes a first gate T11G and a second gate T12G. Along the direction parallel to the plane where the substrate O1 is located, there is a first distance W1 between the first electrode portion C11 and the first gate T11G, and a second distance W2 between the first electrode portion C11 and the second gate T12G.

[0089] This embodiment explains that the first electrode portion C11 of the voltage regulation capacitor C1 used to couple and pull down the potential of the intermediate node T1N in the pixel circuit 10 can be configured to not overlap with the gate of the first dual-gate transistor T1 in the direction Z perpendicular to the plane of the substrate O1. Specifically, the first dual-gate transistor T1 includes a first sub-transistor T11 and a second sub-transistor T12. The first sub-transistor T11 includes a first gate T11G, and the second sub-transistor T12 includes a second gate T12G. The first gate T11G and the second gate T12G can both be disposed on the gate metal layer M1. Along the direction parallel to the plane of the substrate O1, there is a first distance W1 between the first electrode portion C11 and the first gate T11G, where W1 is greater than 0. The first electrode portion C11 and the first gate T11G are perpendicular to the plane of the substrate O1. There is no overlap in the direction Z of the plane where the substrate 01 is located. There is a second distance W2 between the first electrode part C11 and the second gate T12G, where W2 is greater than 0. There is no overlap between the first electrode part C11 and the second gate T12G in the direction Z perpendicular to the plane where the substrate 01 is located. The optional W1 and W2 can be different. Specifically, it can be designed according to the layout of the pixel circuit 10 on the display panel. This can avoid the second scan signal Scan2 provided by the second scan line G2 affecting the potential of the first gate T11G and the second gate T12G when the first electrode part C11 is connected to the second scan line G2. This helps to ensure the stability of the conduction state and cutoff state of the first dual gate transistor T1 when the first scan line G1 is connected to the first gate T11G and the second gate T12G, respectively.

[0090] In some alternative embodiments, please refer to the references. Figure 34 , Figure 5 , Figure 6 , Figure 35 , Figure 35 yes Figure 35 The circuit connection structure in this example is fabricated on the substrate of the display panel, representing another type of layout structure. Figure 5 yes Figure 6 A magnified view of a portion of region J2. Figure 36 yes Figure 37 A schematic diagram of the cross-sectional structure along the B-B' direction. Figure 36 yes Figure 37 The circuit connection structure in this example is fabricated on the substrate of the display panel, representing another type of layout structure. Figure 36 yes Figure 36 A magnified view of a portion of region J3. Figure 36 yes Figure 37 A schematic diagram of the cross-sectional structure along the C-C' direction. Figure 38 yes Figure 38 The circuit connection structure in this example is fabricated on the substrate of the display panel, representing another type of layout structure. Figure 38 yes ​ A magnified view of a portion of region J4.​ yes ​ A cross-sectional structural diagram along the D-D' direction (it should be understood that this diagram is for the purpose of clearly illustrating the structure of this embodiment). ​ and ​ , ​ and ​ , ​ and ​ (Transparency filling is performed in the middle). In this embodiment, the first dual-gate transistor T1 includes a first gate T11G and a second gate T12G. In the direction Z perpendicular to the plane where the substrate O1 is located, the first electrode portion C11 overlaps with a portion of the first gate T11G, and the first electrode portion C11 does not overlap with the second gate T12G (e.g., transparency filling is performed in the middle). ​ (as shown); or the first electrode portion C11 does not overlap with the first gate T11G, and the first electrode portion C11 overlaps with a portion of the second gate T12G (as shown). ​ (as shown); or the first electrode portion C11 overlaps with a portion of the first gate T11G, and the first electrode portion C11 also overlaps with a portion of the second gate T12G (as shown). ​ (As shown).

[0091] This embodiment explains that the first electrode portion C11 of the voltage regulation capacitor C1 used to couple and pull down the potential of the intermediate node T1N in the pixel circuit 10 can be configured to overlap with the gate of the first dual-gate transistor T1 in a small area along the direction Z perpendicular to the plane of the substrate O1. Specifically, the first dual-gate transistor T1 includes a first sub-transistor T11 and a second sub-transistor T12. The first sub-transistor T11 includes a first gate T11G, and the second sub-transistor T12 includes a second gate T12G. The first gate T11G and the second gate T12G can both be disposed on the gate metal layer M1 and can be disposed in the direction Z perpendicular to the plane of the substrate O1. The first electrode portion C11 only overlaps with a portion of the first gate T11G, and the first electrode portion C11 and the second gate T12G do not overlap. The overlap can be achieved by setting a small overlap between the first electrode portion C11 and the gate of the first dual-gate transistor T1, increasing the overlap area between the first electrode portion C11 and the second electrode portion C12 (i.e., the active portion T1P of the first dual-gate transistor T1). This can enhance the coupling pull-down effect of the voltage regulation capacitor C1, further reduce the impact of the leakage current of the first dual-gate transistor T1 on the gate potential of the driving transistor DT, avoid screen flicker, and ensure the display quality of the display panel 000.

[0092] Optional, such as ​ ,​ , ​ , ​ As shown, in order to minimize the overlap between the first electrode portion C11 and the gate of the first dual-gate transistor T1 to avoid affecting the gate potential of the first dual-gate transistor T1, the overlap area can be minimized in the direction Z perpendicular to the plane of the substrate O1. The first electrode portion C11 and a portion of the first gate T11G include a first overlap area F1, and the first electrode portion C11 and a portion of the second gate T12G include a second overlap area F2. Along the length extension direction of the second scan line G2 (the first direction X shown in the figure), the width of the first overlap area F1 is d1, and along the length extension direction of the data line S (the second direction Y shown in the figure), the width of the second overlap area F2 is d2. With d1≤1μm and d2≤1μm, the overlapping area between the first electrode portion C11 and the gate of the first dual-gate transistor T1 can be controlled within a range that will not affect the gate potential of the first dual-gate transistor T1. This avoids the situation where the width d1 of the first overlapping area F1 and the width d2 of the second overlapping area F2 are too small, thus preventing the increase of the overlapping area between the first electrode portion C11 and the second electrode portion C12. It also avoids the situation where the width d1 of the first overlapping area F1 and the width d2 of the second overlapping area F2 are too large, thus affecting the gate potential of the first dual-gate transistor T1. This is beneficial for enhancing the coupling pull-down effect of the voltage regulation capacitor C1 while ensuring the normal driving and display effect of the display panel 000.

[0093] In some alternative embodiments, please refer to the references. ​ , ​ , ​ , ​ , ​ yes ​ The circuit connection structure in this example is fabricated on the substrate of the display panel, representing another type of layout structure. ​ yes ​ A magnified view of a portion of region J5 (it should be understood that this is for the purpose of clearly illustrating the structure of this embodiment). ​ and ​ (Transparency filling was performed in the middle). In this embodiment, the first electrode part C11 includes at least a first sub-electrode part C11A and a second sub-electrode part C11B. The first sub-electrode part C11A and the second sub-electrode part C11B are disposed in different layers and are electrically connected.

[0094] In a direction perpendicular to the plane of substrate 01, the first sub-electrode portion C11A overlaps at least partially with the active portion T1P of the first dual-gate transistor T1, and the second sub-electrode portion C11B overlaps at least partially with the active portion T1P of the first dual-gate transistor T1.

[0095] It is understood that in this embodiment ​ and ​The pixel circuit 10 is still used in the middle. ​ The circuit connection structure shown is used as an example to illustrate the structure of the voltage regulating capacitor C1 on the substrate 01. In specific implementations, the pixel circuit 10 can also have other electrical connection structures. This embodiment is only an example.

[0096] This embodiment explains that the first electrode portion C11 of the voltage regulating capacitor C1 includes at least a first sub-electrode portion C11A and a second sub-electrode portion C11B. The first sub-electrode portion C11A and the second sub-electrode portion C11B are disposed in different layers and are electrically connected. That is, the first electrode portion C11 of the voltage regulating capacitor C1 includes two parts located in different metal film layers. These two parts can be directly electrically connected (not shown in the accompanying drawings), or both parts can be electrically connected to the second scan line G2 (e.g., ...). ​ As shown), to achieve electrical connection between the first sub-electrode C11A and the second sub-electrode C11B, both are fed a second scan signal Scan2, which is out of phase with the first scan signal Scan1, through the second scan line G2. The first sub-electrode C11A and the second sub-electrode C11B, connected to the same potential, together serve as the first electrode C11 of the voltage regulating capacitor C1. In the direction perpendicular to the plane of the substrate O1, not only does the first sub-electrode C11A overlap at least partially with the active portion T1P of the first dual-gate transistor T1, but the second sub-electrode C11B also overlaps at least partially with the active portion T1P of the first dual-gate transistor T1. Optionally, not only does the first sub-electrode C11A overlap at least partially with the channel connection portion T1PL of the first dual-gate transistor T1, but the second sub-electrode C11B also overlaps at least partially with the channel connection portion T1PL of the first dual-gate transistor T1. When the first sub-electrode C11A and the second sub-electrode C11B, which are connected to the same potential, are on different layers and do not overlap, it is equivalent to increasing the overall area of ​​the first electrode C11. This increases the overlapping area between the first electrode C11 and the second electrode C12, which is beneficial to further enhance the coupling pull-down effect of the voltage regulating capacitor C1. When the first sub-electrode C11A and the second sub-electrode C11B, which are connected to the same potential, are on different layers and at least partially overlap, it is equivalent to the first electrode C11 having a double-layer plate structure with the same potential. The capacitance of the double-layer plate has a better coupling effect than that of the single-layer plate, which can further enhance the coupling pull-down effect of the voltage regulating capacitor C1. This better pulls down the high coupling voltage of the intermediate node T1N of the first dual-gate transistor T1, which is beneficial to further ensure the stability of the gate potential of the driving transistor DT and improve the display quality.

[0097] Optionally, this embodiment does not limit whether the first sub-electrode C11A and the second sub-electrode C11B, which are connected to the same potential, overlap. In specific implementation, this can be set according to actual needs. ​ and​ The example given is that the first sub-electrode C11A and the second sub-electrode C11B do not overlap.

[0098] Optionally, in this embodiment, the first electrode portion C11 of the voltage regulating capacitor C1 includes at least a first sub-electrode portion C11A and a second sub-electrode portion C11B disposed in different layers, and the display panel 000 may include multiple reference voltage lines REF (to clearly illustrate the planar structure of the panel, ​ Not shown in the text, please refer to the following: ​ (For understanding) and multiple data lines S, the first sub-electrode C11A can be set in the same layer as the reference voltage line REF, and the second sub-electrode C11B can be set in the same layer as the data lines S. That is, the first sub-electrode C11A can be made using the capacitor metal layer Mc already present in the panel, and the second sub-electrode C11B can be made using the second metal layer M2 already present in the panel, which helps to reduce the film thickness. The electrical connection between the first sub-electrode C11A and the second sub-electrode C11B can be achieved through the first via K1. Since the distance between the capacitor metal layer Mc and the second metal layer M2 is small, the difficulty of opening the first via K1 can be reduced, and the stability of the electrical connection can be avoided if the first via K1 is too deep.

[0099] In some alternative embodiments, please refer to the references. ​ , ​ , ​ , ​ , ​ yes ​ The circuit connection structure in this example is fabricated on the substrate of the display panel, representing another type of layout structure. ​ yes ​ A magnified view of a portion of region J6. ​ yes ​ The circuit connection structure in this example is fabricated on the substrate of the display panel, representing another type of layout structure. ​ yes ​ A magnified view of a portion of region J7. ​ yes ​ The circuit connection structure in this example is fabricated on the substrate of the display panel, representing another type of layout structure. ​ yes ​ A partial enlarged view of region J8 in the middle (it should be understood that this is for the purpose of clearly illustrating the structure of this embodiment). ​(Transparency filling is performed in the middle). In this embodiment, the first dual-gate transistor T1 includes a first gate T11G and a second gate T12G. In the direction perpendicular to the plane where the substrate O1 is located, the second sub-electrode C11B overlaps with a portion of the first gate T11G; and / or, the second sub-electrode C11B overlaps with a portion of the second gate T12G. Optionally, at this time, the first sub-electrode C11A, which is connected to the same potential as the second sub-electrode C11B and is on a different layer from the second sub-electrode C11B, may overlap with at least a portion of the first gate T11G but not with the second gate T12G; or the first sub-electrode C11A may overlap with at least a portion of the second gate T12G but not with the first gate T11G; or the first sub-electrode C11A may overlap with at least a portion of the second gate T12G and also with at least a portion of the first gate T11G; or the first sub-electrode C11A may not overlap with the second gate T12G and not with at least a portion of the first gate T11G. This embodiment... ​ The examples provided all assume that the first sub-electrode portion C11A does not overlap with the second gate T12G, nor with at least a portion of the first gate T11G. For details regarding the overlap between the first sub-electrode portion C11A and the first gate T11G and the second gate T12G, please refer to [reference needed]. ​ The embodiments shown are for illustrative purposes only. The figures in this embodiment are only for specific illustration of the overlap between the second sub-electrode C11B and the first gate T11G and the second gate T12G.

[0100] It is understood that in this embodiment ​ The pixel circuit 10 is still used in the middle. ​ The circuit connection structure shown is used as an example to illustrate the structure of the voltage regulating capacitor C1 on the substrate 01. In specific implementations, the pixel circuit 10 can also have other electrical connection structures. This embodiment is only an example.

[0101] This embodiment explains that the first dual-gate transistor T1 includes a first gate T11G and a second gate T12G. In the direction perpendicular to the plane of the substrate O1, the second sub-electrode portion C11B overlaps with a portion of the first gate T11G, and the second sub-electrode portion C11B does not overlap with the second gate T12G (e.g., ...). ​ and ​ (as shown); or the second sub-electrode portion C11B does not overlap with the first gate T11G, and the second sub-electrode portion C11B overlaps with a portion of the second gate T12G (as shown). ​ and ​ (as shown); or the second sub-electrode portion C11B overlaps with a portion of the first gate T11G, and the second sub-electrode portion C11B also overlaps with a portion of the second gate T12G (as shown). ​ and ​(As shown). The first electrode portion C11 of the voltage regulation capacitor C1 used to couple and pull down the potential of the intermediate node T1N in the pixel circuit 10 may include a first sub-electrode portion C11A and a second sub-electrode portion C11B that are disposed on different layers and connected to the same potential. The second sub-electrode portion C11B may be configured to overlap with the gate of the first dual-gate transistor T1 in a small area in the direction Z perpendicular to the plane where the substrate O1 is located. Specifically, the first dual-gate transistor T1 includes a first sub-transistor T11 and a second sub-transistor T12. The first sub-transistor T11 includes a first gate T11G. The second sub-transistor T12 includes a second gate T12G. Both the first gate T11G and the second gate T12G can be disposed on the gate metal layer M1. The first sub-electrode C11A can be disposed on the capacitor metal layer Mc on the side of the gate metal layer M1 away from the substrate O1. The second sub-electrode C11B can be disposed on the second metal layer M2 on the side of the capacitor metal layer Mc away from the substrate O1, and can be disposed on a plane perpendicular to the plane of the substrate O1. The second sub-electrode C11B only overlaps with a portion of the first gate T11G. The second sub-electrode C11B and the second... The gate T12G does not overlap; or the second sub-electrode C11B does not overlap with the first gate T11G, and the second sub-electrode C11B only overlaps with a portion of the second gate T12G; or the second sub-electrode C11B overlaps with a portion of the first gate T11G, and the second sub-electrode C11B also overlaps with a portion of the second gate T12G. This can be achieved by setting a small overlap structure between the second sub-electrode C11B, which is connected to the potential of the second scan signal Scan2, and the gate of the first dual-gate transistor T1, thereby increasing the overlap area between the second sub-electrode C11B and the second gate T12G. The overlapping area of ​​C12 (i.e., the active part T1P of the first dual-gate transistor T1) is increased, which is equivalent to increasing the overlapping area of ​​the first electrode part C11 and the second electrode part C12 of the voltage regulating capacitor C1. This is beneficial to further enhance the coupling pull-down effect of the voltage regulating capacitor C1 through the cooperative structure of the first sub-electrode part C11A and the second sub-electrode part C11B of the first electrode part C11, reduce the influence of the leakage current of the first dual-gate transistor T1 on the gate potential of the driving transistor DT, better avoid screen flicker, and ensure the display quality of the display panel 000.

[0102] Understandably, the overlap area between the second sub-electrode C11B and the first gate T11G and the second gate T12G can be set as small as possible. That is, the second sub-electrode C11B and the first gate T11G only partially overlap, and the second sub-electrode C11B and the second gate T12G only partially overlap, without complete overlap. This avoids excessive overlap between the second sub-electrode C11B and the first gate T11G and the second gate T12G, which could affect the potential stability of the first gate T11G and the second gate T12G due to coupling.

[0103] Optional, such as ​ , ​ , ​ , ​ As shown, in order to minimize the overlap area between the second sub-electrode C11B and the gate of the first dual-gate transistor T1 to avoid affecting the gate potential of the first dual-gate transistor T1, the second sub-electrode C11B and a portion of the first gate T11G can be configured to include a third overlap region F3 in a direction perpendicular to the plane of the substrate O1, and a fourth overlap region F4 between the second sub-electrode C11B and a portion of the second gate T12G. Along the length extension direction of the second scan line G2 (the first direction X shown in the figure), the width of the third overlap region F3 is d3, and along the length extension direction of the data line S (the second direction Y shown in the figure), the width of the fourth overlap region F4 is d... 4. d3≤1μm, d4≤1μm, thereby controlling the overlapping area between the second sub-electrode C11B and the gate of the first dual-gate transistor T1 within a range that will not affect the gate potential of the first dual-gate transistor T1. This avoids the situation where the width d3 of the third overlapping area F3 and the width d4 of the fourth overlapping area F4 are too small, thus preventing the increase of the overlapping area between the second sub-electrode C11B and the second electrode C12. It also avoids the situation where the width d3 of the third overlapping area F3 and the width d4 of the fourth overlapping area F4 are too large, thus affecting the gate potential of the first dual-gate transistor T1. This is beneficial for enhancing the coupling pull-down effect of the voltage regulation capacitor C1 while ensuring the normal driving display effect of the display panel 000.

[0104] In some alternative embodiments, please refer to the references. ​ , ​ , ​ , ​ , ​ yes ​ The circuit connection structure in this example is fabricated on the substrate of the display panel, representing another type of layout structure. ​ yes ​ A magnified view of a portion of the J9 region. ​ yes ​ A cross-sectional structural diagram along the E-E' direction (it should be understood that this diagram is for the purpose of clearly illustrating the structure of this embodiment). ​ and ​ (Transparency filling is performed in the middle). In this embodiment, in the direction Z perpendicular to the plane where the substrate 01 is located, the second sub-electrode portion C11B and the first sub-electrode portion C11A at least partially overlap.

[0105] This embodiment explains that the first electrode portion C11 of the voltage regulating capacitor C1 includes at least a first sub-electrode portion C11A and a second sub-electrode portion C11B. The first sub-electrode portion C11A and the second sub-electrode portion C11B are disposed in different layers and are electrically connected. Both are connected to a second scan signal Scan2, which is out of phase with the first scan signal Scan1, through the second scan line G2. The first sub-electrode portion C11A and the second sub-electrode portion C11B, which are connected to the same potential, together serve as the first electrode portion C11 of the voltage regulating capacitor C1. In the direction perpendicular to the plane of the substrate O1, not only the first sub-electrode portion C11A and the second sub-electrode portion C11B are connected to the first scan signal Scan2, but also the first sub-electrode portion C11A and the second sub-electrode portion C11B are connected to the first scan signal Scan2. The channel connection portion T1PL of the dual-gate transistor T1 at least partially overlaps, and the second sub-electrode portion C11B at least partially overlaps with the channel connection portion T1PL of the first dual-gate transistor T1, and the second sub-electrode portion C11B at least partially overlaps with the first sub-electrode portion C11A. This is equivalent to the first electrode portion C11 having a double-layer plate structure with the same potential. The capacitance of the double-layer plate has a better coupling effect than that of the single-layer plate, which can further enhance the coupling pull-down effect of the voltage regulating capacitor C1, better pull down the coupling high voltage of the intermediate node T1N of the first dual-gate transistor T1, which is conducive to further ensuring the stability of the gate potential of the driving transistor DT and improving the display quality.

[0106] It is understood that this embodiment does not limit the size of the overlapping area between the second sub-electrode portion C11B and the first sub-electrode portion C11A. Without affecting the film layer layout, the larger the overlapping area between the second sub-electrode portion C11B and the first sub-electrode portion C11A, the better. For example, the second sub-electrode portion C11B can overlap with the first sub-electrode portion C11A in a larger area as possible, as long as the second sub-electrode portion C11B does not come into contact with other conductive structures of the second metal layer M2 (such as data line S, first power signal line 301, etc.) and cause a short circuit.

[0107] Optional, such as ​ , ​ , ​ and ​ As shown, in this embodiment, the first scan line G1 and the gate of the first dual-gate transistor T1 (including the first gate T11G and the second gate T12G) are disposed on the same layer, and the first scan line G1 and the first electrode portion C11 are disposed on different layers.

[0108] This embodiment explains that in the display panel 000, the first scan line G1, which controls the first dual-gate transistor T1 to be turned on or off, can be disposed on the same metal layer as the gate of the first dual-gate transistor T1. For example, the first scan line G1 and the gate of the first dual-gate transistor T1 can both be made of the gate metal layer M1. The first electrode portion C11 of the voltage regulating capacitor C1 can be disposed on a different layer from the first scan line G1. For example, it can be made of the capacitor metal layer Mc included in the panel itself. When the area of ​​the first electrode portion C11 is increased to enhance the coupling effect of the voltage regulating capacitor C1, the short circuit problem between the structure of the gate metal layer M1, such as the first scan line G1 and the gate of the first dual-gate transistor T1, can be avoided, which is conducive to ensuring the display effect of the display panel.

[0109] Optional, such as ​ , ​ , ​ and ​ As shown, the first electrode portion C11 and the second scan line G2 are an integral structure. It can be understood that when the first electrode portion C11 is a single-layer metal structure, the first electrode portion C11 and the second scan line G2 in the single-layer metal film are an integral structure. When the first electrode portion C11 is a double-layer metal structure, that is, when the first electrode portion C11 includes a first sub-electrode portion C11A and a second sub-electrode portion C11B of different layers, the first sub-electrode portion C11A and the second scan line G2 are an integral structure, and the second sub-electrode portion C11B and the second scan line G2 are disposed in different layers. That is, in this embodiment, when the second scan line G2 is used to connect the first electrode portion C11 to the second scan signal Scan2 which is opposite in phase to the first scan signal Scan1, the first electrode portion C11 and the second scan line G2 can both be made of a capacitor metal layer Mc. That is, the first electrode portion C11 and the second scan line G2 can be formed into an integral structure using the same process, which is beneficial to simplify the process and improve the process efficiency.

[0110] In some alternative embodiments, please continue to refer to the references. ​ and ​ In this embodiment, the pixel circuit 10 further includes a first reset module 105 and a data writing module 104. The first terminal of the first reset module 105 is electrically connected to the reference voltage line REF, the second terminal of the first reset module 105 is electrically connected to the control terminal 101C of the driving module 101, and the control terminal of the first reset module 105 is electrically connected to the third scan line G3.

[0111] The first end of the data writing module 104 is electrically connected to the first end 101A of the drive module 101, the second end of the data writing module 104 is electrically connected to the data line S, and the control end of the data writing module 104 is electrically connected to the first scan line G1.

[0112] This embodiment explains that the pixel circuit 10 in the display panel 000, in addition to including the driving module 101, compensation module 102, and voltage adjustment module 103, may also include a first reset module 105 and a data writing module 104; optionally, the pixel circuit 10 may also include a second reset module 106, a first light emission control module 107, a second light emission control module 108, and a storage module 109, or may include other modules such as a bias module (not shown in the figure), etc., which are not limited in this embodiment; wherein, the first terminal of the second reset module 106 can be electrically connected to the reference voltage line REF, the second terminal of the second reset module 106 is electrically connected to the anode of the light emission element 20, and the control terminal of the second reset module 106 can be connected to the third scan line G. 3. Electrical Connections: The first terminal of the first light-emitting control module 107 can be electrically connected to the first power signal line 301, the second terminal of the first light-emitting control module 107 can be electrically connected to the first terminal 101A of the driving module 101, the first terminal of the second light-emitting control module 108 can be electrically connected to the second terminal 101B of the driving module 101, and the second terminal of the second light-emitting control module 108 can be electrically connected to the anode of the light-emitting element 20, such as a light-emitting diode. The control terminals of the first light-emitting control module 107 and the second light-emitting control module 108 are both electrically connected to the light-emitting signal line EM. The first terminal of the storage module 109 is electrically connected to the control terminal 101C of the driving module 101, and the second terminal of the storage module 109 is electrically connected to the first power signal line 301. Further optional, in this embodiment... ​ The specific connection structure of the pixel circuit 10 is illustrated using the following examples: First reset module 105 includes a fourth transistor T4, which is also a dual-gate transistor; data writing module 104 includes a third transistor T3; second reset module 106 includes a fifth transistor T5; first light-emitting control module 107 includes a second transistor T2; second light-emitting control module 108 includes a sixth transistor T6; driving module 101 includes a driving transistor DT; compensation module 101 includes a first dual-gate transistor T1; voltage adjustment module 103 includes a voltage adjustment capacitor C1; and storage module 109 includes a storage capacitor C2. The storage capacitor C2 is used to stabilize the gate potential of the driving transistor DT, which helps keep the driving transistor DT conducting.

[0113] This embodiment ​ The diagram illustrates the circuit connection structure that the pixel circuit 10 in the display panel 000 may include. The pixel circuit 10 includes multiple transistors, a voltage regulation capacitor C1, and a storage capacitor C2. One transistor is a driving transistor DT, and the remaining transistors are switching transistors. This embodiment... ​Taking the schematic diagram of the pixel circuit 10 and the light-emitting element 20 electrically connected as an example, the gate of the driving transistor DT represents the first node N1, the source of the driving transistor DT represents the second node N2, the drain of the driving transistor DT represents the third node N3, and the anode of the light-emitting element 20 is the fourth node N4. The working principle of the pixel circuit 10 is as follows:

[0114] During the initial reset phase, the third scan line G3 transmits a low potential, while the first scan line G1 and the light-emitting signal line EM both transmit a high potential. The fourth transistor T4 and the fifth transistor T5 are turned on, and the remaining transistors are turned off. The potentials of the first node N1 and the fourth node N4 are the reset signals provided by the reference voltage line REF, driving the gate of transistor DT and the anode of the light-emitting element 20 to reset. Optionally, the reference voltage lines connected to the fourth transistor T4 and the fifth transistor T5 can be different; that is, the reset signal used to initialize the gate of the driving transistor DT and the reset signal used to initialize the anode of the light-emitting element 20 can be different. This embodiment does not impose limitations on this. At this time, the second scan line G2 has a low potential that is opposite in phase to the first scan line G1.

[0115] During the data writing and threshold compensation phase, both the third scan line G3 and the light-emitting signal line EM transmit a high potential, while the first scan line G1 transmits a low potential. The third transistor T3, the driving transistor DT, and the first dual-gate transistor T1 are turned on, while the remaining transistors are turned off. The data voltage signal provided by the data line S is sequentially written to the gate of the driving transistor DT through the third transistor T3, the driving transistor DT, and the first dual-gate transistor T1. At this time, the second scan line G2 has a high potential that is opposite in phase to that of the first scan line G1.

[0116] During the light-emitting phase, all light-emitting signal lines EM transmit a low potential, while the third scan line G3 and the first scan line G1 transmit a high potential. The second transistor T2, the sixth transistor T6, and the driving transistor DT are turned on, while the remaining transistors are turned off. A conductive path is formed between the second power signal line 301 and the second power signal line 302 by the second transistor T2, the sixth transistor T6, and the driving transistor DT. The driving transistor DT generates a driving current, driving the light-emitting element 20 to emit light. At this time, the second scan line G2 has a low potential that is opposite in phase to the first scan line G1.

[0117] During the subsequent light-emitting holding stage, the first scan line G1 transmits a high potential, the first dual-gate transistor T1 is turned off, and the second scan line G2 inputs a low potential that is opposite in phase to the first scan line G1. The second scan signal Scan2 on the low-potential second scan line G2 is coupled to the second electrode C12 through the first electrode C11 of the voltage regulating capacitor C1, thereby pulling down the original high potential signal at the intermediate node T1N of the first dual-gate transistor T1. This is equivalent to keeping the intermediate node T1N of the first dual-gate transistor T1 at a lower potential, eliminating the coupling high voltage originally generated by the transistor coupling effect. As a result, the voltage at the intermediate node T1N of the first dual-gate transistor T1 does not jump as much as possible with the change of the conduction state of the first dual-gate transistor T1, reducing the degree of voltage change at the intermediate node T1N of the first dual-gate transistor T1. This allows the light-emitting element 20 to maintain stable brightness, improves the overall display brightness stability of the display panel 000, and helps to improve display quality.

[0118] In some alternative embodiments, please refer to the references. ​ , ​ , ​ , ​ and ​ , ​ yes ​ The circuit connection structure in the display panel is fabricated on the substrate of the display panel as a layout structure of three sub-pixels. ​ yes ​ A partial enlarged view of region J10 (it should be understood that this is for the purpose of clearly illustrating the structure of this embodiment). ​ and ​ (Transparency filling was performed in the middle). In this embodiment, at least a portion of the first electrode portion C11 is located between the first active connection portion PL1 and the second active connection portion PL2 along a direction parallel to the plane where the substrate 01 is located.

[0119] The first active connection part PL1 and the second active connection part PL2 are both located in the active layer 02. The first active connection part PL1 is an active layer 02 in a part of the area between the second end of the first reset module 105 and the control end 101C of the drive module 101. The second active connection part PL2 is an active layer 02 in a part of the area between the second end of the data writing module 104 and the data line S.

[0120] This embodiment explains that when fabricating a voltage-regulating capacitor C1 on substrate 01, in a direction parallel to the plane of substrate 01, along the length extension direction of the second scan line G2, i.e., along the first direction X shown in the figure, at least a portion of the first electrode portion C11 used to form the voltage-regulating capacitor C1 can be disposed between the first active connection portion PL1 and the second active connection portion PL2. Specifically, the first active connection portion PL1 can be understood as a portion of the active layer 02 electrically connected between the second terminal of the first reset module 105 and the control terminal 101C of the drive module 101. The active layer 02 is a portion of the area between the second terminal T4D of the fourth transistor T4 and the gate of the driving transistor DT. The second terminal T4D of the fourth transistor T4 can be understood as the terminal connected to the gate of the driving transistor DT. The second active connection PL2 is a portion of the active layer 02 electrically connected between the second terminal of the data writing module 104 and the data line S. That is, the second active connection PL2 can be understood as a portion of the active layer 02 electrically connected between the first terminal T3S of the third transistor T3 and the data line S. The first terminal T3S of the third transistor T3 can be understood as the terminal connected to the data line S. It can be understood that the film layers containing the first active connection PL1 and the second active connection PL2 are... ​ The active layer 02 in the layout structure shown can be used to fabricate the channel portion of the transistor, the first and second terminals of the transistor at both ends of the channel portion, and active connection portions that serve as connections (such as the first active connection portion PL1 and the second active connection portion PL2 shown in this embodiment). In the first and second terminals of the transistor, the first terminal is the source and the second terminal is the drain, or the first terminal is the drain and the second terminal is the source. This embodiment does not limit this. The first and second electrodes of the transistor are doped active structures that can directly transmit current. The channel is an active structure that overlaps with the gate of the transistor. The conduction or cutoff of the channel can be controlled by the voltage signal applied to the gate of the transistor, thereby realizing the conduction or cutoff of the transistor. In this embodiment, the control of the conduction and cutoff of the transistor will not be described in detail. It is only necessary to understand that the first active connection part PL1 is a part of the active layer O2 that is electrically connected between the second electrode T4D of the fourth transistor T4 and the gate of the driving transistor DT, and the second active connection part PL2 is a part of the active layer O2 that is electrically connected between the first electrode T3S of the third transistor T3 and the data line S.

[0121] In existing technologies, as the resolution of display panels continues to increase, the gaps between the metal film layers used to form signal lines and transistors within the display panel are becoming smaller and smaller. This leads to a greater coupling effect between the metal film layers, forming larger parasitic capacitances. These parasitic capacitances further cause unwanted electric fields during panel display, affecting the display effect. The parasitic capacitance formed between the gate of the driving transistor and the data line has a significant impact on the display. Once a large parasitic capacitance forms between the gate of the driving transistor and the data line, the driving current transmitted to the light-emitting element is affected, causing a significant difference between the actual luminous brightness of the light-emitting element and the required standard luminous brightness. This results in crosstalk in the display panel, degrading the display quality. The larger the parasitic capacitance between the gate of the driving transistor and the data line, the greater the difference between the actual driving current and the standard driving current, and the greater the deviation between the actual luminous brightness of the light-emitting element and the standard luminous brightness, making the crosstalk phenomenon more pronounced.

[0122] In this embodiment, at least a portion of the first electrode portion C11 is located between the first active connection portion PL1 and the second active connection portion PL2, along a direction parallel to the plane where the substrate 01 is located (the first direction X shown in the figure). When a coupling effect occurs between the first active connection portion PL1 and the second active connection portion PL2, generating a coupled electric field, since at least a portion of the first electrode portion C11 is located between the first active connection portion PL1 and the second active connection portion PL2, and the first scan signal Scan1 is at a low potential on the first scan line G1 during the data writing and threshold compensation stage, then at this time, the high... The second scan signal Scan2 of the potential is transmitted to the first electrode C11, which is equivalent to at least part of the first electrode C11 located between the first active connection PL1 and the second active connection PL2 receiving a fixed voltage signal with a high potential during the light-emitting holding stage. Therefore, the at least part of the first electrode C11 located between the first active connection PL1 and the second active connection PL2 can at least partially block the electric field lines formed between the first active connection PL1 and the second active connection PL2, reduce the coupling electric field between the two, and thereby reduce the parasitic capacitance between them. Furthermore, since the first active connection part PL1 is electrically connected to the gate of the driving transistor DT, and the second active connection part PL2 is electrically connected to the data line S, the parasitic capacitance between the first active connection part PL1 and the second active connection part PL2 can be reduced during data writing. This is equivalent to reducing the parasitic capacitance between the gate of the driving transistor DT and the data line S, thereby reducing the impact of coupling at this location on the driving current flowing into the light-emitting element 20, narrowing the gap between the actual luminous brightness and the standard luminous brightness of the light-emitting element 20, making it closer to its standard luminous brightness, which in turn helps to improve the crosstalk phenomenon caused by coupling and further improves the display quality.

[0123] It is understandable that when the first electrode portion C11 and the second scan line G2 are an integral structure in this embodiment, during the manufacturing process, if... ​ and ​ As shown, a section of the first electrode portion C11 can be directly pulled down at the position of the second scan line G2 between the first active connection portion PL1 and the second active connection portion PL2. This portion of the first electrode portion C11 serves to at least partially isolate the electric field lines formed between the first active connection portion PL1 and the second active connection portion PL2. Then, based on this portion of the first electrode portion C11, it bends and extends to the position of the channel connection portion T1PL of the first dual-gate transistor T1, so that the remaining portion of the first electrode portion C11 overlaps with the channel connection portion T1PL to form a first capacitor C1, so as to couple and pull down the potential of the intermediate node T1N of the first dual-gate transistor T1, thereby improving the flickering phenomenon of the display panel.

[0124] It is understandable that, such as ​ , ​ , ​ , ​ and ​ , ​ yes ​ When the circuit connection structure is fabricated on the substrate of the display panel, it represents another layout structure for the three sub-pixels. ​ yes ​ A partial enlarged view of region J11 (it should be understood that this is for the purpose of clearly illustrating the structure of this embodiment). ​ and ​ (Transparency filling is applied). In this embodiment, when the first electrode portion C11 includes at least a first sub-electrode portion C11A and a second sub-electrode portion C11B that are disposed in different layers and both connected to the second scan signal Scan2, the first sub-electrode portion C11A at least partially overlaps with the channel connection portion T1PL (i.e., the second electrode portion C12) of the first dual-gate transistor T1, and the second sub-electrode portion C11B at least partially overlaps with the channel connection portion T1PL (i.e., the second electrode portion C12) of the first dual-gate transistor T1. The first sub-electrode portion C11A and the second sub-electrode portion C11B together... When forming the first electrode portion C11 of the voltage regulating capacitor C1, at least a portion of the first electrode portion C11 can be located between the first active connection portion PL1 and the second active connection portion PL2 in a direction parallel to the plane of the substrate 01. This serves to at least partially isolate the electric field lines formed between the first active connection portion PL1 and the second active connection portion PL2, thereby reducing the coupling electric field between them. This can also reduce the parasitic capacitance between them, reduce the parasitic capacitance of the gate of the driving transistor DT and the data line S, improve the crosstalk phenomenon caused by coupling, and improve the display quality.

[0125] It is understood that this embodiment uses a P-type transistor in the pixel circuit 10 as an example for illustration. In specific implementation, the type of transistor in the pixel circuit 10 includes but is not limited to this, and this embodiment does not limit it.

[0126] Optional, such as ​ and ​ As shown, the driving module 101 in this embodiment includes a driving transistor DT. Both the first dual-gate transistor T1 and the driving transistor DT are low-temperature polysilicon transistors (LTPS). Optionally, other transistors in the pixel circuit 10 can also be LPS, and the active layer 02 can all be made of LPS semiconductors. This reduces the fabrication steps of the active layer 02 and lowers the complexity of the display panel's film structure, simplifying the manufacturing process of the pixel circuit 10, reducing manufacturing difficulty, and improving process efficiency. Optionally, the transistors included in the pixel circuit 10 can all be P-type transistors, such as P-type LPS transistors. The high mobility and high driving speed of LPS transistors can be utilized to ensure a fast response speed of the driving transistor DT when the data writing module 104 writes data signals, allowing the data signals to be written quickly and avoiding insufficient charging due to the long on-time of the driving transistor DT.

[0127] In some alternative embodiments, please refer to the references. ​ , ​ , ​ , ​ This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention (it should be understood that this diagram is for the purpose of clearly illustrating the structure of this embodiment). ​ (Transparency filling was performed in the middle). In this embodiment, an inverter 40 is connected between the first scan line G1 and the second scan line G2.

[0128] This embodiment explains that the second terminal 103B of the voltage adjustment module 103 is electrically connected to the second scan line G2. To ensure that the second scan signal Scan2 provided by the second scan line G2 is out of phase with the first scan signal Scan1 provided by the first scan line G1, an inverter 40 can be connected between the first scan line G1 and the second scan line G2. Optionally, the inverter 40 can be located in the non-display area NA of the display panel 000 (e.g., ...). ​(As shown in the left border position), the inverter 40 can be set to avoid affecting the display quality of the display area AA. When the first scan signal Scan1 provided by the first scan line G1 is a high potential that controls the first dual-gate transistor T1 to be cut off, the first scan signal Scan1 provided by the first scan line G1, after passing through the inverter 40, can be output to the second scan line G2 as a low-potential second scan signal Scan2. The low-potential second scan signal Scan2 can pull down the original high-potential signal at the middle node T1N of the first dual-gate transistor T1, eliminating the coupling high voltage originally generated by the transistor coupling effect, so that the voltage of the control terminal 101C of the driving module 101 can tend to be stable, improving the overall display brightness stability of the display panel 000. This is beneficial to improving the display quality, and at the same time, it is not necessary to set a separate signal terminal for the second scan line G2 to provide the second scan signal Scan2 in the display panel 000. It is only necessary to set it as the signal terminal for the first scan signal Scan1 provided by the first scan line G1. The first scan signal Scan1 can be converted into the second scan signal Scan2 through the inverter 40, which is beneficial to simplifying the panel structure.

[0129] Optional, such as ​ , ​ , ​ As shown, ​ This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention (it should be understood that this diagram is for the purpose of clearly illustrating the structure of this embodiment). ​ (Transparency fill is applied). In this embodiment, an inverter 40 is connected between the first scan line G1 and the second scan line G2. The non-display area NA of the display panel 000 includes a scan driving circuit 50, which includes a first scan signal output terminal 501. The first scan signal output terminal 501 is connected to the input terminal G1 of the first scan line G1. in Connect the first scan signal output terminal 501 to the input terminal 40 of the inverter 40. in Connect the output terminal 40 of inverter 40. out The input terminal G2 of the second scan line G2 in connect.

[0130] This embodiment explains that the non-display area NA of the display panel 000 includes a scan driving circuit 50. The scan driving circuit 50 includes a first scan signal output terminal 501. The scan driving circuit 50 is used to generate at least a first scan signal Scan1. Optionally, the scan driving circuit 50 may include multiple cascaded shift register units. The shift register unit includes a circuit structure for generating the scan driving signal. The first scan signal output terminal 501 of the scan driving circuit 50 is connected to the input terminal G1 of the first scan line G1. inThe connection provides a first scan signal Scan1 to the first scan line G1 in the display panel 000. When an inverter 40 is connected between the first scan line G1 and the second scan line G2, the specific connection structure of the inverter 40 in the display panel 000 can be such that the first scan signal output terminal 501 is also connected to the input terminal 40 of the inverter 40. in Connect the output terminal 40 of inverter 40. out The input terminal G2 of the second scan line G2 in The connection is made so that the first scan signal Scan1 output from the first scan signal output terminal 501 of the scan drive circuit 50 is inverted through the inverter 40, that is, the first scan signal Scan1 output from the first scan signal output terminal 501 of the inverter 40 is inverted. out The generated signal is the second scan signal Scan2, which is provided to the second scan line G2 in the display panel 000. This makes the second scan signal Scan2 on the second scan line G2 and the first scan signal Scan1 on the first scan line G1 out of phase. This achieves the voltage regulation capacitor C1 to pull down the potential of the intermediate node T1N of the first dual-gate transistor T1, while also reducing the number of signal output terminals included in the scan drive circuit 50. Only the first scan signal output terminal 501 needs to be set, and there is no need to set another signal output terminal to connect to the second scan line G2. This helps to reduce the space occupied by the scan drive circuit 50 in the non-display area NA, which helps to reduce the bezel width of the display panel 000 and reduce the wiring difficulty of the scan drive circuit 50 in the non-display area NA.

[0131] It is understood that the diagram in this embodiment is only a block diagram illustrating the scan driving circuit 50. In specific implementation, the circuit structure of the scan driving circuit 50 can be understood by referring to the structure of the scan driving circuit included in the display panel in related technologies. This embodiment will not elaborate on it here.

[0132] In some alternative embodiments, please refer to the references. ​ , ​ , ​ and ​ , ​ This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention. ​ yes ​ A schematic diagram of the connection structure between the intermediate scan drive circuit and the first and second scan lines (it should be understood that this is for the purpose of clearly illustrating the structure of this embodiment). ​ (Transparency filling is applied). In this embodiment, an inverter 40 is connected between the first scan line G1 and the second scan line G2, and a first switch control transistor CT1 is connected between the first scan line G1 and the second scan line G2. The gate of the first switch control transistor CT1 is connected to the first scan line G1, and the first terminal of the first switch control transistor CT1 is connected to the output terminal 40 of the inverter 40. outThe connection is made between the second terminal of the first switch control transistor CT1 and the input terminal G2 of the second scan line G2. in connect;

[0133] When the first dual-gate transistor T1 is turned on, the first switch control transistor CT1 controls the second scan line G2 to not be connected to the second scan signal Scan2; when the first dual-gate transistor T1 is turned off, the first switch control transistor CT1 controls the second scan line G2 to be connected to the second scan signal Scan2.

[0134] Optionally, in this embodiment, when the first dual-gate transistor T1 is turned on, the first switch control transistor CT1 controls the second scan line G2 to not be connected to the second scan signal Scan2, i.e., the first switch control transistor CT1 is turned off; when the first dual-gate transistor T1 is turned off, the first switch control transistor CT1 controls the second scan line G2 to be connected to the second scan signal Scan2, i.e., the first switch control transistor CT1 is turned on. Therefore, the gate of the first switch control transistor CT1 is connected to the first scan line G1, and the first scan signal Scan1 on the first scan line G1 controls whether the first switch control transistor CT1 is turned on or off. When the first dual-gate transistor T1 is set to be a P-type transistor, the first switch control transistor CT1 is an N-type transistor (e.g., ...). ​ and ​ As shown in the diagram, when the first scan signal Scan1 provided by the first scan line G1 is at a low potential and the first dual-gate transistor T1 is turned on, the low-potential first scan signal Scan1 can control the N-type first switch control transistor CT1 to turn off; when the first scan signal Scan1 provided by the first scan line G1 is at a high potential and the first dual-gate transistor T1 is turned off, the high-potential first scan signal Scan1 can control the N-type first switch control transistor CT1 to turn on. Alternatively, when the first dual-gate transistor T1 is set to be an N-type transistor, the first switch control transistor CT1 is a P-type transistor. When the first scan signal Scan1 provided by the first scan line G1 is at a high potential and the first dual-gate transistor T1 is turned on, the high-potential first scan signal Scan1 can control the P-type first switch control transistor CT1 to turn off; when the first scan signal Scan1 provided by the first scan line G1 is at a low potential and the first dual-gate transistor T1 is turned off, the low-potential first scan signal Scan1 can control the P-type first switch control transistor CT1 to turn on (not shown in the diagram).

[0135] This embodiment explains how the first scan signal Scan1 output from the first scan signal output terminal 501 of the scan drive circuit 50 is inverted by the inverter 40 in the display panel 000, so that the signal output from the first scan signal output terminal 501 of the inverter 40 is inverted. outThe generated signal is the second scan signal Scan2, which is provided to the second scan line G2 in the display panel 000. To ensure that the second scan signal Scan2 on the second scan line G2 is out of phase with the first scan signal Scan1 on the first scan line G1, a first switch control transistor CT1 can be connected between the first scan line G1 and the second scan line G2. Specifically, the gate of the first switch control transistor CT1 is connected to the first scan line G1, and the first terminal of the first switch control transistor CT1 is connected to the output terminal 40 of the inverter 40. out The connection is made between the second terminal of the first switch control transistor CT1 and the input terminal G2 of the second scan line G2. in Connection; When the first dual-gate transistor T1 is turned on, the first switch control transistor CT1 can control the second scan line G2 to not be connected to the second scan signal Scan2. This allows the first switch control transistor CT1 to be in a cut-off state when the data voltage signal writing drive module 101 is operating during the data writing phase of the first dual-gate transistor T1 being turned on. At this time, even if the first scan signal Scan1 passes through the inverter 40 and exits from the output terminal 40 of the inverter 40... out The output of the second scan signal Scan2, which is out of phase with the first scan signal Scan1, will not be transmitted to the input terminal G2 of the second scan line G2. in In other words, by controlling the first switch to turn off the transistor CT1, the second scan line G2 can be prevented from being connected to the second scan signal Scan2 during the data writing phase. This avoids the low-potential second scan signal Scan2 affecting the performance of the first dual-gate transistor T1 during the data writing phase through the voltage regulating capacitor C1, thus ensuring display quality. When the first dual-gate transistor T1 is turned off, the first switch to turn on the transistor CT1 controls the second scan line G2 to be connected to the second scan signal Scan2. That is, when the display panel 000 is emitting light, the first switch to turn on the transistor CT1 can be controlled to turn on the second scan line G2 to be connected to the second scan signal Scan2. In other words, the first scan signal Scan1 passes through the inverter 40 and exits from the output terminal 40 of the inverter 40. out A second scan signal, Scan2, which is out of phase with the first scan signal Scan1, is output and transmitted to the input terminal G2 of the second scan line G2. in The second scan signal Scan2, which is at a low potential at this time, is transmitted to the voltage regulation capacitor C1, which pulls down the coupling high potential of the intermediate node T1N of the first dual-gate transistor T1, so as to avoid the potential of the control terminal 101C of the drive module 101 affected by the leakage current of the transistor, thereby improving the flickering phenomenon of the panel.

[0136] In some alternative embodiments, please refer to ​ , ​This is a schematic diagram of the planar structure of a display device provided in an embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. ​ This embodiment uses a mobile phone as an example to illustrate the display device 111. It is understood that the display device 111 provided in this embodiment can be any other display device 111 with display functions, such as a computer, television, or in-vehicle display device; this invention does not impose specific limitations on this. The display device 111 provided in this embodiment has the beneficial effects of the display panel 000 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 000 in the above embodiments; these will not be repeated here.

[0137] As can be seen from the above embodiments, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0138] In the display panel provided by this invention, each sub-pixel includes an electrically connected pixel circuit and a light-emitting element. When the pixel circuit drives the electrically connected light-emitting element to emit light, the driving module generates a driving current to drive the light-emitting element to emit light through the conductive path between the first power signal line, the driving module, the light-emitting element, and the second power signal line, thereby achieving the light-emitting effect of the light-emitting element. The pixel circuit's compensation module is used to detect and compensate for the deviation of the threshold voltage of the driving transistor in the driving module when the pixel circuit operates to the data writing and threshold compensation stage. It then provides the compensated threshold voltage deviation and the data voltage signal provided by the data line itself to the driving module to achieve threshold compensation for the driving module. The compensation module includes a first dual-gate transistor. Since the leakage current of the dual-gate transistor is much smaller than that of the single-gate transistor, it can improve the leakage characteristics of the switching transistor in the compensation module. When the pixel circuit drives the light-emitting element to emit light, it can stabilize the potential of the control terminal of the driving module to a certain extent. The present invention further includes a pixel circuit comprising a voltage adjustment module. The two ends of the voltage adjustment module are electrically connected to the middle node of the first dual-gate transistor and the second scan line, respectively. The second scan line provides a second scan signal. Taking a P-type transistor as an example, after the first dual-gate transistor changes from an on state to an off state (i.e., the gate voltage of the first dual-gate transistor jumps from a low potential to a high potential), due to the coupling effect of the first dual-gate transistor itself, the voltage at the middle node of the first dual-gate transistor will be coupled to a high potential. However, since the second end of the voltage adjustment module is electrically connected to the second scan line, the second scan signal is out of phase with the gate signal of the first dual-gate transistor. That is, when the first scan signal is a high potential controlling the first dual-gate transistor to turn off, the second scan signal is a low potential. The low-potential second scan signal can then be used to... The high-potential signal coupled at the middle node of the dual-gate transistor is pulled down, which is equivalent to keeping the middle node of the first dual-gate transistor at a lower potential. This eliminates the high voltage coupling originally caused by the transistor coupling effect, thus making the voltage at the middle node of the first dual-gate transistor as stable as possible with the change of the conduction state of the first dual-gate transistor. This reduces the degree of voltage change at the middle node of the first dual-gate transistor. Even if the leakage current characteristic of a certain sub-crystal in the first dual-gate transistor still exists unavoidably, the potential at the middle node is transmitted to the control terminal of the driving module, which will not affect the stability of the control terminal of the driving module. Therefore, the voltage at the control terminal of the driving module can tend to be stable, which can keep the brightness of the light-emitting element stable, improve the overall display brightness stability of the display panel, and help improve the display quality.

[0139] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, include: Multiple sub-pixels, each sub-pixel comprising an electrically connected pixel circuit and a light-emitting element; The pixel circuit includes at least a driving module and a compensation module. The first end of the driving module is electrically connected to a first power signal line, the second end of the driving module is electrically connected to the anode of the light-emitting element, and the cathode of the light-emitting element is electrically connected to a second power signal line. The compensation module includes a first dual-gate transistor, the first terminal of which is electrically connected to the control terminal of the driving module, and the second terminal of which is electrically connected to the second terminal of the driving module; the gate of the first dual-gate transistor is connected to a first scan line, and the first scan line provides a first scan signal. The pixel circuit further includes a voltage adjustment module, the first dual-gate transistor includes an intermediate node; a first terminal of the voltage adjustment module is electrically connected to the intermediate node, and a second terminal of the voltage adjustment module is electrically connected to a second scan line, the second scan line providing a second scan signal; The second scan signal is out of phase with the first scan signal; During the initial reset phase, the first scan line transmits a high-potential scan signal, and the second scan line transmits a low-potential scan signal. During the data writing and threshold compensation phases, the first scan line transmits a low-potential scan signal, and the second scan line transmits a high-potential scan signal. During the light emission phase, the first scan line transmits a high-potential scan signal, and the second scan line transmits a low-potential scan signal.

2. The display panel according to claim 1, characterized in that, The first dual-gate transistor includes a first sub-transistor and a second sub-transistor connected to each other. The first terminal of the first sub-transistor is electrically connected to the control terminal of the driving module, the second terminal of the first sub-transistor is electrically connected to the first terminal of the second sub-transistor, and the second terminal of the second sub-transistor is electrically connected to the second terminal of the driving module. The gates of the first sub-transistor and the second sub-transistor are both connected to the first scan line. The intermediate node is located at the connection between the second terminal of the first sub-transistor and the first terminal of the second sub-transistor.

3. The display panel according to claim 1, characterized in that, The voltage regulation module includes a voltage regulation capacitor; the voltage regulation capacitor includes a first electrode portion and a second electrode portion, the first electrode portion being electrically connected to the second scan line, and the second electrode portion being electrically connected to the intermediate node.

4. The display panel according to claim 3, characterized in that, The display panel includes at least a substrate and an active layer located on one side of the substrate, the active layer including the active portion of the first dual-gate transistor; In a direction perpendicular to the plane of the substrate, the first electrode portion at least partially overlaps with the active portion of the first dual-gate transistor, and at least a portion of the active portion of the first dual-gate transistor is multiplexed as the second electrode portion.

5. The display panel according to claim 4, characterized in that, The active portion of the first dual-gate transistor includes at least a first sub-channel portion, a second sub-channel portion, and a channel connection portion, wherein the first sub-channel portion and the second sub-channel portion are connected through the channel connection portion; the channel connection portion includes the intermediate node; In a direction perpendicular to the plane of the substrate, the first electrode portion and the channel connection portion at least partially overlap, and the channel connection portion is reused as the second electrode portion.

6. The display panel according to claim 4, characterized in that, The first dual-gate transistor includes a first gate and a second gate. Along a direction parallel to the plane where the substrate is located, the first electrode portion and the first gate have a first distance, and the first electrode portion and the second gate have a second distance.

7. The display panel according to claim 4, characterized in that, The first dual-gate transistor includes a first gate and a second gate, wherein in a direction perpendicular to the plane of the substrate, the first electrode portion overlaps with a portion of the first gate; and / or, the first electrode portion overlaps with a portion of the second gate.

8. The display panel according to claim 4, characterized in that, The first electrode portion includes at least a first sub-electrode portion and a second sub-electrode portion, the first sub-electrode portion and the second sub-electrode portion are disposed in different layers, and the first sub-electrode portion and the second sub-electrode portion are electrically connected; In a direction perpendicular to the plane of the substrate, the first sub-electrode portion at least partially overlaps with the active portion of the first dual-gate transistor, and the second sub-electrode portion at least partially overlaps with the active portion of the first dual-gate transistor.

9. The display panel according to claim 8, characterized in that, The first dual-gate transistor includes a first gate and a second gate, wherein in a direction perpendicular to the plane of the substrate, the second sub-electrode portion overlaps with a portion of the first gate; and / or, the second sub-electrode portion overlaps with a portion of the second gate.

10. The display panel according to claim 8, characterized in that, In a direction perpendicular to the plane of the substrate, the second sub-electrode portion at least partially overlaps with the first sub-electrode portion.

11. The display panel according to claim 4, characterized in that, The first scan line is disposed on the same layer as the gate of the first dual-gate transistor, and the first scan line is disposed on a different layer from the first electrode portion.

12. The display panel according to claim 4, characterized in that, The pixel circuit further includes a first reset module and a data writing module. The first terminal of the first reset module is electrically connected to the reference voltage line, the second terminal of the first reset module is electrically connected to the control terminal of the driving module, and the control terminal of the first reset module is electrically connected to the third scan line. The first end of the data writing module is electrically connected to the first end of the driving module, the second end of the data writing module is electrically connected to the data line, and the control end of the data writing module is electrically connected to the first scan line.

13. The display panel according to claim 12, characterized in that, Along a direction parallel to the plane where the substrate is located, at least a portion of the first electrode portion is located between the first active connection portion and the second active connection portion; Wherein, both the first active connection portion and the second active connection portion are located in the active layer; the first active connection portion is a portion of the active layer electrically connected between the second end of the first reset module and the control end of the drive module, and the second active connection portion is a portion of the active layer electrically connected between the second end of the data writing module and the data line.

14. The display panel according to claim 4, characterized in that, The first electrode portion and the second scan line are an integral structure.

15. The display panel according to claim 1, characterized in that, An inverter is connected between the first scan line and the second scan line.

16. The display panel according to claim 15, characterized in that, The display panel includes a scan driving circuit, which includes a first scan signal output terminal connected to the input terminal of the first scan line, the first scan signal output terminal connected to the input terminal of the inverter, and the output terminal of the inverter connected to the input terminal of the second scan line.

17. The display panel according to claim 16, characterized in that, A first switch control transistor is connected between the first scan line and the second scan line. The gate of the first switch control transistor is connected to the first scan line. The first terminal of the first switch control transistor is connected to the output terminal of the inverter. The second terminal of the first switch control transistor is connected to the input terminal of the second scan line. When the first dual-gate transistor is turned on, the first switch control transistor controls the second scan line to not be connected to the second scan signal; when the first dual-gate transistor is turned off, the first switch control transistor controls the second scan line to be connected to the second scan signal.

18. The display panel according to claim 17, characterized in that, The first dual-gate transistor is a P-type transistor, and the first switch control transistor is an N-type transistor; or... The first dual-gate transistor is an N-type transistor, and the first switch control transistor is a P-type transistor.

19. The display panel according to claim 1, characterized in that, The driving module includes a driving transistor, wherein both the first dual-gate transistor and the driving transistor are low-temperature polysilicon transistors.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1-19.

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