Power module with low parasitic inductance

Abstract

The present application discloses a low parasitic inductance power module, comprising at least one base extending along a length direction; a carrier plate provided with at least one input and output bus; a first unit comprising a first circuit base provided on the base along a width direction, the first circuit base being provided with a plurality of first power elements, each first power element having a first current input end and a first current output end in parallel with each other; the first current input end or the current output end being connected to the first circuit base; and a second unit. The units are connected to the bus through a plurality of input conductive members and output conductive members staggered and dispersed with each other; thus, individual inductances canceling each other are generated, and the overall parasitic inductance is reduced.

Description

Technical Field

[0001] This invention relates to a power module, and more specifically to a power module with low parasitic inductance. Background Technology

[0002] Third-generation semiconductors are currently a hot high-tech field, playing a crucial role in the development of 5G, electric vehicles, and renewable energy. Also known as "wide-bandgap semiconductors," third-generation semiconductors generally refer to silicon carbide (SiC) or gallium nitride (GaN), whose bandgap is approximately three times that of traditional semiconductors such as silicon (Si) and gallium arsenide (GaAs). They can be used in high-frequency, high-temperature, high-current, and high-voltage operating environments, and overall exhibit excellent performance and stability.

[0003] Among the many application areas of third-generation semiconductors, the demand for power semiconductor components in electric vehicles is undoubtedly the main driving force. The core technologies of electric vehicles lie in "batteries, motors, and electronic controls," which are briefly explained below: First, the three-phase motor is the heart of an electric vehicle. It uses the generation of a rotating magnetic field (RMF) to drive the rotor inside the motor, thereby driving the wheel axle. In order to generate a rotating magnetic field, the three-phase motor needs to use alternating current with phase difference as power. However, the battery packs equipped in electric vehicles, such as lithium batteries, are direct current (DC) power sources. This means that DC to AC conversion is required between the battery and the motor. This conversion is achieved by the brain of the electric vehicle—the inverter.

[0004] An inverter's function extends beyond simply converting input current into AC signals; it can also regulate a three-phase motor using technologies like Pulse Width Modulation (PWM). Essentially, an inverter is a power module containing the aforementioned power semiconductors, using circuit design to electronically control the motor. For example, the faster the rotating magnetic field rotates, the faster the rotor inside the motor. The rotational speed of the magnetic field is determined by the frequency of the AC signal. This means that an electric vehicle can directly change the motor speed by controlling the frequency of the input current, providing a more reliable and linear control method compared to traditional internal combustion engines. Furthermore, the magnitude of the motor's input current directly affects the strength of the generated magnetic field. For high-power output electric vehicles, a power module capable of handling large currents is essential.

[0005] In alternating current circuits, the flow of current through wires or components generates a time-varying magnetic field according to Ampere's law. Furthermore, according to Faraday's law of induction and Leng's law, this time-varying magnetic field produces a counteracting induced electromotive force, affecting the current signal. This effect is similar to inductance and is therefore generally called "parasitic inductance" or "stray inductance." This unintended parasitic inductance is undesirable in practice because it hinders the rapid transformation of the current signal. Typically, this effect can be ignored at low frequencies, but under high-frequency, high-current operating conditions, the influence of stray inductance becomes increasingly severe. It can cause phase delay or lead in the signal, distorting the overall signal, affecting transmission and conversion efficiency, reducing stability, and significantly impacting the efficiency of a motor in converting electrical energy into mechanical energy.

[0006] US Patent 10405450 B2 discloses problems caused by parasitic inductance in high-power modules, such as voltage shooting and ringing. Furthermore, for parallel power modules, it also includes temperature unevenness caused by current imbalance. All of these factors can lead to circuit instability, reduced conversion efficiency, and even limit the maximum switching frequency. Therefore, if... Figure 1 As shown, this design proposes reducing circuit length, increasing conductor cross-sectional area, generating destructive magnetic fields, and reducing module height to bring the power module closer to the endpoints. The current, following the current direction 8, passes through the two power components 7 and forms a return current region 9 at the output bus, which can reduce locally generated parasitic inductance. However, this layout, because the output bus, located slightly above the center of the diagram, can only be close to the circuit below in a localized area in the center, and must maintain distance from the wiring area on the right side of the diagram, limits its effectiveness in reducing parasitic inductance.

[0007] like Figure 2 As shown, US Patent 8637964 B2 also discloses a low stray inductance power module, which achieves this by designing the return current as close as possible to the original current path in the circuit, with the current direction 8 also forming a return path within the power module. However, this horizontal dual-loop layout can lead to current unevenness under high current and high frequency switching because the inner and outer loops of each loop have different travel distances, and the outer loops are relatively far apart, limiting the effect of stray inductance cancellation. Summary of the Invention

[0008] Parasitic inductance has a significant impact on the performance of high-frequency circuits. In order to overcome this problem, according to an embodiment of the present invention, it is desirable to provide a power module with low parasitic inductance, which aims to achieve the following objectives: (1) By means of a special circuit conductor layout in which current is shunted in parallel and distributed and interleaved, the parasitic inductance of the overall power module can be effectively and significantly reduced, so that the high-frequency, high-current power module can obtain better electrical performance and is not degraded by interference from stray inductance; (2) By connecting large current signals in parallel and using a conductor structure in which they are distributed and interleaved, the parasitic inductance generated is significantly reduced; (3) By means of an interleaved and distributed configuration that is adjusted and changed in the horizontal and vertical directions, the circuit structure design of the low parasitic inductance power module is more flexible.

[0009] According to an embodiment, the present invention provides a low parasitic inductance power module for use in devices requiring high-frequency, high-power input, such as electric vehicle motors. The low parasitic inductance power module comprises: at least one insulating base extending along a length direction; a carrier board having at least one current input bus and at least one current output bus parallel to and insulated from the current input bus along a width direction perpendicular to the length direction; a first unit comprising a first circuit board disposed along the width direction on the insulating base, wherein a plurality of first power elements are evenly distributed on the first circuit board, each of the first power elements having a first current input terminal and a first current output terminal connected in parallel; wherein one of the first current input terminal or the first current output terminal is conductively mounted to the first circuit board; and a second unit comprising a second circuit board disposed along the width direction on the insulating base, and the second circuit board being spaced apart from the first circuit board in the length direction, wherein a plurality of second power elements are evenly distributed on the second circuit board, each of the second power elements having a second current input terminal and a second current output terminal connected in parallel. The first unit and the second unit are connected to the second circuit board via a plurality of series conductive elements arranged separately, with one end connected along the length direction. The carrier board is stacked on the first circuit board or the second circuit board along a height direction perpendicular to the length direction and the width direction. When connected in series to the current input bus and the current output bus, and when the series conductors, the input conductors and the output conductors are positioned in the length direction, their projections onto the planes formed by the length and width directions are staggered and dispersed. The projections onto the plane formed by the length direction and a height direction perpendicular to the length and width directions are at least partially staggered. In this way, the dispersed series conductors, the dispersed input conductors and the dispersed output conductors will form individual inductances that cancel each other out when current passes through them, thereby reducing the overall parasitic inductance.

[0010] Compared to existing technologies, the low parasitic inductance power module of this invention distributes the large current signal input to the module by using power semiconductors such as SiC and GaN connected in parallel. Each power semiconductor is equipped with multiple wires distributed along the width direction and connected longitudinally to distribute and stabilize the large current input and output. By distributing and interleaving the wires, the induced magnetic field generated by each wire cancels each other out in a short distance, thereby effectively reducing the parasitic inductance effect caused by high-frequency current. In particular, whether the interleaving occurs in the width direction, the height direction, or even both directions simultaneously, it can flexibly meet the height or width restrictions of users with different structural needs, producing a high-power module with excellent high-frequency response and electrical performance. It can effectively reduce the adverse effects of parasitic inductance, meet usage requirements, and solve the above problems in one fell swoop. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a high-power module disclosed in US Patent US10405450B2 that can reduce locally generated parasitic inductance.

[0012] Figure 2 This is a schematic diagram of a low-spurious-inductance power module disclosed in US Patent US8637964B2.

[0013] Figure 3 This is a side view of the first preferred embodiment of the present invention.

[0014] Figure 4 This is a top view schematic diagram of the first preferred embodiment of the present invention.

[0015] Figure 5 This is a schematic diagram of the current path projection of the first preferred embodiment of the present invention.

[0016] Wherein: 1 is the power module; 46 is the second current output terminal; 2 is the carrier board; 5 is the insulating base; 20 is the current input bus; 50 is the series conductive component; 22 is the current output bus; 52 is the input conductive component; 3 is the first unit; 54 is the output conductive component; 30 is the first circuit board; 60 is the magnetic field integration path; 32 is the first power element; 7 is the power element; 34 is the first current input terminal; 8 is the current direction; 36 is the first current output terminal; 9 is the return current region; 4 is the second unit; X is the length direction; 40 is the second circuit board; Y is the width direction; 42 is the second power element; Z is the height direction; 44 is the second current input terminal. Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. These embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

[0018] like Figures 3 to 5 As shown, the low parasitic inductance power module 1 provided in the first preferred embodiment of the present invention includes an insulating base 5, on which a first circuit board 30 and a second circuit board 40 are disposed. For ease of explanation, the two circuit boards are arranged along the length direction X defined in the present invention, and Figure 3 The vertical direction is defined as the height direction Z, and the direction perpendicular to the plane of the paper is the width direction Y. In this embodiment, the insulating base 5 is made of a metal material, allowing a heat dissipation device (not shown in the figure) to be installed on the lower side of the power component. In this embodiment, the second circuit board, as shown in the figure, is the same width as the first circuit board but longer, so that the carrier board 2 is positioned above the second circuit board 40. The purpose of this design will become clearer after the following explanation. The carrier board 2 is further provided with a current input bus 20 and a current output bus 22 for inputting large current signals (tens to hundreds of amperes) into the module.

[0019] In this embodiment, the first unit 3 is connected to the current input bus 20. The first unit 3 includes a first circuit board 30 extending along the width direction Y, and five first power elements 32 are evenly distributed, for example, in this embodiment. The first power elements 32 are illustrated as power transistors made of SiC. Of course, in other embodiments, other power transistors can be selected according to application requirements, and the number can also be adjusted. Therefore, the illustrative description of this invention should not be considered a limitation. In this embodiment, the first circuit board is illustrated as a circuit board insulated and mounted on an insulating base 5. When the input current enters from the current input bus 20, it is input to the first power elements 32 through a plurality of input conductive elements 52 connected in parallel. For ease of explanation, the electrode on the bottom side of the first power element 32 that is soldered to the first circuit board 30 is defined as the first current input terminal 34, and the top side of the first current input terminal 34 is defined as the first current output terminal 36. In this embodiment, the input conductive elements 52 are twenty wires that are connected in parallel and distributedly soldered to the first circuit board 30. Therefore, the large input current of tens to hundreds of amperes can be evenly distributed, effectively alleviating the current heating effect of each conductive element. Furthermore, from the current input bus through the input conductor to the first power element and the first current output terminal, all currents are uniformly distributed along the width direction, which almost eliminates the time difference between currents at different locations, avoiding timing asynchrony problems caused by different current travel lengths.

[0020] In the first unit 3 of this embodiment, each first power element 32 is synchronously controlled by a first gate signal. When the gate signal is activated, the source and collector of each power transistor are connected, and the input current signal is transmitted to the second current input terminal 44 of the second circuit board 40 via a plurality of first current output terminals 36 connected in parallel to each other. It is worth noting that the circuit through which the current signal enters and exits the first unit 3 includes the series conductor 50 and the input conductor 52, which in this embodiment are a total of 40 wires forming an interlaced structure in three-dimensional space.

[0021] For ease of explanation, each of the first power elements 32 is used as a dividing line here. Figure 4 As shown, the current is introduced from the current input bus 20 through 20 input conductive elements 52 into each first current input terminal 34 and then into the first power element 32, which is defined as the current input half-stroke; the stage from the first current output terminal 36 through 20 series conductive elements 50 to the second circuit board 40 and into the second power element is called the current output half-stroke.

[0022] If the three-dimensional coordinates of each circuit or wire are defined step by step along the length direction X, at the corresponding positions where the length direction coordinates match, it can be observed that... Figure 4 The length and width directions form a projection onto the XY plane from above. During the current input half-stroke, the 20 aluminum strips of the input conductor 52 are arranged with two strips on each of the outermost sides and four strips in each of the middle sections. During the current output half-stroke, the aluminum strips of the series conductor 50 and the output conductor 54 are arranged in groups of four. The lines between adjacent groups of input conductors 52 and series conductors 50 are arranged in an alternating and dispersed manner during both the current input and output half-strokes. Figure 3 Projecting onto the XZ plane formed by the length direction X and the height direction Z from a side view, it can be seen that the lines between each group of input conductive elements 52 and series conductive elements 50 will intersect. At this time, these 40 conductive elements (20 in each direction) will intersect each other in groups of four in the three-dimensional width and height directions, with two groups on the outermost side of the width direction. Through this dispersed and interwoven distribution, the desired effect is achieved... Figure 5 As shown, each pair of series conductors 50 is placed adjacent to each of the two input conductors 52. Finally, according to Ampere's law: the path integral of the magnetic field of a closed loop is proportional to the magnitude of the current passing through the closed loop, it can be obtained that the magnetic field integral path 60 is zero at the closed loop containing the four currents, thus achieving the effect of eliminating local inductance.

[0023] Since the series conductor 50 distributes the current evenly to the second circuit board 40 along the width direction, and also alternates and disperses with the projection of the output conductor 54 in the XY direction, that is, it travels almost entirely along the same path along the length direction X, the same effect of eliminating local inductance can be achieved. In this embodiment, although the conductor does not extend entirely along the X direction, but has components in the width direction Y and the height direction Z, those skilled in the art should understand that this staggered and dispersed loop design can still ensure a sufficiently uniform distribution of the overall current on the one hand, avoid synchronization delay between power components, and on the other hand, maintain a very close round-trip loop structure in three-dimensional space, so that the overall power module's stray inductance can be reduced to below 5nH, or even below 2nH. Compared to the long-distance loop design of the prior art, not only is the current distribution more uniform, but also, according to Ampere's law analysis, it has a much smaller integral path than the prior art, and does not need to expand the integral area to cover the cross-section of the entire module. In other words, even though the prior art proposes a theoretical concept to reduce parasitic inductance, the round-trip current distribution area is too large, which not only causes uneven current, but also makes the calculation cross-sectional area for canceling parasitic inductance very wide, and the actual effect of eliminating the induced magnetic field is limited. This is the excellent effect of the distributed interleaved design of this invention in eliminating parasitic inductance.

[0024] Similarly, after the current signal reaches the second unit 4 through the first unit 3, it enters the second power element 42 through each second current input terminal 44. As mentioned above, the second power element 42 is also controlled by the corresponding gate signal, so that the overall current is finally output through the second current output terminal 46 and the output conductor 54 into the current output bus 22. Likewise, the second unit 4 also has a structural design in which the input current and output current are dispersed and interleaved, so that the noise in the second half can be greatly eliminated, just like in the first half. In this embodiment, both the first circuit board 30 and the second circuit board 40 are direct copper-clad (DBC) circuit boards, structurally located directly below the output conductive element 54. Above the second circuit board 40, there is a carrier board 2, where the current input bus 20 and the current output bus 22 are insulated from each other and arranged in parallel intervals. This ensures that the current on the carrier board and the current on the second circuit board 40 are in opposite directions and evenly distributed. Although the overlap here is not completely "dispersed and interlaced," the vertical Z-direction overlap and the parallel and close arrangement still have a certain effect on reducing parasitic inductance, leaving no gaps in the circuit layout design for eliminating stray inductance. Even though the above embodiment uses the vertically overlapping second circuit board and carrier board arranged side by side in the Z-direction as an example, the circuit configuration of the present invention is not limited to the above scheme.

[0025] The power module of this invention uses parallel circuits and power components to evenly distribute the large input current, ensuring uniform current flow. Furthermore, the circuits within the module form intersecting and nearly overlapping distributed loops. This distributed and intersecting conduction method significantly reduces parasitic inductance. Therefore, the module using this invention can reduce parasitic inductance to below 5nH. The above description of the embodiments is for illustrative purposes only and not for limitation. Any equivalent effects and other modifications resulting from the structure according to the following claims of this invention fall within the scope of this patent.

Claims

1. A power module with low parasitic inductance, comprising: At least one insulating base extending along a length direction; A carrier board has at least one current input bus and at least one current output bus that is parallel to the current input bus and insulated from the current input bus along a width direction perpendicular to the aforementioned length direction. A first unit includes a first circuit board disposed along the width direction on the insulating base, wherein a plurality of first power elements are evenly distributed on the first circuit board, each of the first power elements having a first current input terminal and a first current output terminal connected in parallel; wherein one of the first current input terminal or the first current output terminal is conductively mounted to the first circuit board; and A second unit includes a second circuit board disposed on the insulating base along the width direction, and the second circuit board spaced apart from the first circuit board along the length direction. A plurality of second power elements are evenly distributed on the second circuit board, each of the second power elements having a second current input terminal and a second current output terminal connected in parallel; wherein one of the second current input terminal or the second current output terminal is conductively mounted to the second circuit board. The aforementioned carrier board is stacked on the first circuit board or the second circuit board along a height direction perpendicular to the aforementioned length direction and the aforementioned width direction; and The first unit and the second unit are connected in series at one end along the length direction via a plurality of dispersed series conductors. The first unit, opposite to the end connected to the second unit, is connected in series to the current input bus or the current output bus via a plurality of dispersed input conductors or a plurality of dispersed output conductors. Similarly, the second unit, opposite to the end connected to the first unit, is connected in series to the current output bus or the current input bus via a plurality of dispersed output conductors or a plurality of dispersed input conductors. When the series conductors, input conductors, and output conductors are positioned in the length direction, their projections onto a plane formed by the length and width directions are staggered and dispersed. The projections of the length direction and a plane perpendicular to the length and width directions are at least partially staggered. This allows the dispersed series conductors, dispersed input conductors, and dispersed output conductors to form individual inductances that cancel each other out when current flows through them, thereby reducing the overall parasitic inductance.

2. The low parasitic inductance power module as described in claim 1, characterized in that, The aforementioned carrier plate is located between the aforementioned first power element and the aforementioned second power element along the aforementioned length direction.

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