A bit synchronization method suitable for a medium voltage carrier system

Abstract

The application relates to the technical field of power line communication and discloses a bit synchronization method suitable for a medium-voltage carrier system, which comprises the following steps: a transmitting end cyclically generates an m sequence as a bit synchronization code stream; the bit synchronization code stream is modulated into a bipolar NRZ code; inter-symbol interference is eliminated by using shaping filtering; after frequency up-conversion, the bit synchronization code stream is sent out through a transmitter; after frame synchronization ends, a phase comparison is used to perform plus-minus pulse operation on a local timing signal and correlation is performed on the received bit synchronization code stream; after bit synchronization deviation is calculated, the deviation time is compensated to the frame synchronization end time. The application is based on the medium-voltage carrier communication system, the correlation characteristics of the m sequence and the difference between the local high-frequency clock and the transmission data rate are utilized on the basis of frame synchronization to compensate for the phase deviation caused by frame synchronization, so that more accurate synchronization end time is obtained, the precision of the clock synchronization system is improved, the deviation caused by synchronization in the clock synchronization technology is reduced to the nanosecond level, and the workload of fault positioning and checking is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power line communication, and particularly relates to a bit synchronization method suitable for a medium-voltage carrier system. BACKGROUND

[0002] With the rapid development of the information age, clock synchronization technology plays a very important role in various industries, and power line communication is no exception. However, in the medium-voltage power line communication system, only the master carrier can obtain the UTC time through the management machine, and the slave machine can only obtain the time by sending a message to the master machine, so there is a certain deviation between the local time of the master machine and the slave machine. The PTP technology can achieve the effect of master-slave clock synchronization to a certain extent. The PTP technology uses the sending timestamp information between two points to calculate the path delay and clock offset. There are many factors that affect the accuracy of PTP calculation results, and the frame synchronization deviation, master-slave crystal oscillator difference, and path asymmetry are relatively large. Since the premise of offset calculation is that the path delay of the master-slave round trip is equal, but the carrier machine will be affected by noise and other factors when performing frame synchronization, resulting in deviation, which makes the PTP calculation also deviate, and cannot make the clock synchronization reach the accuracy of nanoseconds.

[0003] If the carrier machine is only used for communication, the influence of synchronization deviation can be solved by adding prefixes and suffixes to the data packet, but for the fault positioning function using the carrier machine, this is a problem that needs to be solved urgently. In the power line, the accuracy of fault positioning depends on the accuracy of clock synchronization. Assuming that the transmission speed of the power line electrical signal is 2.5*10 8 m / s, the clock synchronization error is 20ns, and the positioning accuracy can reach 5m, but if the clock synchronization error reaches 1000ns, the positioning accuracy reaches 250m, which obviously increases the workload of fault location investigation. SUMMARY

[0004] To solve the above problems in the prior art, the application provides a bit synchronization method suitable for a medium-voltage carrier system, which is based on digital phase-locked loop technology and m sequence, so as to reduce the time error caused by synchronization to the nanosecond level.

[0005] The method comprises the following contents:

[0006] A bit synchronization technology suitable for a medium-voltage carrier system, the specific method is as follows:

[0007] The transmitter end:

[0008] S1: generate a 7-bit m sequence through a linear shift register, and generate 4 cycles to take the 28-bit data as a bit synchronization sequence code;

[0009] S2: using binary phase shift keying (BPSK) modulation signal, the bit synchronization sequence code is converted into bipolar non-return-to-zero (NRZ) code;

[0010] S3: using a shaping filter with cosine roll-off characteristics to perform shaping filter processing on the NRZ code;

[0011] S4: the signal after filtering processing is spliced with frame synchronization header and data symbols, and is subjected to up-conversion processing, and is sent out from the transmitter;

[0012] The receiver end:

[0013] S5: the signal sent by the transmitter is transmitted to the receiver end through the channel, and the received signal is subjected to sampling decision and zero-crossing detection at the receiving end;

[0014] S6: the phase deviation of the bit synchronization code stream after zero-crossing detection and the phase of the local clock is judged, and the number of each plus-minus pulse is counted;

[0015] S7: the bit synchronization code stream is subjected to correlation processing with a 7-bit m-sequence, and the number of correlation peaks is counted;

[0016] S8: the phase deviation width is calculated by using the number of plus-minus pulses and the number of correlation peaks, and is compensated to the frame synchronization end time.

[0017] Thus, through the above steps, the time error caused by bit synchronization is reduced.

[0018] Further, in the step S1, the data contained in the 7-bit m-sequence is:

[0019]

[0020] In the formula, n is the number of m-sequence periods; C is the feedback coefficient, which can be obtained by looking up the table, for example, the feedback coefficient of the 7-period m-sequence is 13 in octal number.

[0021] Further, in order to obtain the baseband transmission characteristic without inter-symbol interference, the shaping filter spectrum characteristic in the step S3 is as follows:

[0022]

[0023] In the formula, T s is the sampling period,

[0024] Thus, we can get:

[0025]

[0026] In the formula, H(ω) is the spectrum of the shaping filter, and its time domain signal is as follows:

[0027]

[0028] Furthermore, in step S3, the NRZ signal after BPSK modulation in the transmitter has an impulse response signal characteristic. Assume that the NRZ signal is:

[0029]

[0030] Then the bit synchronization signal after shaping filtering is:

[0031]

[0032] Furthermore, the signal received by the receiving end in step S5 is:

[0033]

[0034] Where n R (t) is the noise.

[0035] Furthermore, in step S5, after sampling and judging the frame synchronization signal received from the transmitter, the following is obtained:

[0036]

[0037] Where, T s Refers to the sampling period, r(kT s +t0) refers to the sampling judgment result, n R Refers to channel noise.

[0038] Furthermore, in step S5, the sampling decision result is subjected to a 4-level cache process and then subjected to a logical exclusive OR process with the original signal to obtain a zero-crossing detection result.

[0039] Furthermore, in step S6, the bit synchronization code stream is a bit synchronization sequence code signal, and the specific determination method is as follows:

[0040] S601: If the phase of the local clock lags behind the phase of the bit synchronization code stream, the local clock signal is reduced by short pulses, and the count is a=a+1, where a is the number of short pulses, and the process returns to step 2 to re-determine the phase difference.

[0041] S602: If the phase of the local clock is ahead of the phase of the bit synchronization code stream, the local clock signal increases by a short pulse, and the count is b=b+1, where b is the number of short pulses, and the process returns to step S2 to re-determine the phase difference.

[0042] S603: If the phase of the local clock is consistent with the phase of the bit synchronization code stream, execute S7.

[0043] Furthermore, in step S6, when the local timing signal is subjected to pulse addition and subtraction processing, each time a short pulse signal is added or subtracted, the adjusted phase width is 1 / N of the bit synchronization code stream rate. At this time, the detection clock frequency is 4N times the data rate. Therefore, the faster the detection clock frequency, the higher the phase adjustment accuracy, and the local timing signal phase will converge to the phase of the bit synchronization code stream faster.

[0044] The beneficial effect of the present invention is that the deviation caused by frame synchronization can be reduced to nanosecond level (depending on the local high-frequency clock frequency) by performing phase adjustment and related calculation on the bit synchronization code element. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 The figure is a flow chart of a bit synchronization method applicable to a medium voltage carrier system according to the present invention. DETAILED DESCRIPTION

[0046] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0047] Example: Figure 1 As shown, the technical solution of the present invention includes the following steps:

[0048] Transmitter side:

[0049] S1: Generate a 7-bit m-sequence through a linear shift register, loop it four times, and use the 28-bit data as the bit synchronization sequence code;

[0050] The bit synchronization sequence code is as follows:

[0051] S2: Use BPSK modulation signal to convert the bit synchronization sequence code into bipolar NRZ code;

[0052] The NRZ code is as follows:

[0053] S3: Use the impulse response with cosine roll-off characteristics to perform shaping filtering on the NRZ code. The impulse response signal is:

[0054]

[0055] Where, T s is the sampling period;

[0056] The shaping filter processing signal is:

[0057]

[0058] Where h(t) is the channel response signal.

[0059] S4: The filtered signal is concatenated with the frame synchronization header and data symbols, and then up-converted and sent out from the transmitter.

[0060] Receiver side:

[0061] S5: The signal sent by the transmitter is transmitted to the receiver through the channel, and the receiver performs sampling judgment and zero-crossing detection on the received signal;

[0062] The received signal is:

[0063]

[0064] The received frame synchronization signal is sampled and judged to obtain:

[0065]

[0066] In the formula, r(kT s +t0) refers to the sampling judgment result, n R Refers to channel noise.

[0067] The sampling judgment result is processed by 4-level cache and then logically XORed with the original signal to obtain the zero-crossing detection result.

[0068] S6: Determine the deviation between the phase of the bit synchronization code stream after zero-crossing detection and the phase of the local clock, and count each addition and subtraction pulse;

[0069] The specific judgment method is as follows:

[0070] S601: If the phase of the local clock lags behind the phase of the bit synchronization code stream, the local clock signal is reduced by short pulses, and the count is a=a+1, where a is the number of reduced short pulses, and the process returns to step S6 to re-determine the phase difference.

[0071] S602: If the phase of the local clock is ahead of the phase of the bit synchronization code stream, the local clock signal increases by a short pulse, and the count is b=b+1, where b is the number of increased short pulses, and the process returns to step S6 to re-determine the phase difference.

[0072] S603: If the phase of the local clock is consistent with the phase of the bit synchronization code stream, execute S7.

[0073] When adding or subtracting pulses from the local timing signal, each time a short pulse signal is added or subtracted, the adjusted phase width is 1 / N of the bit synchronization code stream rate. At this time, the detection clock frequency is 4N times the data rate. Therefore, the faster the detection clock frequency, the higher the phase adjustment accuracy, and the faster the local timing signal phase converges to the phase of the bit synchronization code stream.

[0074] Specifically, the phase comparison function can be achieved by performing a logical AND operation on the zero-crossing detection result and the positive and negative phase local timing signals respectively. If the local timing is ahead of the bit synchronization signal, a positive pulse will be output after the logical AND gate, thereby triggering the closing of the normally open gate, causing the local high-frequency clock to deduct one pulse, achieving the effect of lagging the local phase by one pulse width; conversely, it triggers the opening of the normally closed gate, causing the local high-frequency clock to add one pulse, achieving the effect of advancing the local phase by one pulse width. Each time the normally open gate is triggered to close, b is incremented by one, and each time the normally closed gate is triggered to open, a is incremented by one.

[0075] S7: Correlation processing is performed on the bit synchronization code stream and the 7-bit m-sequence, and the number of correlation peaks is counted. The number of correlation peaks is recorded as l. Because one segment of the m-sequence corresponds to one correlation peak, if l is equal to 4, it means that the frame synchronization result does not deviate from a segment of the m-sequence. Otherwise, based on the number of correlation peaks, it can be judged that the frame synchronization result deviates from 4-1 complete m-sequences.

[0076] S8: Calculate the phase deviation width using the number of addition and subtraction pulses and the number of correlation peaks, and compensate it to the end time of frame synchronization. Assuming that the detection clock frequency is 4N times the data rate, the addition and subtraction pulse width is 1 / N of the data rate. Assuming the data sampling rate is f s , then it is necessary to add the compensation time delta_t=1 / (4*f s )*(ab)+(4-l)*7 / f s Through the above steps, this embodiment reduces the deviation caused by frame synchronization to 12.5 ns when the local high-frequency clock frequency is 80 MHz, thereby improving the clock accuracy.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Ordinary technicians in the relevant field can still modify or replace the specific implementation methods of the present invention with equivalents by referring to the above embodiments. Any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention are within the scope of protection of the claims of the present invention to be approved.

Claims

1. A bit synchronization method applicable to a medium voltage carrier system, characterized in that: The specific steps include: S1: Generate a 7-bit m-sequence through a linear shift register, loop it four times, and use the 28-bit data as the bit synchronization sequence code; S2: Use binary phase shift keying (BPSK) to modulate the signal and convert the bit synchronization sequence code into bipolar non-return-to-zero (NRZ) code. S3: Use a shaping filter with a cosine roll-off characteristic to perform shaping filtering on the NRZ code; S4: The filtered signal is concatenated with the frame synchronization header and data symbols, and then up-converted and sent out from the transmitter. Receiver side: S5: The signal sent by the transmitter is transmitted to the receiver through the channel, and the receiver performs sampling judgment and zero-crossing detection on the received signal; S6: Determine the deviation between the phase of the bit synchronization code stream after zero-crossing detection and the phase of the local clock, and count each addition and subtraction pulse; The deviation is determined as follows: S601: If the phase of the local clock lags behind the phase of the bit synchronization code stream, the local clock signal is reduced by short pulses, and the count is a=a+1, where a is the number of reduced short pulses, and the process returns to step S6 to re-determine the phase difference. S602: If the phase of the local clock is ahead of the phase of the bit synchronization code stream, the local clock signal increases by a short pulse, and the count is b=b+1, where b is the number of increased short pulses, and the process returns to step S6 to re-determine the phase difference. S603: If the phase of the local clock is consistent with the phase of the bit synchronization code stream, execute S7; The addition and subtraction pulse counting methods are as follows: S604: Perform a logical AND operation on the zero-crossing detection result and the positive and negative phase local timing signals respectively. If the local timing is ahead of the bit synchronization signal, a positive pulse will be output after the logical AND gate, thereby triggering the closing of the normally open door; otherwise, the normally closed door will be triggered to open. Each time the normally open door is triggered to close, b is incremented by one, and each time the normally closed door is triggered to open, a is incremented by one. S7: Correlation processing is performed on the bit synchronization code stream and the 7-bit m-sequence, and the number of correlation peaks is counted. The number of correlation peaks is recorded as l. If l = 4, it means that the frame synchronization result does not deviate from a section of the m-sequence. Otherwise, based on the number of correlation peaks, it is judged that the frame synchronization result deviates from 4-1 complete m-sequences; S8: Calculate the phase deviation width using the number of addition and subtraction pulses and the number of correlation peaks, and compensate it to the frame synchronization end time.

2. A bit synchronization method applicable to a medium voltage carrier system according to claim 1, characterized in that: In step S1, the data contained in the 7-bit m-sequence is: Where n is the number of periods of the m-sequence; C is the feedback coefficient, which can be obtained by looking up the table. For example, the feedback coefficient of the m-sequence with a period of 7 is 13 in octal.

3. The bit synchronization method applicable to a medium voltage carrier system according to claim 1, characterized in that: In order to obtain baseband transmission characteristics without inter-code interference, the shaping filter spectrum characteristics in step S3 are as follows: Where, T s is the sampling period, From this we can get: Where H(ω) is the spectrum of the shaping filter, and its time domain signal is as follows:

4. The bit synchronization method applicable to a medium voltage carrier system according to claim 1, characterized in that: In step S3, the NRZ signal after BPSK modulation in the transmitter has an impulse response signal characteristic. Assume that the NRZ signal is: Then the bit synchronization signal after shaping filtering is:

5. The bit synchronization method applicable to a medium voltage carrier system according to claim 1, characterized in that: The signal received by the receiving end in step S5 is: Where n R (t) is noise; In step S5, after sampling and judging the frame synchronization signal received from the transmitter, the following is obtained: Where, T s Refers to the sampling period, r(kT s +t0) refers to the sampling judgment result, n R Refers to channel noise; The sampling judgment result is processed by 4-level cache and then logically XORed with the original signal to obtain the zero-crossing detection result.

6. The bit synchronization method applicable to a medium voltage carrier system according to claim 1, characterized in that: In step S6, when adding and subtracting pulses are performed on the local timing signal, each time a short pulse signal is added or subtracted, the adjusted phase width is 1 / N of the bit synchronization code stream rate. At this time, the detection clock frequency is 4N times the data rate. Therefore, the faster the detection clock frequency, the higher the phase adjustment accuracy, and the faster the phase of the local timing signal will converge to the phase of the bit synchronization code stream.

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