A 600M pixel microscope chip

Abstract

The present invention discloses a 600M pixel microscopy chip, comprising an image sensor pixel array, a digital control circuit, a peripheral analog circuit, and a data output interface. The image sensor pixel array includes pixel subarrays Subarray_0, Subarray_1, Subarray_2, and Subarray_3, each of which includes 10240×13600 pixels. The data output interface includes MIPI interfaces MIPI0, MIPI1, MIPI2, and MIPI3, with MIPI0 corresponding to Subarray_0, MIPI1 corresponding to Subarray_1, MIPI2 corresponding to Subarray_2, and MIPI3 corresponding to Subarray_3. The present invention divides the image sensor pixel array into four pixel subarrays, significantly reducing computational complexity and increasing data transmission rates while achieving 600M pixels.

Description

Technical Field

[0001] The present invention relates to a 600M pixel microscopy chip. Background Art

[0002] Image sensor chips are core components of digital optical imaging modules and are widely used in smartphones, life sciences, security monitoring, autonomous driving, industrial testing, and other fields. However, in high-end equipment such as industrial testing, life sciences, astronomy, and broadcasting, image sensor chips are primarily imported.

[0003] The 600M pixel microscopy chip is a 600-megapixel imaging chip, a high-resolution microscopy chip that enables very detailed image capture and analysis. This chip has a very high pixel density and can capture very small cellular and microbial structures, making it very useful for life science and medical research.

[0004] Specifically, the 600M pixel microchip can be used in high-resolution microscope imaging systems, such as fluorescence microscopes and atomic force microscopes. These systems can place samples under highly stable conditions for imaging, illuminate the samples with lasers or other light sources, and then capture the reflected or transmitted light signals, which are then digitized and processed using the 600M pixel chip.

[0005] The 600M pixel microchip can provide more detailed information on cells, tissues, bacteria, and tiny objects, helping researchers better understand basic and applied research in biology and medicine. For example, it can be used to observe and study life processes such as cell division, intracellular transport, and molecular interactions. It can also be used in fields such as drug development and microelectronics manufacturing.

[0006] However, the realization of 600M pixel microscopy chips in the existing technology has many objective technical difficulties.

[0007] Therefore, a 600M pixel microscopy chip is needed to solve the above problems. Summary of the Invention

[0008] The purpose of the present invention is to overcome the problems existing in the prior art and provide a 600M pixel microscopy chip.

[0009] The present invention includes an image sensor pixel array, a digital control circuit, a peripheral analog circuit, and a data output interface. The image sensor pixel array includes a pixel subarray Subarray_0, a pixel subarray Subarray_1, a pixel subarray Subarray_2, and a pixel subarray Subarray_3. The pixel subarrays Subarray_0, Subarray_1, Subarray_2, and Subarray_3 each include 10240×13600 pixels. The data output interface includes a MIPI interface MIPI0, a MIPI interface MIPI1, a MIPI interface MIPI2, and a MIPI interface MIPI3. The MIPI interface MIPI0 corresponds to the pixel subarray Subarray_0, the MIPI interface MIPI1 corresponds to the pixel subarray Subarray_1, the MIPI interface MIPI2 corresponds to the pixel subarray Subarray_2, and the MIPI interface MIPI3 corresponds to the pixel subarray Subarray_3.

[0010] Furthermore, the digital control circuit includes a timing control module, a data reading module, a data transmission module, a data processing module, a data storage module and a communication interface.

[0011] Furthermore, the analog circuit includes a pixel measurement and data generation module, a switch physical implementation module, a temperature detection module, a voltage conversion module and a clock generation module.

[0012] Furthermore, the pixel subarray Subarray_2 and the pixel subarray Subarray_0 are mirror-symmetrical in left-right direction, the pixel subarray Subarray_3 and the pixel subarray Subarray_1 are mirror-symmetrical in left-right direction, the pixel subarray Subarray_0 and the pixel subarray Subarray_1 are mirror-symmetrical in top-bottom direction, and the pixel subarray Subarray_2 and the pixel subarray Subarray_3 are mirror-symmetrical in top-bottom direction.

[0013] Furthermore, the pixel subarray Subarray_0 and the pixel subarray Subarray_1 have the same pixel reading order in each row, and the pixel subarray Subarray_2 and the pixel subarray Subarray_3 have the same pixel reading order in each row.

[0014] Furthermore, the pixel subarray Subarray_3 reads pixels from row 20479 to row 10240, the pixel subarray Subarray_2 reads pixels from row 0 to row 10239, the pixel subarray Subarray_0 reads pixels from row 0 to row 10239, and the pixel subarray Subarray_1 reads pixels from row 20479 to row 10240.

[0015] Furthermore, each row of the pixel subarray Subarray_0, pixel subarray_1, pixel subarray_2 and pixel subarray_3 is evenly divided into eight parts: A0_0, A0_1, A1_0, A1_1, A2_0, A2_1, A3_0 and A3_1. When reading, A0_0, A1_0, A2_0 and A3_0 are read first, and then A0_1, A1_1, A2_1 and A3_1 are read.

[0016] Furthermore, the data output for each pixel is 10 bits.

[0017] Furthermore, the data bit width of the MIPI interface MIPI0, MIPI interface MIPI1, MIPI interface MIPI2 and MIPI interface MIPI3 is 64 bits, and the bit width of the data word inside the chip is 256 bits. The data word inside the chip is converted into 4 64-bit serials and sent through the MIPI interface MIPI0, MIPI interface MIPI1, MIPI interface MIPI2 or MIPI interface MIPI3.

[0018] Beneficial effects: The present invention divides the pixel array of the image sensor into four pixel sub-arrays, which can greatly reduce the calculation difficulty and improve the data transmission rate on the basis of achieving 600M pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is the chip functional block diagram of the 600M pixel microscopy chip;

[0020] Figure 2 is a structural diagram of an image sensor pixel array;

[0021] Figure 3 Schematic diagram of data word parallel-to-serial conversion;

[0022] Figure 4 is a schematic diagram of a data word;

[0023] Figure 5 This is a schematic diagram of the data division between quadrant 0 and quadrant 1;

[0024] Figure 6 Schematic diagram of pixel grouping;

[0025] Figure 7 Schematic diagram of the order of reading pixels in each row of quadrant 0 and quadrant 1;

[0026] Figure 8 Schematic diagram of data division for quadrant 2 and quadrant 3;

[0027] Figure 9 Schematic diagram of the order of reading pixel data in quadrants 2 and 3. DETAILED DESCRIPTION

[0028] The present invention will now be described in further detail with reference to the accompanying drawings.

[0029] Example 1:

[0030] See also Figure 1 As shown, the 600M pixel microscopy chip of the present invention includes an image sensor pixel array, a peripheral analog circuit, a digital control circuit and a data output interface.

[0031] The digital control circuit includes a timing control module, a data reading module, a data transmission module, a data processing module, a data storage module and a communication interface.

[0032] The analog circuit includes a pixel measurement and data generation module, a switch physical implementation module, a temperature detection module, a voltage conversion module and a clock generation module.

[0033] See also Figure 1 As shown in the figure, the chip functional block diagram: the chip system clock is 200M, and the chip mainly consists of three parts: image sensor pixel array, peripheral analog circuit, digital control circuit and data output interface.

[0034] Digital circuits are responsible for timing control, data reading, data transmission, data processing, data storage, and interface communication;

[0035] The analog circuit is responsible for pixel measurement and data generation, switch physical implementation, temperature detection, voltage conversion and clock generation;

[0036] Image sensor pixel array structure:

[0037] See also Figure 2 As shown, the image sensor pixel array consists of 20480 rows, each row has 27200 pixels, and the entire array size is 20480×27200. The entire pixel array is divided into four subarrays, each subarray size is 10240×13600, as follows Figure 2 shown.

[0038] Please participate Figure 3As shown, each pixel outputs 10 bits of data. The data of the entire pixel array is output through four MIPI interfaces, each corresponding to a pixel subarray. For example, MIPI0 corresponds to Subarray_0, MIPI1 corresponds to Subarray_1, MIPI2 corresponds to Subarray_2, and MIPI3 corresponds to Subarray_3.

[0039] Please participate Figure 4 As shown, each frame consists of several data words (WORD), each data word is 256 bits. Each data word can store up to 25 pixels, each pixel is 10 bits, a total of 250 bits, stored in the lower 250 bits of the data word, [255:250] are all 0.

[0040] Pixel reading order

[0041] See also Figure 5 As shown in the figure, taking row 0 of Subarray_0 as an example, the data is evenly divided into eight sections, namely A0_0, A0_1, A1_0, A1_1, A2_0, A2_1, A3_0, and A3_1. Each section has 1700 pixels. A0_0, A1_0, A2_0, and A3_0 are read out first, followed by A0_1, A1_1, A2_1, and A3_1.

[0042] See also Figure 6 As shown, taking A0_0 as an example, a total of 1700 pixels are divided into 4 groups g(0-3), each group has 17×25 pixels.

[0043] See also Figure 7 As shown, when reading pixels, first read the g0 part of A0_0, A1_0, A2_0, and A3_0, then read the g0 part of A0_1, A1_1, A2_1, and A3_1, and then read the g1, g2, and g3 parts of the data in the order of reading the g0 data. The MSB of each word (data word) corresponds to the high-order pixel, and the LSB corresponds to the low-order pixel. The reading of g0-g3 in row 0 is completed, and the next row is read until row 10239 is completed, and the reading of Subarray_0 data is completed. The schematic diagram of reading data for each row is shown as follows Figure 7 shown.

[0044] For the Subarray_1 pixel array, the row transfer order is the same as that for the Subarray_0 array. However, Subarray_1 starts reading from the last row, that is, reading row 20479 first, then reading the next row up, and finishing at row 10240.

[0045] Subarray_2 is mirror image symmetrical with Subarray_0, and Subarray_3 is mirror image symmetrical with Subarray_1. However, the data output order is different. Figure 8 As shown, taking row 0 as an example, it is divided into B0-B3, and is first output from the rightmost B3_1, B2_1, B1_1, and B0_1 in sequence. There are 4 groups of 272 data words, each group of 68 data words (Word_0-Word_67), which are read in the order of g(3)-g(0). Then B3_0, B2_0, B1_0, and B0_0 are read in sequence. At this point, the reading of row 0 data is completed, and then the next row to row 10239 is read. The reading order of each row of Subarray_3 is the same as that of Subarray_2, but it reads from the last row 20479 to row 10240. The MSB of each Word (data word) corresponds to the high-order pixel, and the LSB corresponds to the low-order pixel. The schematic diagram of the reading order of each row is as follows Figure 9 shown.

[0046] MIPI specifications:

[0047] MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2), Version 1.2, 22 January 2014.

[0048] MIPI Alliance Specification for D-PHY, Version 1.2, 01 August 2014.

[0049] There are a total of 4 4-Lane MIPI interfaces.

[0050] Because the data bit width of the chip's internal MIPI interface is 64 bits, and the chip's internal data word (WORD) is 256 bits wide, the data word must be converted from 256 bits into four 64-bit serial bits before it can be sent over MIPI. The highest 64 bits are sent first, and the lowest 64 bits are sent last.

[0051] The MIPI (Mobile Industry Processor Interface) Alliance was founded in 2003 by companies including ARM, Nokia, ST, and TI. MIPI is an open standard developed by the MIPI Alliance for mobile application processors. Its goal is to standardize internal mobile phone interfaces, such as camera, display, and RF / baseband interfaces, thereby reducing design complexity and increasing flexibility. MIPI is not a single interface or protocol, but rather encompasses a suite of protocols and standards designed to meet the unique requirements of various subsystems. Common protocols include CSI (camera interface), DSI (display interface), DigRF (radio frequency interface), and SLIMbus (microphone / speaker interface). Currently, more mature interface applications include DSI (Display Serial Interface) and CSI (Camera Serial Interface). DSI defines a high-speed serial interface between the processor and display module; CSI defines a high-speed serial interface between the processor and camera module.

[0052] The present invention divides the pixel array of the image sensor into four pixel sub-arrays, which can greatly reduce the calculation difficulty and improve the data transmission rate on the basis of achieving 600M pixels.

Claims

1. A 600M pixel microscopy chip, comprising an image sensor pixel array, a digital control circuit, a peripheral analog circuit, and a data output interface, characterized in that: The image sensor pixel array includes a pixel subarray Subarray_0, a pixel subarray Subarray_1, a pixel subarray_2, and a pixel subarray_3, each of which includes 10240×13600 pixels. The data output interface includes a MIPI interface MIPI0, a MIPI interface MIPI1, a MIPI interface MIPI2, and a MIPI interface MIPI3, wherein the MIPI interface MIPI0 corresponds to the pixel subarray Subarray_0, the MIPI interface MIPI1 corresponds to the pixel subarray Subarray_1, the MIPI interface MIPI2 corresponds to the pixel subarray Subarray_2, and the MIPI interface MIPI3 corresponds to the pixel subarray Subarray_3; The pixel subarray Subarray_2 and the pixel subarray Subarray_0 are mirror-symmetrical in left-right direction, the pixel subarray Subarray_3 and the pixel subarray Subarray_1 are mirror-symmetrical in left-right direction, the pixel subarray Subarray_0 and the pixel subarray Subarray_1 are mirror-symmetrical in top-bottom direction, and the pixel subarray Subarray_2 and the pixel subarray Subarray_3 are mirror-symmetrical in top-bottom direction; The pixel subarrays Subarray_0 and Subarray_1 have the same pixel reading order in each row, and the pixel subarrays Subarray_2 and Subarray_3 have the same pixel reading order in each row. The pixel subarray Subarray_3 reads pixels from row 20479 to row 10240, the pixel subarray Subarray_2 reads pixels from row 0 to row 10239, the pixel subarray Subarray_0 reads pixels from row 0 to row 10239, and the pixel subarray Subarray_1 reads pixels from row 20479 to row 10240; Each row of the pixel subarray Subarray_0, pixel subarray_1, pixel subarray_2 and pixel subarray_3 is evenly divided into eight parts: A0_0, A0_1, A1_0, A1_1, A2_0, A2_1, A3_0 and A3_1. When reading, A0_0, A1_0, A2_0 and A3_0 are read first, and then A0_1, A1_1, A2_1 and A3_1 are read.

2. The 600M pixel microscopy chip according to claim 1, wherein: The digital control circuit includes a timing control module, a data reading module, a data transmission module, a data processing module, a data storage module and a communication interface.

3. The 600M pixel microscopy chip according to claim 1, wherein: The analog circuit includes a pixel measurement and data generation module, a switch physical implementation module, a temperature detection module, a voltage conversion module and a clock generation module.

4. The 600M pixel microscopy chip according to claim 1, wherein: The data output for each pixel is 10 bits.

5. The 600M pixel microscopy chip according to claim 1, wherein: The data bit width of the MIPI interface MIPI0, MIPI interface MIPI1, MIPI interface MIPI2 and MIPI interface MIPI3 is 64 bits, and the bit width of the data word inside the chip is 256 bits. The data word inside the chip is converted into 4 64-bit serials and sent through the MIPI interface MIPI0, MIPI interface MIPI1, MIPI interface MIPI2 or MIPI interface MIPI3.

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