Combining unit with settable time constant

Abstract

According to an aspect, a merging unit with a settable time constant is provided, comprising one or more input interfaces for receiving a plurality of input signals characterizing one or more voltages and / or one or more currents measured by a plurality of measuring devices, a digital processing device, and one or more output interfaces for outputting an output signal. The digital processing device is configured to high-pass filter at least one input signal of the plurality of input signals using one or more digital filters for reducing a time constant associated with said at least one input signal of the one or more input signals to match a target time constant or for increasing a high-pass cutoff frequency associated with said at least one input signal of the one or more input signals to match a target high-pass cutoff frequency, and to merge the plurality of input signals into an output signal having a predefined output format after high-pass filtering.

Description

TECHNICAL FIELD

[0001] Various example embodiments relate to substation protection and metering systems. BACKGROUND

[0002] Merge units are commonly used in substation protection and metering systems for measuring current and voltage signals from sensors and instrument transformers and merging the measured data into a standard digital output format for use by other devices, for example for various power system protection application purposes. The current signals can be associated with a number of different time constants (or equivalently a number of different high-pass cut-off frequencies). This becomes a problem when sharing measurements between devices of different types. That is, any current differential protection algorithm can not necessarily see the same current measurements accurately, even though they should be equal, when the input time constants (or equivalently high-pass cut-off frequencies) are different. This can occur especially at transients or when the frequency response is not solely made up of the nominal frequency or does not include the nominal frequency at all. SUMMARY

[0003] According to an aspect, there is provided an embodiment according to the present invention. Also, there is provided a preferred embodiment according to the present invention.

[0004] One or more examples of implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

[0005] Some embodiments provide apparatuses, methods, and computer programs for implementing a settable time constant or high-pass cut-off frequency. BRIEF DESCRIPTION OF DRAWINGS

[0006] In the following, example embodiments will be described in more detail with reference to the accompanying drawings, in which:

[0007] Figure 1 An exemplary system according to an embodiment is shown; and

[0008] Figures 2 to 4 A process according to an embodiment is shown. DETAILED DESCRIPTION

[0009] The following embodiments are presented by way of example only. Although the specification can refer to "an" or "one" embodiment in several locations, this does not necessarily mean that each reference must be to the same embodiment, or that a particular feature only applies to a single embodiment. Single features or individual embodiments can also be combined with other single features or other embodiments. Furthermore, the described implementation can be implemented as a method, apparatus, or article of manufacture using standard components.

[0010] As used in this application, the term "circuitry" can refer to one or more or all of the following: (a) hardware-only circuitry such as only analog and / or digital circuitry, and (b) combinations of hardware circuits and software (and / or firmware), such as (as applicable): (i) combinations of analog and / or digital hardware circuit(s) with software / firmware, and (ii) portions of hardware processor(s) with software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a terminal device or access node, to perform various functions) and (c) hardware circuit(s) for operating without software, such as a microprocessor or a portion of a microprocessor, but with software needed for operation that can not be present if it is not required for the hardware circuitry to operate. This definition of "circuitry" applies to all uses of this term in this application, including in any claims. As a further example, as used in this application the term "circuitry" also covers an implementation that has a hardware circuit or processor (or multiple processors) and software (and / or firmware) that works together to cause an apparatus, such as a terminal device or access node, to perform various functions) or a hardware circuit or processor (or multiple processors) and its (or their) accompanying software and / or firmware that work together to cause an apparatus, such as a terminal device or access node, to perform various functions. The term "circuitry" also encompasses, for example, and if applicable to a particular claim element, baseband integrated circuit(s) for an access node or terminal device or other computing or network device.

[0011] The term "high-pass cutoff frequency" used hereinafter can be defined as the -3dB point of the high-pass frequency response (i.e. the frequency at which the value of the high-pass frequency response has decreased by 3dB from its maximum value). The high-pass cutoff frequency is via the well-known equation connected to a time constant, where f c is the high-pass cutoff frequency and τ is the time constant.

[0012] As mentioned above, merging units are commonly used in substation protection and automation systems for measuring current and voltage signals from sensors and instrument transformers and merging the measured data into a standard digital output format for use by other devices, e.g. for various power system protection application purposes. Generally, it is advantageous if the current inputs of the merging unit have a high time constant (i.e. a high pass characteristic with a low cut-off frequency) as this enables the merging unit to better represent the decaying DC offset in case of power network faults. However, combining different current input technologies or even the same technology but different components often results in having to deal with different input time constants. This becomes a problem in particular when sharing the measurement results between devices of different types. When the input time constant is different between different input signals (i.e. between different measurement results), a current differential protection algorithm can effectively treat the two current measurements as having different values. The IEC 61869-6 standard gives a limit of a high pass cut-off frequency of maximum 1 Hz, but below 1 Hz it can be any value depending on the implementation. Generally, different types of devices or even devices of different manufacturers are not combined, but the IEC 61850 standard aims at enabling this. The input time constant is generally a result of the hardware design and thus it is not a parameter that can be dynamically changed by the user.

[0013] The embodiments discussed in detail below attempt to overcome at least some of the above-mentioned problems by implementing a settable time constant (or a settable high pass cut-off frequency) in the merging unit. This settable time constant or high pass cut-off frequency will enable the user to match the time constants between the input hardware used (if they are of different types) in order to, for example, improve the differential protection accuracy.

[0014] Figure 1 An exemplary system 100 according to an embodiment is shown. The system 100 can be referred to as a substation automation system (SAS), a power system or a substation protection and metering system. The system 100 comprises a plurality of measuring devices 111, 112, 113, a merging unit 101 and one or more network devices 121, 122. Any of the illustrated elements can be logical elements implemented as hardware or software or a combination thereof.

[0015] The plurality of measuring devices 111, 112, 113 are devices configured to produce measurement data. The measurement data can comprise analog and / or digital voltage measurements and / or analog and / or digital current measurements. The digital voltage and / or current measurement data can be output by the plurality of measuring devices 111, 112, 113 in various different formats. At least some of the different formats can be associated with different time constants (or equivalently different high pass cut-off frequencies).

[0016] The plurality of measuring devices 111, 112, 113 can comprise one or more devices of any of the following types: instrument transformers (IT), electronic instrument transformers (EIT), and low power instrument transformers (LPIT) (or other sensing devices). The LPIT (or the other transmitting devices) can comprise sensors (e.g., voltage sensors or current sensors). The plurality of measuring devices 111, 112, 113 can correspond to the main equipment in the switching devices of the system 100.

[0017] The plurality of measuring devices 111, 112, 113 (or at least some of them) can provide analog output signals to the merging unit 101.

[0018] Optionally, at least some of the plurality of measuring devices 111, 112, 113 can comprise built-in analog-to-digital converters and data formatting means for generating sampled measured value (SMV) signals. The SMV signals (or SMV messages) are digital signals comprising measurement data and having a predefined SV message format as defined in IEC 61850-9-2.

[0019] According to the basic function of the merging unit, the merging unit 101 is configured to receive current and / or voltage signals from the plurality of measuring devices 111, 112, 113, to merge the measured data into a standard digital output format, and to output at least one output signal having the standard digital output format to other devices (i.e., here to the network devices 121, 122). In order to implement the basic function as well as a filtering function according to embodiments, the merging unit 101 comprises a plurality of interfaces 102, digital processing means 103, and at least one memory 104.

[0020] The plurality of interfaces 102 comprises at least a plurality of input interfaces 105 and one or more output interfaces 106. The plurality of input interfaces 105 comprises a plurality of input interfaces for receiving input signals (e.g., analog input signals) from the plurality of measuring devices 111, 112, 113. The merging unit 101 and the plurality of measuring devices 111, 112, 113 can be connected specifically via one or more wired connections (e.g., one or more cables). The plurality of input interfaces 105 for receiving input signals from the plurality of measuring devices 111, 112, 113 can use the IEC 61850-8-1 GOOSE (generic object oriented substation event) profile.

[0021] In some embodiments, the one or more input interfaces 105 can further comprise at least one user interface for receiving user input provided by a user via at least one user input device (e.g., a keyboard, a mouse, a trackball, a set of dedicated buttons and / or control dials, a touchpad, and / or a touch screen) of the merging unit 101.

[0022] In some embodiments, at least one of the one or more input interfaces for receiving input signals from the plurality of measuring devices 111, 112, 113 corresponds to an analog-digital input interface configured to convert received analog input signals into digital input signals. In other words, the merging unit 101 can comprise an analog-digital conversion device (e.g., an analog-digital converter) for converting one or more analog input signals of the merging unit 101 into one or more (corresponding) digital input signals that can be processed (e.g., filtered and merged) by the digital processing device 103.

[0023] The one or more output interfaces 105 comprise at least one or more output interfaces for outputting one or more merged (digital) output signals (i.e., a homogeneously defined digital data stream created from the measurement data and having a standardized format) produced by the merging unit based on the input signals received via the plurality of input interfaces 105 to one or more network devices 121, 122. The output signals outputted via the one or more output interfaces 105 can have a predefined format. The predefined format can in particular be a format defined in a standard such as IEC 61850-9-2. The merging unit 101 and the one or more network devices 121, 122 can in particular be connected via one or more wired connections (e.g., one or more optical fiber connections and / or one or more electrical cables).

[0024] In some embodiments, the one or more interfaces 102 can further comprise one or more communication interfaces (as input / output interfaces) for enabling communication connectivity according to one or more communication protocols via one or more (wired and / or wireless) communication links and / or via one or more (wired and / or wireless) communication networks. In particular, the one or more communication interfaces 910 can comprise interfaces that provide, for example, a connection to the Internet and / or a core network of a wireless communication network. For example, the one or more communication interfaces 910 can provide the apparatus with communication capabilities to communicate in a cellular communication system and to enable communication between a user equipment (terminal device) and different network nodes or elements, and / or provide communication interfaces to enable communication between different network nodes or elements. The one or more communication interfaces can comprise standard well-known components (such as amplifiers, filters, frequency converters, (de-)modulators, and encoder / decoder circuits) controlled by a corresponding control unit, and one or more antennas.

[0025] In some embodiments, the one or more communication interfaces can comprise one or more (optical or electrical) Ethernet network interfaces.

[0026] The digital processing apparatus 103 can be configured to implement the functionality of the merging unit 101 according to the embodiments to be discussed in detail below. In summary, the digital processing apparatus can be at least configured to high-pass filter at least one of the plurality of input signals received via the one or more input interfaces 105 using one or more digital filters in order to reduce a time constant associated with said at least one of the one or more input signals to match a target time constant, or in order to raise a high-pass cutoff frequency associated with said one of the one or more input signals to match a target high-pass cutoff frequency, and to merge the one or more input signals into an output signal having a predefined output format after high-pass filtering. The digital processing apparatus 103 can comprise or correspond to digital processing circuitry.

[0027] The digital processing apparatus 103 can be communicatively connected to at least one memory 104. Alternatively, the digital processing apparatus 103 can comprise at least one memory 104 Figure 1 (not shown in Fig. 1).

[0028] Some example digital processing devices for performing processing according to embodiments can include at least one of the following: a detector, a processor (including dual-core and multi-core processors), a digital signal processor, a controller, a receiver, a transmitter, an encoder, a decoder, a memory, a RAM, a ROM, software, firmware, a display, a user interface, display circuitry, user interface circuitry, user interface software, display software, circuitry, an antenna, antenna circuitry, and circuitry.

[0029] In some embodiments, the digital processing device 103 can comprise, for example, one or more field-programmable gate arrays (FPGA) and / or one or more application-specific integrated circuits (ASIC). In some such embodiments, at least one of the one or more FPGA and / or one or more ASIC can be specifically configured to implement filtering functionality according to embodiments.

[0030] In some embodiments, the digital processing device 103 can comprise at least one processor (e.g., a microprocessor and / or a digital signal processor). Furthermore, the at least one memory 104 can comprise one or more algorithms, for example, computer program code (software). The at least one memory 104 and the computer program code can be configured to, together with the at least one processor 103, cause the execution of the digital processing device 103 (or the merging unit 101) according to embodiments. The at least one memory 104 can also comprise at least one database.

[0031] The at least one memory 104 can be implemented using any suitable data storage technology, such as semiconductor-based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, fixed memory, and removable memory.

[0032] The at least one memory 104 can store (current) values of the target time constant and / or the target high-pass cutoff frequency. Additionally or alternatively, the at least one memory 104 can store filter settings of one or more digital filters used in embodiments.

[0033] In some embodiments, the at least one memory 104 can store a look-up table. In particular, the look-up table can define a plurality of sets of filter settings for one or more digital filters (usable by the digital processing device 103 of the merging unit 101) for implementing a plurality of target time constants and / or target high-pass cutoff frequencies. To provide a more specific non-limiting example, the look-up table can define a set of filters for processing a cutoff frequency from 0.0 Hz to 1.0 Hz in frequency steps of 0.1 Hz or 0.05 Hz, for example. In case of a non-linear input with a 0.5 Hz cutoff frequency, for example, its inverse filter is the same in each case, only the frequencies between 0.5 Hz and 1.0 Hz need to have a look-up table of filter parameters.

[0034] In addition to or as an alternative to the look-up table, a filter design algorithm can be maintained in the at least one memory. The filter design algorithm can be configured to output a set of filter settings based on an input of a target time constant or a target high-pass cutoff frequency.

[0035] As mentioned above, the one or more output signals output via the one or more output interfaces 105 can be fed to one or more network devices 121, 122 (two network devices in the illustrated example), in particular. The one or more network devices 121, 122 are typically (computing) devices that support network operation. The plurality of network devices 121, 122 can be equally referred to as SMV subscribers. The one or more network devices 121, 122 can comprise one or more devices of any of the following types: protection (or protective) devices, power quality devices, and (power) measurement and / or metering devices other than power quality devices.

[0036] The merging unit 101 can be a built-in merging unit of a instrument transformer as defined in IEC 61869, for example, or a stand-alone merging unit (SAMU) as defined in IEC 61869-13, for example.

[0037] It should be noted that, Figure 1 A simplified view of the system 100, and in particular of the merging unit 101 therein, is presented. The system 100 and the merging unit 101 can comprise one or more further elements as common in substation protection and metering systems, substation automation systems, or power systems and / or merging units. For example, the merging unit can comprise a synchronization device (e.g., an integrated clock or a synchronization-enabled interface) for synchronizing the input signals received thereby and a power supply device. Synchronization can employ the IEEE 1588 standard, for example. In some embodiments, the merging unit 101 can comprise a built-in secondary converter or both a built-in primary converter and a built-in secondary converter.

[0038] Figure 2 A process for performing filtering and merging of measured input data according to an embodiment is shown. The process can be performed by Figure 1 the merging unit 101 or a part thereof (i.e. at least by the digital processing device 103). In the following, the entity performing the process is referred to as merging unit, just for simplifying the description.

[0039] Initially, in block 201, the merging unit receives, via one or more input interfaces of the merging unit, a plurality of input signals characterizing one or more voltages and / or one or more currents measured by a plurality of measuring devices of a substation automation system. As discussed in connection with Figure 1 the merging unit 101, the one or more input interfaces can specifically comprise a plurality of input interfaces for connecting to the plurality of measuring devices. Additionally or alternatively, the plurality of input signals can comprise one or more or more signals characterizing currents (i.e. input current signals).

[0040] In some embodiments, each or at least one of the plurality of input signals received from the plurality of measuring devices can specifically be an analog input signal. In such embodiments, the receiving in block 201 further comprises converting the received plurality of analog input signals into a plurality of digital input signals. The following steps of the process are then performed on the plurality of digital input signals.

[0041] In block 202, the merging unit high-pass filters at least one of the plurality of input signals using one or more digital filters for reducing a time constant associated with the at least one of the one or more input signals to match a target time constant, or for increasing a high-pass cutoff frequency associated with the one of the one or more input signals (as an effectively equivalent operation to reducing the time constant) to match a target high-pass cutoff frequency. In other words, the merging unit effectively degrades the frequency response of some input signals in order to form a set of modified input signals: where all input signals (or at least all current input signals) have the same frequency behavior and are thus compatible with each other. This can be beneficial, for example, in view of the implementation of a SMV-based differential protection scheme. It should be noted that the merging unit hardware can limit the minimum high-pass cutoff frequency, but not the maximum high-pass cutoff frequency to implement the operation mentioned before.

[0042] The target time constant or target high-pass cut-off frequency can be predefined. In other words, the value of the target time constant or target high-pass cut-off frequency can be stored in a memory of the merging unit. The target time constant or target high-pass cut-off frequency can be a (adjustable) setting of the merging unit. If the merging unit is a built-in merging unit of a instrument transformer, e.g. as defined in IEC 61869, such (adjustable) setting of the merging unit can specifically control the frequency response of the primary and secondary transducers of the merging unit. If the merging unit is a standalone merging unit, e.g. as defined in IEC 61869-13, such (adjustable) setting of the merging unit can specifically control the frequency response of the current input of the standalone merging unit. For a detailed description of the adjustment operation see the discussion in connection with Figure 2

[0043] In some embodiments, the at least one of the plurality of input signals comprises or consists of one or more current signals (or specifically one or more analog current signals). In other words, the filtering in block 202 can specifically apply to any current input signal received in block 201. Additionally or alternatively, the at least one of the plurality of input signals can comprise or consist of one or more voltage signals (or one or more analog voltage signals).

[0044] In some embodiments, the merging unit can specifically select the at least one of the plurality of input signals to be a (current) signal whose time constant fails to exceed the target time constant or whose high-pass cut-off frequency falls below the target high-pass cut-off frequency.

[0045] The one or more digital filters can be such that they mimic the behavior of an analog current transformer. Such behavior corresponds to a first order analog high-pass RC filter in the analog domain, while in the digital domain it can be implemented using an infinite impulse response (IIR) filter. The sampling frequency used in the digital filtering can for example be equivalent to the output of an analog-to-digital converter (ADC) of the merging unit and / or of the measuring device. In practice, the IIR filter can be a high-pass filter with the target time constant or high-pass cut-off frequency (if the input hardware frequency response does not exhibit a high-pass behavior) or a combination of a high-pass filter with the target time constant or high-pass cut-off frequency and an inverse filter (inverse of the input hardware frequency response), which will be described in more detail below.

[0046] The filter settings of the one or more digital filters can be determined based on at least one of the one or more input signals and a look-up table or a filter design algorithm held in a memory of the merging unit. As discussed in connection with​Figure 1 As described, the lookup table can define a plurality of sets of filter settings for implementing one or more digital filters for achieving a plurality of target time constants and / or target high-pass cutoff frequencies, and / or the filter design algorithm can be configured to output a set of filter settings based on an input of a target time constant or a target high-pass cutoff frequency.

[0047] The target time constant and / or target high-pass cutoff frequency can be defined by a user input (prior to high-pass filtering). The user input can be received via a user input interface providing a connection to at least one user input device of the merging unit or via a communication interface providing a connection over one or more (wired and / or wireless) communication links and / or networks.

[0048] In block 203, the merging unit merges the plurality of input signals into an output signal having a predefined output format. It should be emphasized that the merging in block 203 is performed after high-pass filtering, i.e. the merging in block 203 is performed for a plurality of (digital) input signals including at least one high-pass filtered signal. The predefined format of the output signal can be a standard-based format, e.g. a format defined in IEC 61850-9-2 for the output of a merging unit.

[0049] Finally, in block 204, the merging unit outputs the output signal via one or more output interfaces. The output signal can be output in particular to a network device (e.g. a protection device). In other embodiments, a plurality of (identical) output signals can be output to a plurality of network devices.

[0050] As described above, the merging unit can keep information about the values of the target time constant and / or target high-pass cutoff frequency in a memory of the merging unit. It would be beneficial if the values can be changed by a user, i.e. it would be defined as a user-defined setting of the merging unit. Figure 2 A process for implementing such a functionality according to an embodiment is shown. The process can be performed by Figure 1 the merging unit 101 or a part thereof (i.e. at least by the digital processing device 103) of the merging unit 101. In the following, the entity performing the process is referred to as merging unit, just to simplify the description.

[0051] Initially, in block 301, it is assumed that the merging unit holds information about a target time constant and / or a target high-pass cutoff frequency in at least one memory. Additionally or alternatively, the merging unit can hold information about filter settings of one or more digital filters (or some of them) used to implement the target time constant and / or the target high-pass cutoff frequency in said at least one memory. As mentioned above, the one or more digital filters can specifically comprise an IIR filter. Filter settings of a given IIR digital filter can comprise, for example, feed-forward filter coefficients, feedback filter coefficients, a feed-forward filter order, and / or a feedback filter order.

[0052] In block 302, the merging unit receives a user input (or a signal comprising information about a user input) via a user input interface or a communication interface of the merging unit. As discussed in connection with Figure 1 the merging unit can comprise at least one user input interface for receiving input provided by a user via at least one user input device of the merging unit (or connected to the merging unit) and / or at least one communication interface for receiving signals over at least one communication link and / or network.

[0053] In some embodiments, the merging unit can check whether the value of the target time constant and / or the target high-pass cutoff frequency received in block 302 is different from the corresponding value held in said at least one memory, and only further continue in this process in case the received value is a new value not held in said at least one memory.

[0054] In response to the reception in block 302, the merging unit stores the received value of the target time constant or the target high-pass cutoff frequency to said at least one memory in block 303. In other words, the merging unit updates the current value of the target time constant or the target high-pass cutoff frequency held in said at least one memory to match the received (user-defined) value.

[0055] Additionally, in block 304, the merging unit adjusts filter settings of the one or more digital filters (or some of them) based on the target time constant or the target high-pass cutoff frequency defined by the user input. The adjustment in block 304 can be performed in response to the reception in block 302 or subsequently, for example, in response to receiving an input signal for merging that needs to be filtered (as discussed in connection with Figure 1 Specifically, filter properties of a high-pass digital (IIR) filter defined in terms of the target time constant and / or the target high-pass cutoff frequency can be adjusted in block 304 (see discussion in connection with Figure 4 As also described above, the adjustment can be performed based on a lookup table or a filter design algorithm held in said at least one memory.

[0056] Figure 4 Another more detailed process for performing filtering and merging of measured input data is shown, in accordance with an embodiment. The process can be performed by the merging unit 101 or a part thereof (i.e. at least by the digital processing device 103). Any feature discussed in connection with Figure 1 may be applied to the process of Figure 2 . In the following, the entity performing the process is referred to as the merging unit, merely for simplifying the description. Figure 4 The process of Figure 3 may be preceded by the process of Figure 4 . The process of

[0057] Referring to Figure 4 , the block 401 can fully correspond to the block 201 of Figure 2 . After the reception in the block 401, the operation of the merging unit depends on the current operating mode (or current operating settings) of the merging unit. Two different operating modes can be defined for filtering different types of input signals, e.g. as follows: a first operating mode can be used for filtering input signals which do not exhibit a high-pass behavior, while a second operating mode can be used for filtering input signals which exhibit a high-pass behavior which fails to meet a target time constant or a target high-pass cutoff frequency. Information about the current operating mode can be held in at least one memory of the merging unit. The operating mode can be a setting of the merging unit which can be set by a user (e.g. via a user input interface or remotely via a communication interface). The setting of the operating mode can be performed in a similar or analogous manner as discussed in connection with Figure 3 for setting a target time constant and / or a target high-pass cutoff frequency for a plurality of input signals (although, obviously, Figure 3 the block 304 of is not applicable in this case). It should be noted that the high-pass behavior of an input signal can not only depend on the input signal itself, but also on the high-pass properties of a given (analog) input interface of the merging unit.

[0058] In the block 402, if the merging unit is currently configured to operate using the first operating mode for filtering input signals which do not exhibit a high-pass behavior (i.e. which correspond to a shunt input), then in the block 403 the merging unit applies a high-pass digital (IIR) filter to the input signal which matches the target time constant and / or the target high-pass cutoff frequency. The filter settings of the high-pass digital (IIR) filter can be previously determined and can be held in at least one memory of the merging unit. Thus, the input signal in question is modified to correspond to the target time constant and / or the target high-pass cutoff frequency. The target time constant and / or the target high-pass cutoff frequency can be defined as discussed in connection with Figure 1 .

[0059] If, in block 402, the merging unit is currently configured to operate using the second operating mode to filter the input signal which exhibits a high-pass behavior which fails to meet the target time constant or the target high-pass cutoff frequency, then, in block 404, the merging unit applies, successively (i.e. one after the other) to the input signal, an inverse digital (IIR) filter and a high-pass digital filter which matches the target time constant and / or the target high-pass cutoff frequency. The inverse digital filter signal can be defined as an inverse filter (i.e. an inverse filter for the frequency response of the input signal) which corresponds to the (assumed) high-pass behavior for the input signal.

[0060] Alternatively, in block 404, the merging unit can apply to the input signal a digital (IIR) filter which corresponds (e.g. is derived as a product of the frequency responses of the inverse digital filter and the high-pass digital filter) to the combination of the inverse digital filter and the high-pass digital filter. Obviously, after block 404, the input signal has the same form in both cases. In either case, the input signal in question is modified to increase the high-pass cutoff frequency (or equivalently to lower the time constant).

[0061] Although not shown in Figure 4 for the sake of simplicity of representation, the merging unit obviously can also have a third operating mode in which no filtering is performed on the input signal.

[0062] Once the input signal has been filtered in block 403 or block 404, the merging unit checks, in block 405, whether all of the plurality of input signals have been covered (i.e. whether the processing of blocks 402 to 404 has been performed for all input signals). If this is not the case, then, in block 408, the merging unit selects the next input signal of the plurality of input signals for analysis and possible filtering and repeats the actions related to blocks 402, 403, 405 or blocks 402, 404, 405. If all of the plurality of input signals have been covered in block 405, the merging unit proceeds to blocks 406, 407. Said blocks 406, 407 can fully correspond to blocks 204, 205 of Figure 2 .

[0063] In some embodiments, the actions related to blocks 402 to 408 can be performed only for one or more current input signals of the plurality of input signals received in block 401.

[0064] In some alternative embodiments, only one of the first operating mode and the second operating mode can be defined.

[0065] The above is summarized by Figures 2 to 4The described blocks, related functions, and information exchanges do not have to be implemented in the given order and some of the blocks can be implemented in parallel or in a different order. Other functions can also be carried out between or within the blocks and other information can be sent and / or other rules can be applied. Some of the blocks or parts of blocks or one or more pieces of information can also be omitted or replaced by corresponding blocks or parts of blocks or one or more pieces of information.

[0066] The described embodiments can also be carried out in the form of a computer process defined by a computer program or a piece of a computer program. The program can be stored in a computer program distribution medium readable by a computer or a processor. The computer program medium can be, for example but not limited to, a record medium, computer memory, read-only memory, electrical carrier signal, telecommunications signal, and software distribution package, for example. The computer program medium can be non-transitory. Coding the software for Figures 2 to 4 Embodiments of the described methods can be implemented by executing at least part of a computer program comprising corresponding instructions. The computer program can be provided as a computer program distribution medium having stored thereon the program instructions. The computer program medium can be, for example but not limited to, a record medium, computer memory, read-only memory, electrical carrier signal, telecommunications signal, and software distribution package, for example. The computer program medium can be non-transitory. Coding the software for execution on a computer or processor can be a procedure that is well within the ordinary skills of a person knowledgeable in the art. The software essentially may, and usually does, include machine code or some other form of code or instructions generated by a compiler.

[0067] Although embodiments have been described above with reference to examples according to the accompanying drawings, it is clear that the embodiments are not limited to them but can be modified in several ways within the scope of the appended claims. Therefore, all words and expressions should be interpreted broadly and they are intended to illustrate, not to restrict, the embodiment. It will be obvious to a person skilled in the art that, as technology advances, the inventive concept can be implemented in various ways. Further, it will be apparent that the described embodiments can be combined with other embodiments in various ways.

Claims

1. A merging unit, comprising: one or more input interfaces for receiving a plurality of input signals characterizing one or more voltages and / or one or more currents measured by a plurality of measuring devices; a digital processing device for: high-pass filtering at least one input signal of the plurality of input signals using one or more digital filters for reducing a time constant associated with the at least one input signal of the plurality of input signals to match a target time constant or for increasing a high-pass cutoff frequency associated with the at least one input signal of the plurality of input signals to match a target high-pass cutoff frequency, and merging the plurality of input signals into an output signal having a predefined output format after the high-pass filtering; and one or more output interfaces for outputting the output signal, wherein the digital processing device is configured to perform the high-pass filtering for each input signal of the plurality of input signals by: applying a high-pass digital filter matching the target time constant and / or the target high-pass cutoff frequency to the input signal if the merging unit is currently configured to operate using a first operating mode for filtering input signals not exhibiting a high-pass behavior; and applying an inverse digital filter and a high-pass digital filter matching the target time constant and / or the target high-pass cutoff frequency to the input signal successively or applying a digital filter corresponding to a combination of the inverse digital filter and the high-pass digital filter to the input signal if the merging unit is currently configured to operate using a second operating mode for filtering input signals exhibiting a high-pass behavior failing to meet the target time constant or the target high-pass cutoff frequency. The at least one input signal of the plurality of input signals comprises or consists of one or more current signals.

2. The merge unit of claim 1, wherein, The digital processing device is further configured to select the at least one input signal of the plurality of input signals as a signal associated with a time constant failing to exceed the target time constant or a high-pass cutoff frequency falling below the target high-pass cutoff frequency.

3. The merging cell of claim 1 or 2, wherein, The digital processing device is further configured to:

4. The merge unit of claim 1, wherein, hold information about the target time constant and / or the target high-pass cutoff frequency and / or information about filter settings of the one or more digital filters used for implementing the target time constant and / or the target high-pass cutoff frequency in at least one memory.

5. The merging unit according to claim 1, further comprising: at least one user input interface for receiving a user input defining the target time constant and / or the target high-pass cutoff frequency for the plurality of input signals via at least one user input device; and / or ​ at least one communication interface for receiving a signal defining a user input via a communication link or network, the user input defining the target time constant and / or the target high-pass cutoff frequency for the plurality of input signals, wherein the digital processing device is further configured to: store a value of the target time constant or the target high-pass cutoff frequency received to the at least one memory in response to receiving a user input defining the target time constant or the target high-pass cutoff frequency via the at least one user input interface or the at least one communication interface; and adjust a filter setting of at least one of the one or more digital filters based on the target time constant or the target high-pass cutoff frequency defined by the user input.

6. The merge unit of claim 5, wherein, The digital processing device is further configured to: maintain a lookup table in the at least one memory, the lookup table defining a plurality of sets of filter settings for the one or more digital filters implementing a plurality of target time constants and / or target high-pass cutoff frequencies; and perform the adjustment of the filter setting of the at least one of the one or more digital filters based on the lookup table.

7. The merge unit of claim 1, wherein, The one or more input interfaces or a portion thereof comprise an analog-to-digital input interface for converting a received analog input signal into a digital input signal.

8. The merge unit of claim 1, wherein, The plurality of input signals are analog input signals, the merging unit further comprising: an analog-to-digital conversion device for converting the plurality of input signals into digital signals for processing by the digital processing device.

9. The merge unit of claim 1, wherein, The one or more digital filters are infinite impulse response filters.

10. The merge unit of claim 1, wherein, The predefined output format of the output signal is a standard-based format based on IEC 61850-9-2.

11. The merge unit of claim 1, wherein, The digital processing device comprises one or more field programmable gate arrays, FPGAs, and / or one or more application specific integrated circuits, ASICs.

12. The merge unit of claim 1, wherein, The digital processing device comprises: at least one processor; and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the performance of the digital processing device.

13. A merging method, comprising: receiving a plurality of input signals representing one or more voltages and / or one or more currents measured by a plurality of measuring devices; high-pass filtering at least one of the plurality of input signals using one or more digital filters for reducing a time constant associated with the at least one of the plurality of input signals to match a target time constant or for increasing a high-pass cutoff frequency associated with the at least one of the plurality of input signals to match a target high-pass cutoff frequency; merging the plurality of input signals into an output signal having a predefined output format after the high-pass filtering; and outputting the output signal, wherein the high-pass filtering is performed for each of the plurality of input signals by: if operating using a first operating mode to filter an input signal that does not exhibit a high-pass behavior, applying a high-pass digital filter matching the target time constant and / or the target high-pass cutoff frequency to the input signal; and if operating using a second operating mode to filter an input signal that exhibits a high-pass behavior that fails to meet the target time constant or the target high-pass cutoff frequency, applying an inverse digital filter and a high-pass digital filter matching the target time constant and / or the target high-pass cutoff frequency successively to the input signal, or applying a digital filter corresponding to a combination of the inverse digital filter and the high-pass digital filter to the input signal.

14. A computer-readable medium comprising program instructions which, when executed by an apparatus, cause the apparatus to perform at least the following: receiving a plurality of input signals characterizing one or more voltages and / or one or more currents measured by a plurality of measurement devices; high-pass filtering at least one input signal of the plurality of input signals using one or more digital filters for reducing a time constant associated with the at least one input signal of the plurality of input signals to match a target time constant or for increasing a high-pass cutoff frequency associated with the at least one input signal of the plurality of input signals to match a target high-pass cutoff frequency; after the high-pass filtering, merging the plurality of input signals into an output signal having a predefined output format; and outputting the output signal, wherein the program instructions, when executed by the apparatus, further cause the apparatus to perform the high-pass filtering for each input signal of the plurality of input signals by: if the apparatus is currently configured to operate using a first operating mode to filter an input signal that does not exhibit a high-pass behavior, applying a high-pass digital filter matching the target time constant and / or the target high-pass cutoff frequency to the input signal; and if the apparatus is currently configured to operate using a second operating mode to filter an input signal that exhibits a high-pass behavior that fails to meet the target time constant or the target high-pass cutoff frequency, applying an inverse digital filter and a high-pass digital filter matching the target time constant and / or the target high-pass cutoff frequency successively to the input signal, or applying a digital filter corresponding to a combination of the inverse digital filter and the high-pass digital filter to the input signal.

Images