An IJTAG-based Automotive SoC Monitoring System and Monitoring Method

Abstract

The present invention discloses an IJTAG-based automotive SoC monitoring system, which includes a target health monitoring processor; the target health monitoring processor is connected to an IJTAG network interface through voltage detection EI and delay detection EI. The voltage detection EI is connected to the target health monitoring processor to detect the local voltage inside it in real time, and the delay detection EI is connected to the target health monitoring processor to detect the critical path delay and the highest frequency inside it. It also discloses a detection method for an IJTAG-based automotive SoC monitoring system, including entering the health monitoring mode, monitoring all target operating voltages and delays to ensure good target health status and normal life prediction. The present invention embeds voltage detection EI and delay detection EI through the IJTAG network interface to perform online monitoring and prediction on automotive SoC chips, improving the reliability and stability of automotive SoC chips in use; the settings of voltage detection EI and delay detection EI further improve the accuracy of monitoring data.

Description

Technical Field

[0001] The present invention belongs to the technical field of automotive electronic chip design, and in particular relates to an IJTAG-based automotive SoC monitoring system and a monitoring method. Background Art

[0002] At present, with the reduction of the chip size at the low nanometer (10 - 28 nm) level, the use of multi-processor cores in current automotive SoCs (system-on-a-chip) has been increasingly widespread, and each processor core can be used as a microcontroller unit (MCU). However, the reliability of these automotive SoC chips is significantly decreasing, especially under harsh operating conditions. For example, inside an automobile, wheel sensors and controllers must withstand a working ambient temperature of about 200 °C. At the same time, these harsh conditions exacerbate the aging mechanisms of semiconductors, such as negative bias temperature instability (NBTI), electromigration (EM), hot carrier injection (HCI), etc. Therefore, in order to ensure high reliability throughout the operating cycle of the automotive SoC, such as zero-fault operation time, real-time health monitoring of the target SoC must be carried out. By extracting the aging information from the monitored health status parameters, it provides a basis for the life prediction and health management of the target SoC, so as to carry out fault warning and replacement maintenance in advance.

[0003] The existing automotive SoC chips improve reliability based on design for testability (DFT), including off-line testing or on-line testing. However, off-line testing cannot process and alarm faults in real time; while most on-line detections require additional measurement circuits, greatly increasing the system cost. Secondly, embedded instrument (EI) circuits have been implemented a long time ago. For example, ring oscillators (ROs) are often embedded inside the chip and used as different design process evaluation modules to ensure error-free processing technology. Also, for example, temperature sensors are used as EIs functionally to track the working temperature of different regions of the SoC chip. However, many existing EI designs have a large area, including the use of additional design circuits (ADCs, comparators, etc.), which increases the overall chip design cost and has a limited number of uses inside each chip. Summary of the Invention

[0004] Object of the Invention: The present invention aims to provide an IJTAG-based automotive SoC monitoring system with high reliability and accurate monitoring; another object of the present invention aims to provide an IJTAG-based automotive SoC monitoring method.

[0005] Technical solution: The IJTAG-based automotive SoC monitoring system described in the present invention includes a target health monitoring processor; the target health monitoring processor is connected to the IJTAG network interface through voltage detection EI and delay detection EI. The voltage detection EI is connected to the target health monitoring processor to detect the local voltage inside it in real time, and the delay detection EI is connected to the target health monitoring processor to detect the critical path delay and the highest frequency inside it; the IJTAG network interface is connected to the AI data processor to transfer data and commands between the AI data processor, the voltage detection EI, and the delay detection EI; the voltage detection EI and the delay detection EI share the voltage supply of the target health monitoring processor and the network supply of the IJTAG network interface through the connection.

[0006] Among them, the target health monitoring processor includes a start trigger, a critical path CP, and a probe trigger; the voltage detection EI collects the input clock signals of the start trigger and the probe trigger, the delay detection EI collects the input clock signals of the start trigger and the probe trigger, and also receives the data signal by connecting to the end of the critical path CP; the target health monitoring processor includes a health monitoring mode and a normal user mode.

[0007] Among them, the voltage detection EI includes a first JTAG interface, a first JTAG peripheral circuit, a first electronic switch SW1, a second electronic switch SW2, a third electronic switch SW3, a first switch mixer SM1, a second switch mixer SM2, a multiplier, a programmable operational amplifier, a comparator, and a detector; the voltage detection EI is connected to the target health monitoring processor through the first electronic switch SW1, the second electronic switch SW2, and the third electronic switch SW3 to monitor the voltage levels DUT_input and DUT_output, and detects, compares, and evaluates the supply static voltage VDD of the critical path CP through the multiplier, the programmable operational amplifier, the comparator, and the detector. For the detected result voltage signal value β, the AI data processor reads it through the IJTAG network interface connected to the first JTAG interface and the first JTAG peripheral circuit.

[0008] Among them, the voltage detection range of the voltage detection EI is 0.85V to 1.25V, and the detection accuracy is 100μV.

[0009] Among them, the delay detection EI includes a second JTAG interface, a second JTAG peripheral circuit, a controller, a time-to-digital conversion circuit TDC, a first latch Stage-1, and a second latch Stage-2; the delay detection EI further includes a DATA interface, a CLK interface, and a RESET interface; the data signal is input through the DATA interface connected to the end of the critical path CP, the CLK interface is used to capture the clock signals input by the start trigger and the detection trigger on the critical path CP, and the RESET interface is used to receive the system reset signal.

[0010] Among them, the total area of the delay monitoring EI is 39.12μm * 206.9μm; among them, the area of the time-to-digital conversion circuit TDC is 12μm * 103.5μm, and the area of the controller is 27.12μm * 103.4μm.

[0011] A monitoring method for an automotive SoC monitoring system based on IJTAG at least includes the following steps:

[0012] Step 1: Power on the target health monitoring processor SoC chip to the target operating voltage VDD, and the target health monitoring processor enters the health monitoring mode.

[0013] Step 2: The AI data processor issues a command to perform health monitoring on the target health monitoring processor and all EIs.

[0014] Step 3: The AI data processor obtains and stores all EI health monitoring data through the IJTAG network interface.

[0015] Step 4: The AI data processor issues an estimate of the health status and a life prediction of the target health monitoring processor. If the target health status is good and the life prediction is normal, the target health monitoring processor boots up normally and enters the user mode; otherwise, it notifies to replace the target processor.

[0016] Among them, the evaluation of the good target health status and normal life prediction is determined by the digital voltage signal value β and the threshold of the critical path CP delay. The voltage and the critical path CP delay in the target health state are 90% of the threshold.

[0017] Among them, the detection of the digital voltage signal value β at least includes the following steps:

[0018] Step 1: The voltage detection EI is connected to the target health monitoring processor to monitor the voltage bits DUT_input and DUT_output through the first electronic switch SW1, the second electronic switch SW2, and the third electronic switch SW3, and the first switch mixer SM1 and the first switch mixer SM2 are reset to zero.

[0019] Step 2: Based on the binary search method, program and compare at least 10-digit digital voltage signal values β, starting from the minimum value until the detection trigger is reversed. At this time, the digital voltage signal value β is the measured voltage value;

[0020] Step 3: If no digital voltage signal value β that can reverse the detection trigger is detected, set the 10-digit digital voltage signal value β to a negative value and start the comparison and determination again; the determined digital voltage signal value β is stored in the register of the AI data processor.

[0021] Among them, the critical path CP delay monitoring includes the following steps:

[0022] Step 1: The delay monitor El enters the monitoring mode, and MODE_OFF is set to "1";

[0023] Step 2: The controller module sets a window of 256 clock cycles to capture the first change of the data signal, and the MUX uses the captured DATA signal as the input of the "delay line";

[0024] Step 3: Capture the data signal at the positive edge of each CLK through the first latch Stage-1. The 32-bit output Q[31:0] of the first latch Stage 1 will be transmitted to the controller module, and this module determines whether any data change has occurred;

[0025] Step 4: If a change occurs, the controller module will generate a capture signal to the second latch Stage-2, and this latch captures the same content as the first latch Stage-1; if no change occurs, the controller module will generate a capture signal at the end of the 256-clock-cycle window, and the measurement of the delay time is obtained through the 32-bit output OUT[31:0] of Stage-2.

[0026] Beneficial effects: Compared with the prior art, the present invention has the following remarkable improvements:

[0027] (1) The present invention monitors the health of the target health monitoring processor through voltage monitoring EI and delay detection EI, replaces aging or faulty specific processors before the occurrence of automotive SoC failures, thereby avoiding catastrophic failures caused by aging; among them, the power supply and network supply of voltage monitoring EI and delay detection EI come from health monitoring and the IJTAG network interface, reducing the power consumption of the system and the area of the chip; increasing the number of voltage monitoring EI and delay detection EI that can be embedded and integrated in the target health monitoring processor, improving the data acquisition volume, establishing a data processing model through the big data AI data processor, and increasing the accuracy and precision of monitoring.

[0028] (2) The target health monitoring processor conducts data interaction with the AI data processor through the IJTAG network interface to achieve the purpose of real-time monitoring. The target health monitoring processor includes a normal user mode and a health monitoring mode, which avoids the system crash situation during the use of the SoC chip and improves the reliability of the system. Secondly, by setting thresholds, the health status is predicted to ensure that maintenance of the system is reduced before a fault occurs, further improving the reliability and stability of the entire automotive electronic system. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the overall structure of the present invention;

[0030] Figure 2 It is a voltage monitoring EI design architecture diagram of the present invention;

[0031] Figure 3 It is a delay monitoring EI design architecture diagram of the present invention;

[0032] Figure 4 It is a verification GDS diagram of the voltage monitoring EI and the delay monitoring EI of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] As Figure 1 shown, the IJTAG-based automotive SoC monitoring system in the present invention, the IJTAG-based automotive SoC monitoring system includes a target health monitoring processor; the target health monitoring processor is connected to the IJTAG network interface through a voltage detection EI and a delay detection EI. The voltage detection EI is connected to the target health monitoring processor for real-time detection of the local voltage inside it, and the delay detection EI is connected to the target health monitoring processor for detecting the critical path delay and the highest frequency inside it; the IJTAG network interface is connected to the AI data processor for transmitting data and commands between the AI data processor and the voltage detection EI and the delay detection EI; the voltage detection EI and the delay detection EI share the voltage supply of the target health monitoring processor and the network supply of the IJTAG network interface through connections. The target health monitoring processor includes a start trigger, a critical path CP, and a probe trigger. The start trigger transmits the data signal to the probe trigger through the critical path CP; the voltage detection EI collects the input clock signals of the start trigger and the probe trigger, the delay detection EI collects the input clock signals of the start trigger and the probe trigger, and also receives the data signal by connecting to the end of the critical path CP; the target health monitoring processor includes a health monitoring mode and a normal user mode.

[0034] As Figure 2As shown, the voltage detection EI includes a first JTAG interface, a first JTAG peripheral circuit, a first electronic switch SW1, a second electronic switch SW2, a third electronic switch SW3, a first switched mixer SM1, a second switched mixer SM2, a multiplier, a programmable operational amplifier, a comparator, and a detector; the voltage detection EI is connected to the target health monitoring processor to monitor the voltage levels DUT_input and DUT_output through the first electronic switch SW1, the second electronic switch SW2, and the third electronic switch SW3, and detects, compares, and evaluates the supply static voltage VDD of the critical path CP through the multiplier, the programmable operational amplifier, the comparator, and the detector. For the detected result voltage signal value β, the AI data processor reads it through the IJTAG network interface connected to the first JTAG interface and the first JTAG peripheral circuit. The voltage detection range of the voltage detection EI is 0.85V to 1.25V, and the detection accuracy is 100μV.

[0035] As Figure 3 shown, the delay detection EI includes a second JTAG interface, a second JTAG peripheral circuit, a controller, a time-to-digital conversion circuit TDC, a first latch Stage-1, and a second latch Stage-2; the delay detection EI also includes a DATA interface, a CLK interface, and a RESET interface; the data signal is input through the DATA interface connected to the end of the critical path CP, the CLK interface is used to capture the clock signals input by the start trigger and the probe trigger on the critical path CP, and the RESET interface is used to receive the system reset signal.

[0036] As Figure 4 shown, the total area of the delay monitoring EI is 39.12μm * 206.9μm; among them, the area of the time-to-digital conversion circuit TDC is 12μm * 103.5μm, and the area of the controller is 27.12μm * 103.4μm.

[0037] The monitoring method of the IJTAG-based automotive SoC monitoring system includes at least the following steps: the target health monitoring processor SoC chip is powered on with the target operating voltage VDD, and the target health monitoring processor enters the health monitoring mode; the AI data processor issues commands to perform health monitoring on the target health monitoring processor and all EIs; the AI data processor obtains and stores all EI health monitoring data through the IJTAG network interface; the AI data processor issues an estimate of the health status and a life prediction of the target health monitoring processor. If the target health status is good and the life prediction is normal, the target health monitoring processor boots up normally and enters the user mode, otherwise it notifies to replace the target processor.

[0038] The evaluation of good target health status and normal life prediction is determined by the digital voltage signal value β and the threshold of the critical path CP delay. The voltage and the critical path CP delay in the target health status are 90% of the threshold value.

[0039] Among them, the detection of the digital voltage signal value β includes at least the following steps:

[0040] The voltage monitor EI is divided into the original instrument and its IJTAG package part. The basic operation is based on the principle of successive approximation method, in which the voltage offset value to be monitored is compared with the voltage generated by a 10-bit digitally controlled programmable amplifier / comparator. The IJTAG network inside the SoC generates and processes a 10-bit digital voltage signal.

[0041] For the operation of the voltage monitor EI, first, the voltage monitor EI is connected to the positions of the target monitored voltages (DUT_input and DUT_output) through the first electronic switch SW1, the second electronic switch SW2, and the third electronic switch SW3. The first switch mixer SM1 and the second switch mixer SM2 are reset to zero. The programming of the 10-bit digital voltage signal value β is found based on a binary search method, starting from the minimum until the detection flip-flop can be inverted. At this time, the β value is the measured voltage value. If this value cannot be found, β is set to a negative value and the search process is restarted. Finally, the result β can be read and stored in the register of the AI data processor.

[0042] Among them, the critical path CP delay monitoring includes the following steps:

[0043] The delay monitor EI circuit includes a JTAG interface, a JTAG peripheral circuit, a controller, a time-to-digital conversion (TDC) circuit, a monitoring switch, such as Figure 3As shown. The delay monitoring EI is connected to the DATA input signal at the end of the monitored critical path, and the CLK is the input clock signal of the latch used to capture data changes on the critical path; the RESET signal is the system reset signal. The main idea of this design is to sample the DATA signal before the rising edge occurs at the clock edge. The delay monitoring El can be configured into three different operating modes, and the monitoring mode is the most important mode. At this time, MODE_OFF is set to "1"; in the monitoring mode, the controller module sets a window of 256 clock cycles to capture the first change of the DATA signal. This value is obtained through design trade-offs, which can balance the probability of DATA changes occurring and the waiting time for detecting DATA changes at the system level. Then, the MUX will select DATA as the input of the "delay line". The main purpose of the "delay line" is to set the observation window before the rising edge of the clock. In order to sample the DATA signal content in the "delay line", the first latch Stage-1 is used to capture the DATA signal at the positive edge of each CLK. The 32-bit output Q[31:0] of the first latch Stage-1 will be transmitted to the controller module, which determines whether any DATA changes have occurred. If a change occurs, the controller module will generate a capture signal to the second latch Stage-2, which captures the content of the first latch Stage-1. If no change occurs, the controller module will generate a capture signal at the end of the 256-clock-cycle window. The measurement of the delay time is obtained through the 32-bit output OUT[31:0] of the second latch Stage-2.

[0044] As Figure 4 shown, to verify the effect of the present invention, the layout of the delay detection EI is shown, where the TDC is implemented using an inverter with the minimum propagation delay in the TSMC standard cell library. The area of the TDC block is 12μm * 103.5μm, while the area of the control module is 27.12μm * 103.4μm. The total area of the proposed timing EI is 39.12μm * 206.9μm (or 0.008mm 2 ). Therefore, the delay monitoring EI can be easily integrated into multiple SoC processors, increasing the data acquisition volume and improving the monitoring accuracy and precision.

Claims

1. An IJTAG-based automotive SoC monitoring system, including a target health monitoring processor; characterized in that: The target health monitoring processor is connected to the IJTAG network interface through voltage detection EI and delay detection EI. The voltage detection EI is connected to the target health monitoring processor to detect the local voltage inside it in real time. The delay detection EI is connected to the target health monitoring processor to detect the critical path delay and the highest frequency inside it. The IJTAG network interface is connected to the AI data processor to transfer data and commands between the AI data processor, the voltage detection EI, and the delay detection EI. The voltage detection EI and the delay detection EI share the voltage supply of the target health monitoring processor and the network supply of the IJTAG network interface through connections. The voltage detection EI includes a first JTAG interface, a first JTAG peripheral circuit, a first electronic switch SW1, a second electronic switch SW2, a third electronic switch SW3, a first switch mixer SM1, a second switch mixer SM2, a multiplier, a programmable operational amplifier, a comparator, and a detector. The voltage detection EI is connected to the target health monitoring processor to monitor the voltage bits DUT_input and DUT_output through the first electronic switch SW1, the second electronic switch SW2, and the third electronic switch SW3. The static supply voltage VDD of the critical path CP is detected, compared, and evaluated through the multiplier, the programmable operational amplifier, the comparator, and the detector. For the detected result voltage signal value β, the AI data processor reads it through the IJTAG network interface connected to the first JTAG interface and the first JTAG peripheral circuit.

2. The automotive SoC monitoring system based on IJTAG according to claim 1, wherein The target health monitoring processor includes a start trigger, a critical path CP, and a probe trigger. The voltage detection EI collects the input clock signals of the start trigger and the probe trigger. The delay detection EI collects the input clock signals of the start trigger and the probe trigger and also receives the data signal by connecting to the end of the critical path CP. The target health monitoring processor includes a health monitoring mode and a normal user mode.

3. The automotive SoC monitoring system based on IJTAG according to claim 1, characterized in that, The voltage detection range of the voltage detection EI is 0.85V to 1.25V, and the detection accuracy is 100μV.

4. A vehicle SoC monitoring system based on IJTAG according to claim 1, characterized in that, The delay detection EI includes a second JTAG interface, a second JTAG peripheral circuit, a controller, a time-to-digital conversion circuit TDC, a first latch Stage-1, and a second latch Stage-2. The delay detection EI also includes a DATA interface, a CLK interface, and a RESET interface. The data signal is input through the DATA interface connected to the end of the critical path CP. The CLK interface is used to capture the clock signals input by the start trigger and the probe trigger on the critical path CP. The RESET interface is used to receive the system reset signal.

5. The automotive SoC monitoring system based on IJTAG according to claim 4, wherein The total area of the delay detection EI is 39.12μm * 206.9μm. Among them, the area of the time-to-digital conversion circuit TDC is 12μm * 103.5μm, and the area of the controller is 27.12μm * 103.4μm.

6. The monitoring method of the IJTAG-based automotive SoC monitoring system according to any one of claims 1 to 5, characterized in that, At least include the following steps: Step 1: Power on the target working voltage VDD of the target health monitoring processor SoC chip, and the target health monitoring processor enters the health monitoring mode; Step 2: The AI data processor issues a command to perform health monitoring on the target health monitoring processor and all EIs; Step 3: The AI data processor obtains and stores all EI health monitoring data through the IJTAG network interface; Step 4: The AI data processor issues an estimate of the health status and life prediction of the target health monitoring processor. If the target health status is good and the life prediction is normal, the target health monitoring processor boots up normally and enters the user mode. Otherwise, it notifies to replace the target processor.

7. The monitoring method of the IJTAG-based automotive SoC monitoring system according to claim 6, characterized in that, The evaluation of the target health status being good and the life prediction being normal is determined by the digital voltage signal value β and the threshold of the critical path CP delay. The voltage and the critical path CP delay in the target health status are 90% of the threshold.

8. The monitoring method of the IJTAG-based automotive SoC monitoring system according to claim 7, characterized in that The detection of the digital voltage signal value β at least includes the following steps: Step 1: The voltage detection EI is connected to the target health monitoring processor to monitor the voltage bits DUT_input and DUT_output through the first electronic switch SW1, the second electronic switch SW2, and the third electronic switch SW3. The first switch mixer SM1 and the second switch mixer SM2 are reset to zero; Step 2: Based on the binary search method, the digital voltage signal value β of at least 10 bits is programmed and compared, starting from the minimum value until the detection flip-flop is inverted. At this time, the digital voltage signal value β is the measured voltage value; Step 3: If the digital voltage signal value β that causes the detection flip-flop to invert cannot be detected, the 10-bit digital voltage signal value β is set to a negative value and the comparison is restarted to determine; the determined digital voltage signal value β is stored in the register of the AI data processor.

9. The monitoring method of the IJTAG-based automotive SoC monitoring system according to claim 7, characterized in that The critical path CP delay monitoring includes the following steps: Step 1: The delay monitoring El enters the monitoring mode, and MODE_OFF is set to "1"; Step 2: The controller module sets a window of 256 clock cycles to capture the first change of the data signal, and the MUX uses the captured DATA signal as the input of the "delay line"; Step 3: The data signal at the positive edge of each CLK is captured through the first latch Stage-1. The 32-bit output Q[31:0] of the first latch Stage 1 will be transmitted to the controller, and the controller determines whether any data change has occurred; Step 4: If a change occurs, the controller module will generate a capture signal to the second latch Stage-2, and this latch captures the same content as the first latch Stage-1; if no change occurs, the controller will generate a capture signal at the end of the 256-clock-cycle window, and the measurement of the delay time is obtained through the 32-bit output OUT[31:0] of the second latch Stage-2.

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