A floating point processing method, system, medium and device applied to vector operation

Abstract

The application belongs to the field of floating point calculation, and particularly relates to a floating point processing method, system, medium and device applied to vector operation. The method comprises the following steps: obtaining a to-be-processed instruction, and increasing a counter of a transmission queue; when the counter of the transmission queue is not 0, and a transmission receiving unit is ready, according to the number of elements in the to-be-processed instruction and the category of the to-be-processed instruction, transmitting a first operand corresponding to the number of elements according to a preset channel, calculating the first operand, generating an execution result, putting the execution result into a result queue, and increasing a counter of the result queue; when the counter of the result queue is not 0, integrating the execution result in the result queue according to the category of the to-be-processed instruction; and repeating steps 1 to 3 until all to-be-processed instructions are completed. Through the application, the effects of high performance, small area and low power consumption can be achieved.

Description

Technical Field

[0001] This invention belongs to the field of floating-point computing, and particularly relates to a floating-point processing method, system, medium, and device applied to vector operations. Background Technology

[0002] Artificial intelligence and image processing are important directions in the development of calculators, both of which involve a large number of vector operations, especially floating-point calculations. However, due to the inherent characteristics of floating-point operations, they result in significant clock latency, and in many cases, they are even the timing critical path. This makes the vector floating-point calculation component a key problem that must be solved in high-performance vector calculators.

[0003] Many current vector floating-point calculation methods simply copy the execution unit, which leads to a significant increase in area and power consumption, affecting overall performance.

[0004] The lack of pipelining for execution units results in long waiting times and unsatisfactory performance.

[0005] Insufficient key functional units (such as addition and multiplication) lead to inadequate pipeline performance and prevent vector processing from being implemented effectively. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a floating-point processing method, system, medium and device for vector operations.

[0007] The technical solution of this invention to solve the above-mentioned technical problems is as follows: A floating-point processing method applied to vector operations, comprising:

[0008] Step 1: Obtain image processing data or artificial intelligence data that meets preset conditions. Compile the image processing data or artificial intelligence data using a vector compiler to obtain vector instructions. Generate an operand queue based on the vector instructions. Determine whether the valid bit of the operand queue and the ready bit of the execution unit are both 0. When the determination result is yes, obtain the instruction to be processed, update the status of the instruction to be processed to the ready-to-launch status, and increment the counter of the launch queue.

[0009] Step 2: When the counter of the transmission queue is not 0, verify whether the transmission and receiving unit is ready. When the verification result is ready, according to the number of elements in the instruction to be processed and the type of the instruction to be processed, transmit the first operand corresponding to the number of elements through a preset channel. After all the elements in the instruction to be processed have been transmitted, the first operand is calculated by the transmission and receiving unit to generate an execution result. The execution result is placed in the result queue, and the counter of the result queue is incremented. The type of instruction to be processed is one of floating-point multiplication and addition, floating-point division, floating-point comparison, and floating-point conversion.

[0010] Step 3: When the counter of the result queue is not 0, the execution results in the result queue are integrated according to the category of the instruction to be processed.

[0011] Step 4: Repeat steps 1 to 3 until all pending instructions are completed.

[0012] The beneficial effects of this invention are: **Multiple Instruction Support:** The design includes vector floating-point addition, subtraction, multiplication, division, square root, comparison, sign injection, and integer-floating-point conversion, basically covering the vector floating-point instructions of current RISC instruction sets. The arrangement of different forms in the preset channels balances area, power consumption, and performance. **Higher Performance:** For floating-point multiplication-addition and comparison instructions, which have higher frequency of use, more functions, and greater impact on the program, the clock latency is relatively low compared to floating-point division instructions. These instructions are placed in parallel. More execution units allow for parallel computation of instructions with different floating-point formats, reducing waiting time and improving parallelism and performance. **Smaller Area and Lower Power Consumption:** For floating-point division and conversion instructions that are infrequent, have a larger hardware area, and higher clock latency, a merged placement method is used, reducing the number of execution units, thus reducing hardware area and power consumption. **Performance Improvement through Pipelining:** All execution units are designed to operate in a pipelined manner. Pipelining allows for parallel computation in two aspects, significantly improving performance. Pipelining enables parallel computation of vector instruction data. Due to the inherent characteristics of vectors, each vector instruction involves very long bytes of data, exceeding the maximum width that an arithmetic unit can execute at one time. Therefore, pipelining allows for parallel execution of all vector data, reducing data execution wait times and significantly decreasing the execution time of a single vector instruction, thus improving performance. Pipelining also enables parallel execution between instructions. With a sufficient number of execution units to handle the parallel execution of different instructions, pipelining allows multiple instructions to be continuously issued to the execution unit for execution. The design can support up to four instructions executing simultaneously, reducing the execution time of multiple instructions and improving performance. It is reusable with scalars: by setting the vector enable bit, multiple channels can be disabled, allowing for scalar computation. It offers strong scalarity: extension bits are provided in the design. By adding supported floating-point formats, secondary channels and arithmetic units can be added, supporting other floating-point formats. By adding different functional execution units to the corresponding classes, other instructions can be supported.

[0013] Based on the above technical solution, the present invention can be further improved as follows.

[0014] Furthermore, the preset channel includes:

[0015] Parallel placement channels for floating-point multiply-accumulate and floating-point compare classes;

[0016] And a merged placement channel for floating-point division and floating-point conversion classes;

[0017] The parallel placement channel consists of three channels, each of which is one of a 16-bit channel, a 32-bit channel, or a 64-bit channel.

[0018] The merged placement channel is a single channel.

[0019] Furthermore, before transmitting the first operand corresponding to the number of elements according to the preset channel, the method further includes:

[0020] Determine whether the instruction to be processed is a special instruction. If the determination result is yes, then based on special requirements, the first operand corresponding to the number of elements is transmitted through a preset channel. The special requirements include: transmitting only half of the elements.

[0021] Furthermore, step 4 is preceded by:

[0022] Reset all counters.

[0023] Another technical solution of the present invention to solve the above-mentioned technical problems is as follows: A floating-point processing system applied to vector operations, comprising:

[0024] The preparation module is used to: acquire image processing data or artificial intelligence data that meet preset conditions, compile and process the image processing data or artificial intelligence data through a vector compiler to obtain vector instructions, generate an operand queue according to the vector instructions, determine whether the valid bit of the operand queue and the preparation bit of the execution unit are both 0, and when the determination result is yes, acquire the instruction to be processed, update the status of the instruction to be processed to the ready-to-launch status, and increment the counter of the launch queue.

[0025] The calculation module is used to: verify whether the transmit-receive unit is ready when the counter of the transmit queue is not 0; when the verification result is ready, transmit the first operand corresponding to the number of elements in the instruction to be processed and the category of the instruction to be processed through a preset channel; after all the elements in the instruction to be processed have been transmitted, calculate the first operand through the transmit-receive unit to generate an execution result, put the execution result into the result queue, and increment the counter of the result queue; the category of the instruction to be processed is one of floating-point multiplication-addition, floating-point division, floating-point comparison, and floating-point conversion.

[0026] The results module is used to: when the counter of the results queue is not 0, integrate the execution results in the results queue according to the category of the instruction to be processed;

[0027] The repeat module is used to repeatedly execute the preparation module, the calculation module, and the result module until all pending instructions are completed.

[0028] The beneficial effects of this invention are: **Multiple Instruction Support:** The design includes vector floating-point addition, subtraction, multiplication, division, square root, comparison, sign injection, and integer-floating-point conversion, basically covering the vector floating-point instructions of current RISC instruction sets. The arrangement of different forms in the preset channels balances area, power consumption, and performance. **Higher Performance:** For floating-point multiplication-addition and comparison instructions, which have higher frequency of use, more functions, and greater impact on the program, the clock latency is relatively low compared to floating-point division instructions. These instructions are placed in parallel. More execution units allow for parallel computation of instructions with different floating-point formats, reducing waiting time and improving parallelism and performance. **Smaller Area and Lower Power Consumption:** For floating-point division and conversion instructions that are infrequent, have a larger hardware area, and higher clock latency, a merged placement method is used, reducing the number of execution units, thus reducing hardware area and power consumption. **Performance Improvement through Pipelining:** All execution units are designed to operate in a pipelined manner. Pipelining allows for parallel computation in two aspects, significantly improving performance. Pipelining enables parallel computation of vector instruction data. Due to the inherent characteristics of vectors, each vector instruction involves very long bytes of data, exceeding the maximum width that an arithmetic unit can execute at one time. Therefore, pipelining allows for parallel execution of all vector data, reducing data execution wait times and significantly decreasing the execution time of a single vector instruction, thus improving performance. Pipelining also enables parallel execution between instructions. With a sufficient number of execution units to handle the parallel execution of different instructions, pipelining allows multiple instructions to be continuously issued to the execution unit for execution. The design can support up to four instructions executing simultaneously, reducing the execution time of multiple instructions and improving performance. It is reusable with scalars: by setting the vector enable bit, multiple channels can be disabled, allowing for scalar computation. It offers strong scalarity: extension bits are provided in the design. By adding supported floating-point formats, secondary channels and arithmetic units can be added, supporting other floating-point formats. By adding different functional execution units to the corresponding classes, other instructions can be supported.

[0029] Furthermore, the preset channel includes:

[0030] Parallel placement channels for floating-point multiply-accumulate and floating-point compare classes;

[0031] And a merged placement channel for floating-point division and floating-point conversion classes;

[0032] The parallel placement channel consists of three channels, each of which is one of a 16-bit channel, a 32-bit channel, or a 64-bit channel.

[0033] The merged placement channel is a single channel.

[0034] Furthermore, before transmitting the first operand corresponding to the number of elements according to the preset channel, the method further includes:

[0035] Determine whether the instruction to be processed is a special instruction. If the determination result is yes, then based on special requirements, the first operand corresponding to the number of elements is transmitted through a preset channel. The special requirements include: transmitting only half of the elements.

[0036] Furthermore, it also includes:

[0037] The reset module is used to reset all counters.

[0038] Another technical solution of the present invention to solve the above-mentioned technical problems is as follows: a storage medium storing instructions, wherein when a computer reads the instructions, the computer executes the method described in any of the above-mentioned methods.

[0039] The beneficial effects of this invention are: **Multiple Instruction Support:** The design includes vector floating-point addition, subtraction, multiplication, division, square root, comparison, sign injection, and integer-floating-point conversion, basically covering the vector floating-point instructions of current RISC instruction sets. The arrangement of different forms in the preset channels balances area, power consumption, and performance. **Higher Performance:** For floating-point multiplication-addition and comparison instructions, which have higher frequency of use, more functions, and greater impact on the program, the clock latency is relatively low compared to floating-point division instructions. These instructions are placed in parallel. More execution units allow for parallel computation of instructions with different floating-point formats, reducing waiting time and improving parallelism and performance. **Smaller Area and Lower Power Consumption:** For floating-point division and conversion instructions that are infrequent, have a larger hardware area, and higher clock latency, a merged placement method is used, reducing the number of execution units, thus reducing hardware area and power consumption. **Performance Improvement through Pipelining:** All execution units are designed to operate in a pipelined manner. Pipelining allows for parallel computation in two aspects, significantly improving performance. Pipelining enables parallel computation of vector instruction data. Due to the inherent characteristics of vectors, each vector instruction involves very long bytes of data, exceeding the maximum width that an arithmetic unit can execute at one time. Therefore, pipelining allows for parallel execution of all vector data, reducing data execution wait times and significantly decreasing the execution time of a single vector instruction, thus improving performance. Pipelining also enables parallel execution between instructions. With a sufficient number of execution units to handle the parallel execution of different instructions, pipelining allows multiple instructions to be continuously issued to the execution unit for execution. The design can support up to four instructions executing simultaneously, reducing the execution time of multiple instructions and improving performance. It is reusable with scalars: by setting the vector enable bit, multiple channels can be disabled, allowing for scalar computation. It offers strong scalarity: extension bits are provided in the design. By adding supported floating-point formats, secondary channels and arithmetic units can be added, supporting other floating-point formats. By adding different functional execution units to the corresponding classes, other instructions can be supported.

[0040] Another technical solution of the present invention to solve the above-mentioned technical problems is as follows: an electronic device, including the above-mentioned storage medium and a processor that executes the instructions in the above-mentioned storage medium.

[0041] The beneficial effects of this invention are: **Multiple Instruction Support:** The design includes vector floating-point addition, subtraction, multiplication, division, square root, comparison, sign injection, and integer-floating-point conversion, basically covering the vector floating-point instructions of current RISC instruction sets. The arrangement of different forms in the preset channels balances area, power consumption, and performance. **Higher Performance:** For floating-point multiplication-addition and comparison instructions, which have higher frequency of use, more functions, and greater impact on the program, the clock latency is relatively low compared to floating-point division instructions. These instructions are placed in parallel. More execution units allow for parallel computation of instructions with different floating-point formats, reducing waiting time and improving parallelism and performance. **Smaller Area and Lower Power Consumption:** For floating-point division and conversion instructions that are infrequent, have a larger hardware area, and higher clock latency, a merged placement method is used, reducing the number of execution units, thus reducing hardware area and power consumption. **Performance Improvement through Pipelining:** All execution units are designed to operate in a pipelined manner. Pipelining allows for parallel computation in two aspects, significantly improving performance. Pipelining enables parallel computation of vector instruction data. Due to the inherent characteristics of vectors, each vector instruction involves very long bytes of data, exceeding the maximum width that an arithmetic unit can execute at one time. Therefore, pipelining allows for parallel execution of all vector data, reducing data execution wait times and significantly decreasing the execution time of a single vector instruction, thus improving performance. Pipelining also enables parallel execution between instructions. With a sufficient number of execution units to handle the parallel execution of different instructions, pipelining allows multiple instructions to be continuously issued to the execution unit for execution. The design can support up to four instructions executing simultaneously, reducing the execution time of multiple instructions and improving performance. It is reusable with scalars: by setting the vector enable bit, multiple channels can be disabled, allowing for scalar computation. It offers strong scalarity: extension bits are provided in the design. By adding supported floating-point formats, secondary channels and arithmetic units can be added, supporting other floating-point formats. By adding different functional execution units to the corresponding classes, other instructions can be supported. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating an embodiment of a floating-point processing method for vector operations according to the present invention.

[0043] Figure 2 This is a structural framework diagram of an embodiment of a floating-point processing system applied to vector operations according to the present invention;

[0044] Figure 3 This is a schematic diagram of the vector floating-point component structure provided in an embodiment of a floating-point processing method applied to vector operations according to the present invention;

[0045] Figure 4 This is a flowchart illustrating the execution of floating-point instructions, provided in an embodiment of a floating-point processing method for vector operations according to the present invention. Detailed Implementation

[0046] The principles and features of the present invention are described below. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0047] like Figure 1 As shown, a floating-point processing method applied to vector operations includes:

[0048] Step 1: Obtain image processing data or artificial intelligence data that meets preset conditions. Compile the image processing data or artificial intelligence data using a vector compiler to obtain vector instructions. Generate an operand queue based on the vector instructions. Determine whether the valid bit of the operand queue and the ready bit of the execution unit are both 0. When the determination result is yes, obtain the instruction to be processed, update the status of the instruction to be processed to the ready-to-launch status, and increment the counter of the launch queue.

[0049] Step 2: When the counter of the transmission queue is not 0, verify whether the transmission and receiving unit is ready. When the verification result is ready, according to the number of elements in the instruction to be processed and the type of the instruction to be processed, transmit the first operand corresponding to the number of elements through a preset channel. After all the elements in the instruction to be processed have been transmitted, the first operand is calculated by the transmission and receiving unit to generate an execution result. The execution result is placed in the result queue, and the counter of the result queue is incremented. The type of instruction to be processed is one of floating-point multiplication and addition, floating-point division, floating-point comparison, and floating-point conversion.

[0050] Step 3: When the counter of the result queue is not 0, the execution results in the result queue are integrated according to the category of the instruction to be processed.

[0051] Step 4: Repeat steps 1 to 3 until all pending instructions are completed.

[0052] In some possible implementations, the instruction set supports multiple functions: the design includes vector floating-point addition, subtraction, multiplication, division, square root, comparison, sign injection, integer and floating-point conversion, basically covering the vector floating-point instructions of current RISC instruction sets. The arrangement of different configurations in the preset channels balances area, power consumption, and performance. Higher performance: For floating-point multiplication-addition and floating-point comparison instructions, which have lower clock latency compared to floating-point division instructions, higher frequency of use, more functions, and greater impact on the program, a parallel placement approach is used. More execution units allow for parallel computation of instructions with different floating-point formats, reducing waiting time and improving parallelism and performance. Smaller area and lower power consumption: For floating-point division and floating-point conversion instructions, which have lower frequency of use, larger hardware area, and higher clock latency, a merged placement approach is used, reducing the number of execution units and thus reducing hardware area and power consumption. Improved performance through pipelining: All execution units are designed to operate in a pipelining manner. Pipelining allows for parallel computation in two aspects, significantly improving performance. Pipelining enables parallel computation of vector instruction data. Due to the inherent characteristics of vectors, each vector instruction involves very long bytes of data, exceeding the maximum width that an arithmetic unit can execute at one time. Therefore, pipelining allows for parallel execution of all vector data, reducing data execution wait times and significantly decreasing the execution time of a single vector instruction, thus improving performance. Pipelining also enables parallel execution between instructions. With a sufficient number of execution units to handle the parallel execution of different instructions, pipelining allows multiple instructions to be continuously issued to the execution unit for execution. The design can support up to four instructions executing simultaneously, reducing the execution time of multiple instructions and improving performance. It is reusable with scalars: by setting the vector enable bit, multiple channels can be disabled, allowing for scalar computation. It offers strong scalarity: extension bits are provided in the design. By adding supported floating-point formats, secondary channels and arithmetic units can be added, supporting other floating-point formats. By adding different functional execution units to the corresponding classes, other instructions can be supported.

[0053] It should be noted that the preset conditions can be: continuous, repetitive and large amounts of data. This part of the data can be selected by manual screening. Similarly, the definition of "large amount" can also be determined manually.

[0054] Image processing data can be any data needed or used in any processing step within the field of image processing. Similarly, artificial intelligence data can be any data needed or used in any processing, recognition, or interaction step within the field of artificial intelligence. The vector compiler is an existing compiler whose function is to compile the code of image data or the code of artificial intelligence data into vector instructions. Generating an operand queue based on the vector instructions is simply instruction arrangement; all generated vector instructions are arranged in sequence to form the operand queue. Each vector instruction in the operand queue has a corresponding operand. In this scheme, the operand queue, the transmit queue, and the result queue all have a valid bit, which indicates whether there is data to be processed in that queue. A valid bit of 0 indicates the presence of data to be processed. Furthermore, the execution unit, transmit / receive unit, etc., can all be understood as spaces for receiving, processing, or temporarily storing data to be processed, and each has a ready bit, which is located in the valid bit. Additionally, the instruction to be processed can be understood as any vector instruction compiled and transformed by the vector compiler. By judging the valid bit and the ready bit of the execution unit, and combining this scheme's designed preset channel, the processing of the instruction to be processed is completed. Repeating the above content achieves the processing of all vector instructions.

[0055] Once all pending instructions are completed, the resulting image data (such as image convolution) can be obtained. This result can be applied in subsequent image optimization processes such as smoothing, sharpening, denoising, and edge detection. Alternatively, once all pending instructions are completed, the resulting image data (image transformation) can be obtained. This result can be applied in rapid feature extraction or image enhancement processes.

[0056] This solution can be applied to either image processing or artificial intelligence. The following section uses image processing as an example to illustrate this solution. One frequently encountered algorithm in image processing is floating-point matrix multiplication.

[0057] Instruction issue queues and result queues can cache multiple instructions during floating-point matrix multiplication operations, allowing multiple instructions with different operations to execute simultaneously. This solves the latency problem caused by floating-point matrix multiplication, which consists of various instruction types, where later instructions must wait for the results of earlier instructions before execution. In short, it provides a solution for quickly completing matrix operations.

[0058] Simultaneous operand count can resolve the waiting issue caused by a large number of data needing to be processed simultaneously in floating-point matrix multiplication. The number of elements indicates how many identical operations are yet to be executed. While the current element is being executed, subsequent identical operations can be executed sequentially, reducing the need for repeated instruction and data fetching and significantly improving execution efficiency.

[0059] In continuous and rapid image processing, where multiple color data need to be processed quickly, the image can be viewed as a matrix, with each pixel representing a matrix element. Some image processing becomes matrix processing (such as image transformation), and convolution operations involve numerous repetitive floating-point additions, multiplications, and multiply-additions. A vector compiler transforms these repetitive floating-point operations into vector floating-point instructions (addition, multiplication, multiply-addition, etc.) to avoid redundant instruction and data reads and improve processing efficiency. Essentially, in image transformation, the vector compiler first converts the floating-point operations into vector floating-point instructions. It's important to note that the floating-point operations in image transformation are known instructions.

[0060] In a multi-channel execution unit, a large number of floating-point addition, multiplication, and multiply-add instructions for images can be executed simultaneously in parallel. Moreover, each image data of different widths has its own execution channel without affecting the others, which greatly improves the calculation speed and reduces the data congestion caused by repetitive operations on large amounts of data in the field of image processing, thereby improving the processing speed of image matrices and image convolution.

[0061] It should be noted that the design concept of this solution is as follows: Figure 3As shown, the top layer is the floating-point layer. In this layer, the operands from the operand queue are primarily processed according to the instruction requirements of the decoded instructions from the decoding unit. (Instructions with the same computational process are merged into one operation by adding some operations or judgment bits, and then sent to the execution unit. For example, addition and reverse addition, multiplication and reverse multiplication, etc., only require switching the positions of the two operands to be considered the same operation. Instructions with operands of different precisions have their precision unified according to the instruction result requirements.) This also forms the issue and result queues. (Issue queue: Instruction execution supports pipelined execution, so the upper-level decoding unit can continuously send multiple instructions that do not require computation, and these instructions can be sent to the execution unit simultaneously. A queue is needed to buffer these instructions that can be sent downwards. Result queue: Similar to the issue queue, it supports multiple instructions submitting results simultaneously, requiring a queue to buffer the results.) The process involves determining whether a transmission is possible (checking if the necessary arithmetic units are idle and ready to accept new operations, and whether all operands for the current instruction are prepared. Idleness is determined via a handshake signal; non-fully pipelining units can check their own internal instruction processing status to determine if they can accept new operations, while fully pipelining units can receive new instructions for processing in every clock cycle), and writing back the result (writing back the result of the instruction is written back to the result register. This only requires checking if the result queue is full; if not, writing back is allowed). It also specifies the supported floating-point formats (in this invention, selectable floating-point formats are allowed: only double-precision, single-precision, half-precision, and single-byte floating-point formats are recognized; setting the corresponding flag to 0 prevents the generation of execution channels for that format, thus meeting customized needs).

[0062] The next level is the first-level channel partitioning module. This layer mainly divides the entire floating-point system into four channels. Each channel has corresponding functions and execution unit placement methods (the composition method of functional components), as well as functional component implementation modules. This primarily involves injecting corresponding functional modules into the two placement modes respectively. In the parallel module, the multiply-accumulate module (ADDMUL) and the comparison / sign injection module (comp / sgnj) are instantiated. In the merge-slice module, the division / square root module (div / sqrt) and the integer-to-floating-point conversion module (cvt) are instantiated.

[0063] The final level divides functional channels based on the supported floating-point formats, with different slicing methods yielding different results. In the parallel placement method, three functional channels are divided based on the three supported floating-point formats (32-bit, 64-bit, and 16-bit). The merged method, however, does not divide channels based on different formats, resulting in only one functional channel. Specific execution units are instantiated based on different formats, and the number of instantiated execution units varies depending on the placement method. In the parallel method, a 32-bit channel instantiates two 32-bit execution units, a 64-bit channel instantiates one 64-bit execution unit, and a 16-bit channel instantiates four 16-bit execution units. The merged method, however, has only one channel, below which execution units are instantiated based on the narrowest supported floating-point format. The design supports a narrowest format of 16-bit, so four execution units are instantiated: one 64-bit, one 32-bit, and two 16-bit execution units. When performing 16-bit corresponding calculations in merge slice mode, all four components operate simultaneously, and the lower 16 bits of the operand are taken as the effective operand. In 32-bit calculations, the two 16-bit components are invalid, and the lower 32 bits of the 32-bit and 64-bit components are taken as the effective operands. In 64-bit calculations, only the 64-bit component is valid.

[0064] Channel allocation phase:

[0065] First, in the top-level module, floating-point operations are divided into four channels—ADDMUL, DIVSQRT, NONCOMP, and CONV—based on the four instruction types, slicing methods, and corresponding configurations. Instructions are then placed into their respective channels for execution (the determination is still based on the instruction type mentioned above; each type has its own corresponding channel, for a total of four channels). In the result queue, arbitration is performed after each execution unit outputs its results (here, a fixed priority and a round-robin arbitrator are used for arbitration; instructions with a high probability of occurrence in normal use, such as addition, subtraction, and multiplication, are set to high priority, while instructions with a low probability of occurrence are set to low priority. Then, within each priority level, a round-robin arbitrator is used to prioritize the previously occurring instruction to the end). This ensures that only one result is valid per channel at any given time. After using the arbitrator, multiple results enter and are output according to their priority.

[0066] The next module then implements two execution unit placement methods: parallel and merged. The implementation structures differ between these methods. The parallel method determines the number of execution channels based on the given number of floating-point formats, resulting in three channels corresponding to 32, 64, and 16 floating-point formats respectively. The merged method, on the other hand, determines the number of execution units based on the minimum width of the implemented floating-point format; since the minimum width is 16, there are four execution units. After each execution unit produces a result, arbitration is performed to ensure that only one channel's result is valid.

[0067] The vector floating-point instructions in the current mainstream instruction set are divided into four categories: floating-point multiplication and addition, which mainly includes vector floating-point addition (subtraction), multiplication, and multiplication-addition instructions; floating-point division, which mainly includes vector floating-point division and floating-point square root instructions; floating-point comparison, which mainly includes vector floating-point comparison and vector floating-point sign injection instructions; and floating-point conversion, which mainly includes instructions for converting between vector floating-point and integers. Separate arithmetic channels are established for each of these four categories, and these channels are independent of each other.

[0068] Based on the differences in clock latency, hardware consumption, usage frequency, and the number of instructions required for floating-point instruction operations, the four types of instructions are divided into two types of arithmetic unit placement methods: one is the parallel placement method, which is used for floating-point multiplication and addition and floating-point comparison; the other is the merged placement method, which is used for floating-point division and floating-point conversion.

[0069] It supports three standard IEEE 754 floating-point formats: double precision, single precision, and half precision.

[0070] The number of arithmetic units varies depending on the supported format and placement method of the channel. In parallel processing, the channel is divided into three secondary channels based on the three supported formats, each with different arithmetic units. The single-precision channel has two 32-bit floating-point units, the double-precision channel has one 64-bit arithmetic unit, and the half-precision channel has four 16-bit arithmetic units. The arithmetic units in each channel are independent; the same instruction in different formats can be processed in parallel without affecting each other.

[0071] The channel using the merging method has only one secondary channel. It contains one 64-bit arithmetic unit, one 32-bit arithmetic unit, and two 16-bit arithmetic units. When performing narrow-bit-width floating-point operations, it borrows the wide-bit-width arithmetic unit and takes the low-order bits of the result.

[0072] All operations can be performed in a pipelined manner. The control signals of the pipeline are implemented through a handshake between valid and ready. When the data sender has the data ready, it will check whether the receiver's ready signal is valid. If it is valid, it will send the data and the valid bit. The receiver checks whether the valid signal is valid. If it is valid, it will process the data. If it is invalid, it will wait.

[0073] Because parallel computation is possible, a round-robin arbiter is used to arbitrate the results and data. When multiple results are written back at the same time, the arbiter prioritizes writing back the results with higher priority and waits for the results with lower priority.

[0074] The vector enable bit is used to enable the sharing of vectors and scalar floating-point operations. When the enable bit is invalid, only the first unit of operation under the second-level channel can be used, and the others are invalid, so as to realize scalar operations.

[0075] Specifically, such as Figure 4 As shown, in step 1, it is determined whether the valid bit of the operand queue and the ready bit of the execution unit are both 0. When the determination result is yes, the instruction to be processed is obtained, the status of the instruction to be processed is updated to the ready-to-be-launched state, and the counter of the launch queue is incremented. The specific process is illustrated in the following example:

[0076] Preparation Phase: The preparation phase mainly takes place in the top-level module. It primarily receives instructions and operands, as well as mask values, and sends the result, destination address, and valid bits (the result is the output of the corresponding instruction's operation; the destination address is in the instruction encoding, decoded by the upper-level decoder and passed down; the valid bits are returned by the execution unit along with the execution result, indicating that the result is valid) back to the VRF (Vector Register). Within the module, each instruction is divided into three execution phases: issue, execute, and commit. (After the instruction is fetched, it is decoded, and the required operands are retrieved from the register based on the source address and then sent to the execution phase. Execution involves a corresponding execution unit with floating-point addition, subtraction, multiplication, and division algorithms. After execution, the result is sent to the register via the top-level floating-point module based on the decoded destination address.) Each phase has a corresponding instruction counter with a depth of 4, and a result queue with a depth of 2 to store the result values ​​returned by the execution unit.

[0077] The entire preparation phase is divided into several stages;

[0078] 1. Maintain state: In this state, all valid bits and ready bits are 0, and all counters retain their original values. There is no mask operation by default.

[0079] 2. Issuing Instruction Status to the Execution Unit (Each instruction has an instruction status, marked at the floating-point level. This includes: Issue status, where the instruction is still preparing operands and corresponding flags at the floating-point level, or waiting to be issued; Execution status, where the instruction is issued to the execution unit and is being executed, and the floating-point level marks the instruction as being executed; Commit status, where the instruction has been completed, and the result and result validity bits are committed to the floating-point level by the execution unit; and Writing the Result Back to the VRF status, where the floating-point level exits the marking status after committing the instruction result to the floating-point register, indicating that the instruction has been completed.)

[0080] Step 2: When the counter of the transmission queue is not 0, verify whether the transmission and receiving unit is ready. When the verification result is ready, according to the number of elements in the instruction to be processed and the type of the instruction to be processed, transmit the first operand corresponding to the number of elements through a preset channel. After all elements in the instruction to be processed have been transmitted, the transmission and receiving unit calculates the first operand to generate an execution result, puts the execution result into the result queue, and increments the counter of the result queue. The specific process for the instruction to be processed being one of the following: floating-point multiplication-addition, floating-point division, floating-point comparison, and floating-point conversion types can be referred to the following example:

[0081] When the issue queue (both the issue queue and the result queue are in the top-level floating-point unit) is not 0 (instructions are waiting to be issued), the valid bit of the required execution unit (here, the execution unit is the actual execution unit, not in the top-level unit; it's the channel of the execution stage. The top-level floating-point unit only has a valid bit indicating which execution unit is needed) is pulled high. Then, it verifies whether the required execution unit is ready (in the floating-point unit pipeline, this valid bit is always 1 to ensure that instructions can be continuously issued). At the same time, an acknowledgment signal indicating that the operand has been received is returned to the operand queue, which is equivalent to a handshake signal. Once a valid bit of an operand is received and the operand is buffered, an acknowledgment signal is returned. This mode records the number of elements issued when issuing operands (here, it's floating-point calculation of vectors; all data is in vector form. A vector operand consists of many 8-bit, 16-bit, 32-bit, or 64-bit elements; the specific width is pre-specified by a special instruction to determine the element width of this instruction; an element here is a single 8-bit, 16-bit, 32-bit, or 64-bit element in a vector operand) and updates the element counter for each generation (this counter is determined by the number of elements; once the width of a single element and the vector length are determined, the number of elements is also determined = element width / vector length) until all elements are issued. If it's a reduced instruction (the instructions mentioned above are a general term for all floating-point instructions; the reduced instruction here is just one type; each instruction has a special flag indicating what kind of instruction it is after decoding), only half of the elements are issued (based on instruction requirements; some instructions require high-order bits, while others default to low-order bits). If masking operations are required (these operations involve special adjustments to the instruction operands and simultaneous checks of the transmit queue), the mask is confirmed to be high and returned to the mask unit. Finally, the transmit counter is checked to see if it is 0; if so, the transmit micro-operation for this vector instruction is completed.

[0082] Step 3: When the counter in the result queue is not 0, the specific process of integrating the execution results in the result queue according to the category of the instruction to be processed can be referred to in the following example:

[0083] The result (the result after execution, i.e., the calculated result) is written to the result queue status (execution phase). First, it checks whether each result queue (there are four result queues corresponding to the four major functional components mentioned above) is full. If not, it prepares to accept the result. Then, based on the operation type in the instruction execution queue (first checking what types of instructions are in the instruction queue and then accepting the corresponding result from the corresponding result queue), it determines which execution unit (there are only four large execution units in total, each of which can be subdivided into many operations) to accept the result, valid bits, and mask value. If it is a narrowing instruction (again, based on the operation type), the result is reshuffled. Simultaneously, check if the valid bit of the execution unit (the unit required for this instruction's calculation) and the result queue are full. If both are valid, calculate (record a number for each returned result; completion occurs when the result equals the number of elements; the method for calculating the number of elements is mentioned above) how many elements have been processed during the execution phase and update the number of elements to be processed. If it's a reduction instruction, only half of the elements are processed, and then the result is written to the result queue. Finally, check if the execution instruction counter is 0; if it is 0, the write status is complete.

[0084] 4. Write the result back to the VRF state. First, send the result signal to the VRF, including the validity bit, address, instruction ID, result, and mask bit. Check if the result validity bit or mask operand is valid, record the number of elements to be committed (calculated here based on the number of elements), and simultaneously set the result queue validity bit to 0. Check if the result queue is full; if full, set the write instruction to 0; otherwise, increment the read pointer (normally not full) and increment the result queue counter. Then calculate the commit counter. Finally, check if the commit counter is 0. If it is 0, it indicates that the commit operation has been completed, and set the instruction completion flag to 1, sending it to the upper-level control unit.

[0085] Step 4: Repeat steps 1 to 3 until all pending instructions are completed. The specific process can be seen in the following example:

[0086] First, check if the instruction operation queue is full, if the valid bit from the upper-level control unit is valid, and if the operation is a floating-point operation. If all are valid, assign the operation data from the upper-level control unit to the operation queue and initialize all counters. If it is a floating-point instruction that requires expansion, modify the corresponding width flag. Then, increment all instruction pointers and queues by 1.

[0087] In Example 1, in the parallel placement mode, the implemented operations are ADDMUL and NONCOMP. The number of specific operation modules in the three channels implemented at the upper layer varies depending on the different floating-point formats. Channel 0 uses a 32-bit format with two 32-bit operation units; Channel 1 has one 64-bit operation unit; and Channel 2 has four 16-bit operation units. Each channel executes instructions of corresponding widths, and the results do not interfere with each other. The operand width entering the unit is also the same as the format, and is separated before entering. The result is combined into 64 bits only after exiting the channel.

[0088] In the merged placement method, the operations implemented are DIVSSQRT and CONV. The number of execution units in each channel is as follows: Channel 0 is a 64-bit unit, and only this channel is valid when the instruction is 64-bit; Channel 1 is a 64-bit unit, and the lower 32 bits of Channel 1 and Channel 0 are valid when the instruction is 32-bit; Channels 2 and 3 are each a 16-bit unit, and the lower 16 bits of all channels are valid when the instruction is 16-bit. Operands are also placed according to element width: for 32-bit instructions, Channel 1 places the high 32 bits; for 16-bit instructions, Channel 3 places the low 16 bits, Channel 2 places bits 16 to 32, Channel 1 is a 64-bit unit shifted right by 16 bits, and Channel 0 places the full 64 bits.

[0089] Preferably, in any of the above embodiments, the preset channel includes:

[0090] Parallel placement channels for floating-point multiply-accumulate and floating-point compare classes;

[0091] And a merged placement channel for floating-point division and floating-point conversion classes;

[0092] The parallel placement channel consists of three channels, each of which is one of a 16-bit channel, a 32-bit channel, or a 64-bit channel.

[0093] The merged placement channel is a single channel.

[0094] Preferably, in any of the above embodiments, before transmitting the first operand corresponding to the number of elements through a preset channel, the method further includes:

[0095] Determine whether the instruction to be processed is a special instruction. If the determination result is yes, then based on special requirements, the first operand corresponding to the number of elements is transmitted through a preset channel. The special requirements include: transmitting only half of the elements.

[0096] Preferably, in any of the above embodiments, step 4 is preceded by:

[0097] Reset all counters.

[0098] like Figure 2As shown, a floating-point processing system for vector operations includes:

[0099] The preparation module 100 is used to: acquire image processing data or artificial intelligence data that meet preset conditions, compile and process the image processing data or artificial intelligence data through a vector compiler to obtain vector instructions, generate an operand queue according to the vector instructions, determine whether the valid bit of the operand queue and the preparation bit of the execution unit are both 0, and when the determination result is yes, acquire the instruction to be processed, update the status of the instruction to be processed to the ready-to-launch status, and increment the counter of the launch queue.

[0100] The calculation module 200 is used to: verify whether the transmit-receive unit is ready when the counter of the transmit queue is not 0; when the verification result is ready, transmit the first operand corresponding to the number of elements in the instruction to be processed and the category of the instruction to be processed through a preset channel; after all the elements in the instruction to be processed have been transmitted, calculate the first operand through the transmit-receive unit to generate an execution result, put the execution result into the result queue, and increment the counter of the result queue; the category of the instruction to be processed is one of floating-point multiplication-addition, floating-point division, floating-point comparison, and floating-point conversion.

[0101] The result module 300 is used to: when the counter of the result queue is not 0, integrate the execution results in the result queue according to the category of the instruction to be processed;

[0102] The repeat module 400 is used to repeatedly execute the preparation module 100, the calculation module 200, and the result module 300 until all pending instructions are completed.

[0103] In some possible implementations, the instruction set supports multiple functions: the design includes vector floating-point addition, subtraction, multiplication, division, square root, comparison, sign injection, integer and floating-point conversion, basically covering the vector floating-point instructions of current RISC instruction sets. The arrangement of different configurations in the preset channels balances area, power consumption, and performance. Higher performance: For floating-point multiplication-addition and floating-point comparison instructions, which have lower clock latency compared to floating-point division instructions, higher frequency of use, more functions, and greater impact on the program, a parallel placement approach is used. More execution units allow for parallel computation of instructions with different floating-point formats, reducing waiting time and improving parallelism and performance. Smaller area and lower power consumption: For floating-point division and floating-point conversion instructions, which have lower frequency of use, larger hardware area, and higher clock latency, a merged placement approach is used, reducing the number of execution units and thus reducing hardware area and power consumption. Improved performance through pipelining: All execution units are designed to operate in a pipelining manner. Pipelining allows for parallel computation in two aspects, significantly improving performance. Pipelining enables parallel computation of vector instruction data. Due to the inherent characteristics of vectors, each vector instruction involves very long bytes of data, exceeding the maximum width that an arithmetic unit can execute at one time. Therefore, pipelining allows for parallel execution of all vector data, reducing data execution wait times and significantly decreasing the execution time of a single vector instruction, thus improving performance. Pipelining also enables parallel execution between instructions. With a sufficient number of execution units to handle the parallel execution of different instructions, pipelining allows multiple instructions to be continuously issued to the execution unit for execution. The design can support up to four instructions executing simultaneously, reducing the execution time of multiple instructions and improving performance. It is reusable with scalars: by setting the vector enable bit, multiple channels can be disabled, allowing for scalar computation. It offers strong scalarity: extension bits are provided in the design. By adding supported floating-point formats, secondary channels and arithmetic units can be added, supporting other floating-point formats. By adding different functional execution units to the corresponding classes, other instructions can be supported.

[0104] Preferably, in any of the above embodiments, the preset channel includes:

[0105] Parallel placement channels for floating-point multiply-accumulate and floating-point compare classes;

[0106] And a merged placement channel for floating-point division and floating-point conversion classes;

[0107] The parallel placement channel consists of three channels, each of which is one of a 16-bit channel, a 32-bit channel, or a 64-bit channel.

[0108] The merged placement channel is a single channel.

[0109] Preferably, in any of the above embodiments, before transmitting the first operand corresponding to the number of elements through a preset channel, the method further includes:

[0110] Determine whether the instruction to be processed is a special instruction. If the determination result is yes, then based on special requirements, the first operand corresponding to the number of elements is transmitted through a preset channel. The special requirements include: transmitting only half of the elements.

[0111] Preferably, in any of the above embodiments, it further includes:

[0112] The reset module is used to reset all counters.

[0113] Another technical solution of the present invention to solve the above-mentioned technical problems is as follows: a storage medium storing instructions, wherein when a computer reads the instructions, the computer executes the method described in any of the above-mentioned methods.

[0114] In some possible implementations, the instruction set supports multiple functions: the design includes vector floating-point addition, subtraction, multiplication, division, square root, comparison, sign injection, integer and floating-point conversion, basically covering the vector floating-point instructions of current RISC instruction sets. The arrangement of different configurations in the preset channels balances area, power consumption, and performance. Higher performance: For floating-point multiplication-addition and floating-point comparison instructions, which have lower clock latency compared to floating-point division instructions, higher frequency of use, more functions, and greater impact on the program, a parallel placement approach is used. More execution units allow for parallel computation of instructions with different floating-point formats, reducing waiting time and improving parallelism and performance. Smaller area and lower power consumption: For floating-point division and floating-point conversion instructions, which have lower frequency of use, larger hardware area, and higher clock latency, a merged placement approach is used, reducing the number of execution units and thus reducing hardware area and power consumption. Improved performance through pipelining: All execution units are designed to operate in a pipelining manner. Pipelining allows for parallel computation in two aspects, significantly improving performance. Pipelining enables parallel computation of vector instruction data. Due to the inherent characteristics of vectors, each vector instruction involves very long bytes of data, exceeding the maximum width that an arithmetic unit can execute at one time. Therefore, pipelining allows for parallel execution of all vector data, reducing data execution wait times and significantly decreasing the execution time of a single vector instruction, thus improving performance. Pipelining also enables parallel execution between instructions. With a sufficient number of execution units to handle the parallel execution of different instructions, pipelining allows multiple instructions to be continuously issued to the execution unit for execution. The design can support up to four instructions executing simultaneously, reducing the execution time of multiple instructions and improving performance. It is reusable with scalars: by setting the vector enable bit, multiple channels can be disabled, allowing for scalar computation. It offers strong scalarity: extension bits are provided in the design. By adding supported floating-point formats, secondary channels and arithmetic units can be added, supporting other floating-point formats. By adding different functional execution units to the corresponding classes, other instructions can be supported.

[0115] Another technical solution of the present invention to solve the above-mentioned technical problems is as follows: an electronic device, including the above-mentioned storage medium and a processor that executes the instructions in the above-mentioned storage medium.

[0116] In some possible implementations, the instruction set supports multiple functions: the design includes vector floating-point addition, subtraction, multiplication, division, square root, comparison, sign injection, integer and floating-point conversion, basically covering the vector floating-point instructions of current RISC instruction sets. The arrangement of different configurations in the preset channels balances area, power consumption, and performance. Higher performance: For floating-point multiplication-addition and floating-point comparison instructions, which have lower clock latency compared to floating-point division instructions, higher frequency of use, more functions, and greater impact on the program, a parallel placement approach is used. More execution units allow for parallel computation of instructions with different floating-point formats, reducing waiting time and improving parallelism and performance. Smaller area and lower power consumption: For floating-point division and floating-point conversion instructions, which have lower frequency of use, larger hardware area, and higher clock latency, a merged placement approach is used, reducing the number of execution units and thus reducing hardware area and power consumption. Improved performance through pipelining: All execution units are designed to operate in a pipelining manner. Pipelining allows for parallel computation in two aspects, significantly improving performance. Pipelining enables parallel computation of vector instruction data. Due to the inherent characteristics of vectors, each vector instruction involves very long bytes of data, exceeding the maximum width that an arithmetic unit can execute at one time. Therefore, pipelining allows for parallel execution of all vector data, reducing data execution wait times and significantly decreasing the execution time of a single vector instruction, thus improving performance. Pipelining also enables parallel execution between instructions. With a sufficient number of execution units to handle the parallel execution of different instructions, pipelining allows multiple instructions to be continuously issued to the execution unit for execution. The design can support up to four instructions executing simultaneously, reducing the execution time of multiple instructions and improving performance. It is reusable with scalars: by setting the vector enable bit, multiple channels can be disabled, allowing for scalar computation. It offers strong scalarity: extension bits are provided in the design. By adding supported floating-point formats, secondary channels and arithmetic units can be added, supporting other floating-point formats. By adding different functional execution units to the corresponding classes, other instructions can be supported.

[0117] Readers should understand that in the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0118] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the method embodiments described above are merely illustrative. For instance, the division of steps is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple steps may be combined or integrated into another step, or some features may be ignored or not executed.

[0119] If the above methods are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0120] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A floating-point processing method applied to vector operations, characterized in that, include: Step 1: Obtain image processing data or artificial intelligence data that meets preset conditions. Compile the image processing data or artificial intelligence data using a vector compiler to obtain vector instructions. Generate an operand queue based on the vector instructions. Determine whether the valid bit of the operand queue and the ready bit of the execution unit are both 0. When the determination result is yes, extract any instruction to be processed from the operand queue, update the status of any instruction to be processed to the ready-to-launch state, and increment the counter of the launch queue. Step 2: When the counter of the transmission queue is not 0, verify whether the transmission and receiving unit is ready. When the verification result is ready, according to the number of elements in any pending instruction and the category of any pending instruction, transmit the first operand corresponding to the number of elements through a preset channel. After all elements in any pending instruction have been transmitted, calculate the first operand through the transmission and receiving unit to generate an execution result, put the execution result into the result queue, and increment the counter of the result queue. The category of any pending instruction is one of floating-point multiplication and addition, floating-point division, floating-point comparison, and floating-point conversion. Step 3: When the counter of the result queue is not 0, the execution results in the result queue are integrated according to the category of any instruction to be processed. Step 4: Repeat steps 1 to 3 until all pending instructions are completed.

2. The floating-point processing method applied to vector operations according to claim 1, characterized in that, The preset channels include: Parallel placement channels for floating-point multiply-accumulate and floating-point compare classes; And a merged placement channel for floating-point division and floating-point conversion classes; The parallel placement channel consists of three channels, each of which is one of a 16-bit channel, a 32-bit channel, or a 64-bit channel. The merged placement channel is a single channel.

3. The floating-point processing method applied to vector operations according to claim 1, characterized in that, Before transmitting the first operand corresponding to the number of elements according to the preset channel, the following steps are also included: Determine whether any of the instructions to be processed is a special instruction. If the determination result is yes, then based on special requirements, the first operand corresponding to the number of elements is transmitted through a preset channel. The special requirements include: transmitting only half of the elements.

4. The floating-point processing method applied to vector operations according to claim 1, characterized in that, Step 4 is preceded by: Reset all counters.

5. A floating-point processing system applied to vector operations, characterized in that, include: The preparation module is used to: acquire image processing data or artificial intelligence data that meet preset conditions; compile and process the image processing data or artificial intelligence data through a vector compiler to obtain vector instructions; generate an operand queue according to the vector instructions; determine whether the valid bit of the operand queue and the preparation bit of the execution unit are both 0; when the determination result is yes, extract any instruction to be processed from the operand queue; update the status of any instruction to be processed to the ready-to-launch state; and increment the counter of the launch queue. The calculation module is used to: verify whether the transmit-receive unit is ready when the counter of the transmit queue is not 0; when the verification result is ready, transmit the first operand corresponding to the number of elements in any instruction to be processed and the category of any instruction to be processed through a preset channel; after all elements in any instruction to be processed have been transmitted, calculate the first operand through the transmit-receive unit to generate an execution result, put the execution result into the result queue, and increment the counter of the result queue; the category of any instruction to be processed is one of floating-point multiplication-addition, floating-point division, floating-point comparison, and floating-point conversion. The results module is used to: when the counter of the results queue is not 0, integrate the execution results in the results queue according to the category of any instruction to be processed; The repeat module is used to repeatedly execute the preparation module, the calculation module, and the result module until all pending instructions are completed.

6. A floating-point processing system for vector operations according to claim 5, characterized in that, The preset channels include: Parallel placement channels for floating-point multiply-accumulate and floating-point compare classes; And a merged placement channel for floating-point division and floating-point conversion classes; The parallel placement channel consists of three channels, each of which is one of a 16-bit channel, a 32-bit channel, or a 64-bit channel. The merged placement channel is a single channel.

7. A floating-point processing system for vector operations according to claim 5, characterized in that, Before transmitting the first operand corresponding to the number of elements according to the preset channel, the following steps are also included: Determine whether any of the instructions to be processed is a special instruction. If the determination result is yes, then based on special requirements, the first operand corresponding to the number of elements is transmitted through a preset channel. The special requirements include: transmitting only half of the elements.

8. A mediator allocation system based on QR codes according to claim 5, characterized in that, Also includes: The reset module is used to reset all counters.

9. A storage medium, characterized in that, The medium stores instructions that, when read by a computer, cause the computer to execute the method as described in any one of claims 1 to 4.

10. An electronic device, characterized in that, Includes the storage medium of claim 9 and a processor that executes instructions within the storage medium.

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