Remote powered contactless card

Abstract

Embodiments of the present disclosure relate to a remote powered contactless card. The present disclosure relates to an electronic device connected to an antenna. The electronic device delivers a first amplitude modulated analog signal of a signal captured by the antenna, the captured signal being associated with a spaced electromagnetic field presenting a minimum level. The electronic device comprises a first circuit, a second circuit and a third circuit. The first circuit delivers a second analog signal resulting from rectification and filtering of the first analog signal. The second circuit delivers a first binary signal based on demodulation of the second analog signal. The third circuit couples the antenna to a resistor during each pause. The resistance value of the resistor depends on the maximum amplitude of the electromagnetic field before the pause.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French application No. 2200102, filed on January 7, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to electronic devices, and in certain embodiments to remotely powered contactless cards. Background Technology

[0004] A remotely powered contactless card is a card designed to exchange data with a terminal, drawing its power from the terminal. Data can be exchanged between the remotely powered contactless card and the terminal by modulating the magnetic field emitted by the terminal.

[0005] For some applications, the maximum delay that the card should begin responding to messages from the terminal may be imposed. The terminal can end message transmission with a pause, during which the electromagnetic field is maintained at a minimum level, and expects a response from the card at the end of the pause. This means the electronic device should correctly detect the card when the pause ends following a message sent by the terminal. However, the signal representing the electromagnetic field captured by the card may fluctuate, potentially causing errors in the card's electronic device's detection of the card at the end of a pause following a message sent by the terminal. Summary of the Invention

[0006] One embodiment aims to provide an electronic device for remotely powered contactless cards that overcomes all or part of the disadvantages of existing electronic devices.

[0007] According to one embodiment, the electronic device of the remotely powered contactless card is configured to detect the end of a pause in the electromagnetic field delivered by the terminal.

[0008] According to one embodiment, the signal representing the electromagnetic field emitted by the terminal, captured by the card, does not exhibit oscillation during the pause.

[0009] One embodiment provides an electronic device intended to be connected to an antenna that delivers a first amplitude-modulated analog signal captured from an electromagnetic field exhibiting minimal horizontal spacing. The electronic device includes: a first circuit for delivering a second analog signal obtained by rectifying and filtering the first analog signal; a second circuit for delivering a first binary signal based on demodulation of the second analog signal; and a third circuit for coupling the antenna to a resistor during each pause, the resistance value of which depends on the maximum amplitude of the electromagnetic field before the pause.

[0010] One embodiment also provides a method for processing a first amplitude-modulated analog signal captured from an electromagnetic field delivered via an antenna, the electromagnetic field exhibiting minimal horizontal spacing, the method comprising: delivering a second analog signal obtained by rectifying and filtering the first analog signal by a first circuit; delivering a first binary signal based on demodulation of the second analog signal by a second circuit; and coupling the antenna to a resistor by a third circuit during each pause, the resistance value of the resistor depending on the maximum amplitude of the electromagnetic field before the pause.

[0011] According to one embodiment, the third circuit is configured to couple the antenna to a resistor at a resistance value when the first binary signal switches from a first state to a second state.

[0012] According to one embodiment, the third circuit is configured to interrupt the coupling between the antenna and the resistor at the resistance value when the first binary signal switches from the second state to the first state.

[0013] According to one embodiment, the third circuit is configured to interrupt the coupling between the antenna and the resistor at the end of a constant duration.

[0014] According to one embodiment, the third circuit includes: an analog-to-digital converter configured to convert a third analog signal representing a second analog signal into a first digital signal; a fourth circuit configured to deliver a second digital signal equal to the first digital signal with a delay; a fifth circuit configured to deliver a third digital signal, configured to deliver the third digital signal with a constant digital value when the first binary signal is in a first state, and configured to deliver the third digital signal equal to the second signal when the first binary signal switches from the first state to a second state; and a resistor-to-analog converter configured to convert the third digital signal into a resistance value.

[0015] According to one embodiment, the analog-to-digital converter is rated by a first clock signal, and the fourth circuit includes a first flip-flop rated by a second clock signal, the frequency of which is a divisor of the frequency of the first clock signal.

[0016] According to one embodiment, the fifth circuit includes a second flip-flop and logic AND gates, the second flip-flop being rated by inversion of a second binary signal and receiving a second digital signal, and each logic AND gate delivering the second binary signal at a first input and delivering the output of one of the second flip-flops at a second input.

[0017] According to one embodiment, the second binary signal is equal to the first binary signal.

[0018] According to one embodiment, each rising edge of the second binary signal is synchronized with the falling edge of the first binary signal, and each falling edge of the second binary signal follows the rising edge of the second binary signal, with the rising edge of the second binary signal preceding each falling edge of the second binary signal by a constant duration.

[0019] One embodiment also provides a contactless reader card, including an antenna and electronic devices such as those previously defined. Attached Figure Description

[0020] The above features and advantages, as well as others, will be described in detail below with reference to the accompanying drawings, which are given by way of illustration rather than limitation, in which:

[0021] Figure 1 This is a block diagram of one embodiment of a remotely powered contactless card positioned near a terminal;

[0022] Figure 2 This is a timing diagram of the envelope of an embodiment of an electromagnetic signal sent by a terminal;

[0023] Figure 3 Is with Figure 1 Timing diagrams of various signals associated with embodiments of remotely powered contactless cards;

[0024] Figure 4 This is a block diagram of one embodiment of a remotely powered contactless card positioned near a terminal;

[0025] Figure 5 Is with Figure 4 Timing diagrams of various signals associated with embodiments of remotely powered contactless cards;

[0026] Figure 6 Is with Figure 4 An embodiment of a remotely powered contactless card; a schematic diagram of an embodiment of a remotely powered contactless card.

[0027] Figure 7 Is with Figure 6 A schematic diagram of an embodiment of the circuit associated with an embodiment of a remotely powered contactless card;

[0028] Figure 8 Is with Figure 6 A schematic diagram of an embodiment of the circuit associated with an embodiment of a remotely powered contactless card;

[0029] Figure 9 Is with Figure 6 Timing diagrams of various signals associated with embodiments of remotely powered contactless cards;

[0030] Figure 10 Is with Figure 4 Timing diagrams of various signals associated with embodiments of remotely powered contactless cards;

[0031] Figure 11 Is with Figure 4 An embodiment of a remotely powered contactless card; A schematic diagram of an embodiment of a remotely powered contactless card.

[0032] Figure 12 Is with Figure 11 An embodiment of a remotely powered contactless card; and a schematic diagram of an embodiment of a remotely powered contactless card; and

[0033] Figure 13 This is a timing diagram of a signal used to generate a delay according to one embodiment. Detailed Implementation

[0034] In the various figures, similar features are indicated by similar reference numerals. Specifically, common structural or functional features in various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties. For clarity, only steps and elements that aid in understanding the embodiments described herein are illustrated and described in detail.

[0035] Unless otherwise specified, when referring to two connected elements, this implies a direct connection without any intermediate elements other than conductors, and when referring to two coupled elements, this implies that the two elements can be connected, or that they can be coupled via one or more other elements. Furthermore, the terms "insulating" and "conductive" are considered herein to mean "electrically insulating" and "electrically conductive," respectively.

[0036] In the following description, when terms that define absolute position, such as “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or terms that define relative position, such as “above,” “below,” “up,” “down,” etc., or terms that define direction, such as “horizontal,” “vertical,” etc., are used, they refer to the display screen in the orientation of the figure or in its normal use position, unless otherwise stated.

[0037] Furthermore, a signal that alternates between a first constant state (e.g., a low state, labeled "0") and a second constant state (e.g., a high state, labeled "1") is called a "binary signal". The high and low states of different binary signals in the same electronic circuit may be different. In practice, a binary signal may correspond to a voltage or current that may not be constantly at a high or low level.

[0038] Unless otherwise stated, the expressions “approximately,” “about,” “substantially,” and “about” indicate within 10%, and preferably within 5%. Unless otherwise stated, ordinal numbers such as “first,” “second,” etc., are used only to distinguish elements from one another. In particular, these adjectives do not limit the described embodiments to a specific order of these elements.

[0039] Figure 1 The illustration shows a remotely powered contactless card 1 positioned near a terminal 3. Terminal 3 includes an antenna 5 and electronic circuitry 7. The contactless card 1 includes an antenna 9 coupled to a data processing circuitry 11 via a shaping circuitry 13. Terminal 3 permanently emits an electromagnetic field. Therefore, when the card 1 is near terminal 3, it is powered through the antenna 9 and is able to receive signal 15 and transmit signal 17.

[0040] Terminal 3 transmits an electromagnetic field, hereinafter referred to as the carrier, at a frequency of, for example, 13.56 MHz. The period during which the signal is transmitted from terminal 3 to card 1 is referred to as the polling phase. Terminal 3 modulates the carrier with a data signal, and the modulated carrier is received by antenna 9 of card 1. Processing circuit 11 then recovers the data signal. As an example, the transmission of the signal from terminal 3 to card 1 is performed by amplitude modulation of the carrier, specifically by 1-bit amplitude modulation as defined by the ISO / IEC 14443 standard. Shaping circuit 13 delivers the analog signal RXA obtained from the signal captured by antenna 9 to processing circuit 11. The analog signal RXA is demodulated by processing circuit 11 to determine the binary signal RX.

[0041] The period from signal transmission from card 1 to terminal 3 is referred to as the response phase, during which processing circuit 11 can change its current consumption. The current change in antenna 9 is converted into a carrier wave change, which is then detected by terminal 3.

[0042] Card 1 must detect the end of the polling phase to begin the response phase. According to one embodiment, during each polling phase, the electromagnetic field emitted by terminal 3 is "paused"; each pause corresponds to an interval during which the electromagnetic field has a minimum amplitude, for example, essentially zero.

[0043] Figure 2 The diagram illustrates the changes in the normalized envelope E of the electromagnetic field emitted by terminal 3 before, during, and immediately after the pause. The pause begins at time t1, and the amplitude of the envelope E decreases from a high level to a low level at time t2, essentially zero. From time t2 to time t3, the level remains low, and from time t3, the amplitude of the envelope E increases to a high level at time t4, with temporary oscillations observed near the high level.

[0044] Card 1 detects that the amplitude of envelope E begins to rise at time t3. The duration between time t3 and the start of the next response phase is called FDT (Frame Delay Time). The remote communication standard between terminal 3 and card 1 may impose a limit on the FDT duration that card 1 should adhere to; otherwise, terminal 3 will interrupt communication if the response phase has not yet started. This may be particularly suitable for banking applications, especially when the communication protocol is implemented, for example, at a rate of 106 kbits / s according to the Type A ISO / IEC 14443 standard, with anti-collision phases based on the card's response within a fixed delay.

[0045] Therefore, this forces time t3 to be correctly detected by card 1 so that the next response phase begins at the correct time. The determination of time t3 is performed by processing circuit 11 based on the signal RXA delivered by shaping circuit 13. If the signal captured by antenna 9 perfectly reproduces the electromagnetic field emitted by terminal 3, then shaping circuit 13 can deliver signal RXA that reproduces the envelope E. However, the signal captured by antenna 9 may present interference and therefore must be filtered, so in practice, signal RXA cannot perfectly reproduce the changes in envelope E.

[0046] Figure 3 The following diagrams, from top to bottom, illustrate: the timing diagram of the upper part of the electromagnetic field envelope E transmitted by the antenna 5 of terminal 3; the timing diagram of the upper part of the signal envelope E' captured by the antenna 9 of card 1, represented by a solid line; the timing diagram of the signal RXA delivered by the shaping circuit 13, represented by a dashed line; and the timing diagram of the signal RX delivered by the processing circuit 11 after demodulation of the signal RXA.

[0047] The envelope E' of the electromagnetic field of the signal captured by antenna 9 may oscillate during the pause. This oscillation needs to be filtered out so that it does not appear on signal RXA and so that processing circuit 11 does not deliver the binary signal RX with an incorrect value. This filtering causes signal RXA to rise at the end of the pause, which may be delayed relative to the rise of envelopes E and E'. Since the detection of the end of the pause is performed based on signal RXA, the detected rise time t3' of signal RXA may be after the rise time t3 of envelope E'.

[0048] According to one embodiment, an impedance is applied to antenna 9. In this embodiment, the impedance is purely resistive during each pause in the electromagnetic field. In this embodiment, the value of the resistive impedance is low enough to suppress the oscillation of the envelope E' of the signal captured by antenna 9. In this embodiment, the value of the resistive impedance is high enough to give the signal captured by antenna 9 significant dynamic characteristics, especially when the magnetic field increases again at the end of the pause.

[0049] Figure 4 It is similar to Figure 1The figure illustrates an embodiment of a remotely powered contactless card 20 arranged near terminal 3. Card 20 includes... Figure 1 The card 1 differs from other cards in that it also includes circuitry 30 for modifying the impedance as seen by antenna 9. According to one embodiment, impedance modification circuitry 30 receives signal RX. According to another embodiment, impedance modification circuitry 30 is deactivated except during pauses.

[0050] Figure 5 The following diagrams, from top to bottom, illustrate: the upper timing diagram of the envelope E of the electromagnetic field emitted by the antenna 5 of terminal 3; the timing diagram of the enable signal S5 of the resistance impedance delivered to the antenna 9 by the impedance modification circuit 30, which will be described in further detail below; the upper timing diagram of the envelope E' of the signal captured by the antenna 9 of card 20; and the timing diagram of the signal RX delivered by the processing circuit 11 for one embodiment of the circuit 30 that modifies the impedance seen through the antenna 9.

[0051] Figure 5 The time series diagram of the envelope E of the electromagnetic field in the figure and Figure 3 The same applies as shown. The timing diagram of the envelope E' of the signal captured by antenna 9 of card 20 does not show any wobbling. Then the signal RXA can essentially correspond to the envelope E'. Therefore, the determination of time t3 can be performed correctly.

[0052] Figure 6 It is used to obtain Figure 5 The timing diagram shown in the figure is an electrical diagram of an embodiment of the impedance modification circuit 30 of card 20, an antenna 9, and an embodiment of the shaping circuit 13.

[0053] According to one embodiment, the shaping circuit 13 includes: a capacitor C1, coupled in parallel with terminals AC1 and AC0 of the antenna 9; a rectifier bridge 31, for example, a diode bridge, including two inputs coupled to (preferably connected to) terminals AC1 and AC0 respectively, a first output O1 delivering the rectified signal VRECT, and a second output O2 coupled to a source of a low reference potential Gnd (e.g., ground of card 20); a capacitor C2 having a first plate coupled to (preferably connected to) the first output O1 of the rectifier bridge 31 and a second plate coupled to (preferably connected to) the source of the low reference potential Gnd; and a voltage divider bridge 32, which includes, for example, components connected in series with the rectifier bridge. The bridge 31 has two resistors R1 and R2 between its first output S and the source of the low reference potential Gnd; an insulated gate field-effect transistor T1, also known as, for example, a MOS transistor (metal-oxide-semiconductor) with an N-channel, whose drain is coupled to (preferably connected to) the first output O1 of the rectifier bridge 31 and whose source is coupled to (preferably connected to) the source of the low reference potential Gnd; and a differential amplifier 33, which includes a first input (+) coupled to (preferably connected to) the node N between resistors R1 and R2, a second input (-) receiving the reference voltage VREF, and a gate coupled to (preferably connected to) the output transistor T1.

[0054] The assembly of a voltage divider bridge 32, an amplifier 33, and a MOS transistor T1 forms a circuit 34 for controlling the impedance seen through the antenna 9. This circuit controls the impedance of the device with... Figure 6 The circuit 34 for controlling the impedance seen through antenna 9 in the structure shown corresponds to a fast antenna impedance manager circuit placed after rectifier bridge 31. However, the circuit 34 for controlling the impedance seen through antenna 9 can have different characteristics. Figure 4 The structure shown can be a fast antenna impedance manager placed before the rectifier bridge 31.

[0055] According to one embodiment, in Figure 6 In the embodiment illustrated, the impedance modification circuit 30 includes: a MOS transistor T2, for example having an N-channel, whose gate is coupled to (preferably connected to) the gate of transistor T1, whose source is coupled to (preferably connected to) the source of a low reference potential Gnd, and whose drain receives a current I_sense; an analog-to-digital converter 35 (ADC), rated by a clock signal RF_CLOCK, which includes an input coupled to (preferably connected to) the drain of transistor T2, and N outputs, each output delivering a first binary signal B1i, i being an integer varying from 1 to N, the first binary signal B1i forming a digital signal S1 with N bits, N being an integer greater than or equal to 1, for example varying from 1 to 20, and... Figure 6Taking an example of 3; N first flip-flops 36 (D), preferably of type D, each i-th flip-flop 36 varying from 1 to N is rated by a clock signal RF_CLOCK / 8, the frequency of which is equal to a divisor of the frequency of the clock signal RF_CLOCK, for example, one-eighth. They receive a first binary signal B1i and output a second binary signal B2i, which forms a second digital signal S2; N second flip-flops 37 (D), preferably of type D, each i-th flip-flop 37 varying from 1 to N is rated by a clock signal RF_CLOCK / 8, receives the second binary signal B2i, and outputs a third binary signal B3i, which forms a third digital signal S3; N third flip-flops 38 (D), preferably of type D, i varying from 1 to N... Each i-flip-flop 38 is rated by signal RXb, receives a third binary signal B3i, and outputs a fourth binary signal B4i, which forms a fourth digital signal S4; an inverter INV1, whose input receives signal RX and whose output delivers signal RXb; N logic gates 39 (AND), each logic gate implementing the logic AND function, each i-th logic gate 39 varying from 1 to N includes a first input receiving the fourth binary signal B4i and a second input receiving signal RXb, and outputs a fifth binary signal B5i, which forms a fifth digital signal S5; and a resistor digital-to-analog converter (resistor DAC) 40, which receives the fifth digital signal S5 and includes two output terminals AC0 and AC1 respectively coupled to (preferably connected to) antenna 9.

[0056] According to one embodiment, the resistor-to-analog converter 40 is a unary network converter, a binary network converter, and an R-2R network. Specifically, when the digital signal received as input is "0", the digital-to-analog converter 40 delivers a very high resistance value, preferably corresponding to an open-circuit infinite resistance value.

[0057] Figure 7 and Figure 8 An embodiment of a resistive digital-to-analog converter 40 is shown. Each of these digital-to-analog converters 40 includes a resistor and a switch SW, each switch SW being controlled by a binary signal B5. i One of the controls, where i varies from 1 to N. Each of these digital-to-analog converters 40 also includes two output terminals OUT1 and OUT2, between which a resistance value VRES delivered by the converter 40 is applied. According to one embodiment, as Figure 6As shown, terminal OUT1 can be coupled to (preferably connected to) terminal AC1 of antenna 9, and terminal OUT2 can be coupled to (preferably connected to) terminal AC0 of antenna 9. According to another embodiment, impedance modification circuit 30 may include first and second digital-to-analog converters 40, each receiving digital signal S5, the first digital-to-analog converter 40 applying a resistance value VRES between terminal AC1 of antenna 9 and the source of low reference potential Gnd, and the second digital-to-analog converter 40 applying a resistance value VRES between terminal AC2 of antenna 9 and the source of low reference potential Gnd.

[0058] exist Figure 7 In this configuration, the digital-to-analog converter 40 is a binary network type. This means it uses resistors with different values ​​of 1R, 2R, and 4R, each resistor value corresponding to each binary signal B5. i Binary weights. In Figure 8 In this example, the digital-to-analog converter 40 is a ladder network type. This means that the resistor network forms a ladder with a small number of basic resistance values. Specifically, the network can be of type R-2R with two basic resistance values ​​R and 2R.

[0059] Figure 6 The shaping circuit 13 shown operates as follows: The voltage across antenna 9 is rectified by rectifier bridge 31 and filtered by capacitor C2 and resistors R1 and R2. Amplifier 33 delivers a gate voltage to transistor T1, which is proportional to the difference between the voltage VN at node N (proportional to voltage VRECT) and the reference voltage VREF. Therefore, transistor T1 is more or less turned on depending on the difference between the voltage VN at node N and the reference voltage VREF.

[0060] Figure 6 The impedance modification circuit 30 shown operates as follows: The ratio K between the widths of transistors T1 and T2 is less than 1, for example, equal to 1 / 100. Transistors T1 and T2 are controlled by the same signal at their gates. The current I_sense flowing through transistor T2 is proportional to the current flowing through transistor T1. The analog-to-digital converter 35 delivers a digital signal S1 corresponding to the digital conversion of the current I_sense's strength.

[0061] The i-th flip-flop 36, whose i varies from 1 to N, is copied at its output to the binary signal B1 received as input at each rising edge of the signal RF_CLOCK / 8. i .

[0062] Therefore, the second binary signal B2 iA second digital signal S2 is formed, which corresponds to the sampling of the first digital signal S1 at a frequency equal to one-eighth of the frequency of the signal RF_CLOCK. Each i-th flip-flop 37 replicates at its output the binary signal B2 received as input at each rising edge of the signal RF_CLOCK / 8. i .

[0063] Therefore, the third binary signal B3 i A third digital signal S3 is formed, which corresponds to the second digital signal S2 within the delay caused by the operation of the second flip-flop 37. Each i-th flip-flop 38 replicates at its output the binary signal B3 received as input at each rising edge of the signal RXb. i .

[0064] Therefore, the fourth binary signal B4 i A fourth digital signal S4 is formed, which corresponds to the sampling of the third digital signal S3 at the rising edge of signal RXb (i.e., at the falling edge of signal RX). Each i-th AND logic gate 39 outputs a binary signal B5. i When signal RXb is "1" (i.e., when signal RX is "0"), it is equal to the binary signal B4 received as input. i And it is equal to "0" when the signal RXb is "0" (that is, when the signal RX is "1").

[0065] Therefore, the fifth binary signal B5 i A fifth digital signal S5 is formed. When signal RXb is "1" (i.e., when signal RX is "0"), the fifth digital signal S5 corresponds to the fourth digital signal S4, and when signal RXb is "0" (i.e., when signal RX is "1"), the fifth digital signal S5 is equal to "0". The digital-to-analog converter 40 provides a resistor with a value corresponding to the analog conversion of the digital signal S5.

[0066] Before the pause begins, the envelope E of the electromagnetic field received by antenna 9 is at its maximum, such that the signal RX delivered by processing circuit 11 is "1" and the signal RXb is "0". Therefore, the digital signal S5 is "0". When the digital signal received as input is "0", the digital-to-analog converter 40 outputs a resistance value corresponding to the input equal to "0", preferably a very high resistance value, preferably an infinite resistance value corresponding to an open circuit. When the pause of the electromagnetic field begins, the signal RX switches to "0" and the signal RXb switches to "1". The digital signal S5 becomes non-"0" and then corresponds to the value taken by the digital signal S1. This digital signal S5 is sent to the digital-to-analog converter 40, which outputs a resistance value VRES corresponding to the digital-to-analog conversion of the digital signal S5. Therefore, the resistance value VRES delivered by impedance modification circuit 30 during the pause depends on the electromagnetic field value at the point before the pause begins. At the end of the pause, the amplitude of the envelope E of the electromagnetic field received by antenna 9 increases. Signal RX switches to "1" and signal RXb switches to "0", therefore digital signal S5 switches back to "0". According to one embodiment, regardless of the actual value received as input, outside of the pause, impedance modification circuit 30 is disabled and digital-to-analog converter 40 outputs a resistance value corresponding to the input equal to "0", preferably a very high resistance value, preferably an infinite resistance value corresponding to an open circuit.

[0067] The first simulation has been performed. For the first simulation, processing circuit 11 and impedance modification circuit 30 have... Figure 6 The structure shown.

[0068] Figure 9 The following graphs, arranged from top to bottom according to the duration of the pause, illustrate: the curve showing the change in the envelope E of the electromagnetic field emitted by terminal 3; the curves showing the changes in signal B, signal RXA, and binary signal RX captured by antenna 9 without impedance modification circuit 30; the curves showing the changes in signal B', signal RXA', and binary signal RX' captured by antenna 9 with impedance modification circuit 30; and the curve showing the change in digital signal S5 after digital-to-analog conversion.

[0069] like Figure 9 As shown, the curve of the change of signal B captured by antenna 9 in the absence of impedance modification circuit 30 shows a swing during the pause, while no swing 30 is observed on curve B' in the presence of impedance modification circuit.

[0070] In the previously described embodiment, the duration for which the circuit 30 for modifying the impedance seen through the antenna 9 presents the resistance value VRES to the antenna 9 during a pause corresponds to the duration for which the signal RX is at "0". According to another embodiment of the impedance modification circuit 30, the duration for which the circuit 30 for modifying the impedance seen through the antenna 9 presents the resistance value VRES to the antenna 9 during a pause corresponds to a predetermined duration.

[0071] Figure 10 The illustration shows an embodiment of circuit 30 used to modify the impedance as seen through antenna 9, similar to... Figure 5 The timing diagram shows that the duration for which circuit 30 presents the resistance value VRES to antenna 9 during the pause corresponds to a predetermined duration.

[0072] The timing diagram of the envelope E of the electromagnetic field emitted by terminal 3 and Figure 3 The same applies as shown. The envelope E' of the electromagnetic field received by antenna 9 of card 20 does not exhibit oscillation. Therefore, signal RXA can essentially correspond to envelope E'.

[0073] The impedance value VRES presented to the antenna 9 by circuit 30 can be compared with the previous value at time tA. Figure 5 The same method described is used to execute the circuit. The end of circuit 30 presenting the impedance value VRES to antenna 9 can be executed after time tA elapses for a duration ΔT1.

[0074] Figure 11 This is an electrical diagram of one embodiment of the shaping circuit 13 and impedance modification circuit 30 of card 20, which enables the acquisition of Figure 10 The timing diagram is shown in the figure. Circuits 13 and 30 of card 20 have the same... Figure 6 The same structure is shown, except that there is no inverter INV1 and the third flip-flop 38 and logic gate 39 receive the binary signal load_ctrl delivered by circuit 50. The signal load_ctrl presents a rising edge synchronized with the falling edge of the signal RX at the start of the pause, and a falling edge following the rising edge after the duration ΔT1 has elapsed.

[0075] Figure 12An embodiment of circuit 50 for delivering the binary signal load_ctrl is illustrated. Circuit 50 includes: a current source 51, with a first terminal coupled (preferably connected) to the source of a low reference potential Gnd; a current mirror 52, including, for example, a P-channel MOS transistor T3, whose source is coupled (preferably connected) to the source of a high reference potential VDD, whose drain is coupled (preferably connected) to the second terminal of the current source 51, and whose gate is connected to the drain; and, for example, a P-channel MOS transistor T4, whose source is coupled (preferably connected) to the source of the high reference potential VDD, and whose drain is connected to the gate of transistor T3; and an inverter INV2, receiving the input signal RX, for example... Examples include, for instance, a P-channel MOS transistor T5, whose source is coupled to (preferably, connected to) the drain of transistor T4, whose drain is coupled to (preferably, connected to) the output of inverter INV2, and whose gate is coupled to (preferably, connected to) the input of inverter INV2; and, for instance, an N-channel MOS transistor T6, whose source is coupled to (preferably, connected to) the source of a low reference potential Gnd, whose drain is coupled to (preferably, connected to) the output of inverter INV2, and whose gate is coupled to (preferably, connected to) the input of inverter INV2; and a capacitor C3, having coupled to (preferably...)... The first plate of the inverter INV2 is connected to the output of the inverter C3, and the second plate is coupled to the source of the inverter C3 (preferably connected to the low reference potential Gnd). The voltage across the capacitor C3 is referred to as VC3. The inverter INV3, whose input is coupled to the first plate of the capacitor C3, is, for example, a MOS transistor T7 with a P-channel, whose source is coupled to the source of the inverter C3 (preferably connected to the high reference potential VDD), whose drain is coupled to the output of the inverter INV3, and whose gate is coupled to the input of the inverter INV2, and for example... A MOS transistor T8 with an N-channel has its source coupled (preferably connected to) a low reference potential Gnd, its drain coupled (preferably connected to) the output of inverter INV3, and its gate coupled (preferably connected to) the input of inverter INV2. The voltage between the output of inverter INV3 and the low reference potential Gnd is referred to as VSINV3. An inverter INV4 has its input receiving the signal RX. An AND logic gate 53 has its first input receiving the output of inverter INV4, its second input receiving the output of inverter INV3, and its output signal load_ctrl.

[0076] Circuit 50 operates as follows. Before the pause, signal RX is "1". Therefore, the first input of AND gate 53 is "0", and signal load_ctrl is "0". Furthermore, the voltage across capacitor C3 is essentially zero, capacitor C3 is discharged, and the output signal of inverter INV3 (and therefore the second input of AND gate 53) is "1". At the start of the pause, signal RX switches to "0". Therefore, the first input of AND gate 53 switches to "1". Capacitor C3 is discharged, and the output signal of inverter INV3 (and therefore the second input of AND gate 53) remains "1". Therefore, signal load_ctrl switches to "1". Capacitor C3 is charged, causing the voltage across it to increase. When the voltage across capacitor C3 is sufficiently high after a duration ΔT1, the output of inverter INV3 (and therefore the second input of AND gate 53) switches to "0". Therefore, signal load_ctrl switches to "0" at the end of duration ΔT1. When signal RX switches back to "1", capacitor C3 is discharged.

[0077] The second simulation has been performed. For the second simulation, circuit 50 has... Figure 12 The structure shown.

[0078] Figure 13 The graphs, arranged from top to bottom according to the duration of the pause, depict the following curves: the curve of signal RX; the curve of voltage change across capacitor C3; the curve of voltage VISIN3; and the curve of signal load_ctrl.

[0079] like Figure 13 As shown, the duration ΔT1 of the signal load_ctrl in state "1" specifically depends on the charging duration of capacitor C3, and therefore can be predetermined.

[0080] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0081] Finally, based on the functional indications provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

Claims

1. A method for processing amplitude-modulated analog signals, comprising: An amplitude-modulated analog signal associated with an electromagnetic field generated by an external device is received by an antenna capable of being coupled to an electronic device, the electromagnetic field having a minimum horizontal spacing; A demodulated signal is generated based on the amplitude-modulated analog signal, the demodulated signal comprising the rectified, filtered and demodulated signal of the amplitude-modulated analog signal; A binary signal is generated based on the demodulated signal; The maximum amplitude value of the electromagnetic field before the pause is determined based on the binary signal. as well as During the pause, a resistor is coupled to the antenna, the value of which is based on the maximum amplitude value.

2. The method of claim 1, wherein the coupling comprises coupling the resistor to the antenna in response to a change of the binary signal from a first state to a second state.

3. The method of claim 2, further comprising decoupling the resistor from the antenna in response to a change in the binary signal from the second state to the first state.

4. The method of claim 2, further comprising decoupling the resistor from the antenna in response to the end of a constant duration after the resistor has been coupled to the antenna.

5. The method according to claim 1, further comprising: The demodulated signal is converted into a first digital signal; A second digital signal is generated based on the first digital signal, and the second digital signal is equal to the first digital signal with a delay; Generate a third digital signal, the third digital signal having a constant digital value in response to the binary signal being in a first state, and the third digital signal having a digital value equal to the value of the second digital signal in response to the binary signal changing from the first state to a second state; and The third digital signal is converted into the value of the resistor.

6. An electronic device, comprising: A first circuit is configured to generate a demodulated signal based on an amplitude-modulated analog signal, the demodulated signal comprising a rectified, filtered, and demodulated signal of the amplitude-modulated analog signal, the amplitude-modulated analog signal being associated with an electromagnetic field generated by an external device and received by an antenna capable of being coupled to the electronic device, the electromagnetic field having a minimum horizontal spacing. The second circuit is configured to generate a binary signal based on the demodulated signal; as well as A third circuit is configured to couple a resistor to the antenna during a pause, the value of which is based on the maximum amplitude of the electromagnetic field before the pause, the maximum amplitude being determined based on the binary signal.

7. The electronic device of claim 6, wherein the third circuit is configured to couple the resistor to the antenna in response to a change in the binary signal from a first state to a second state.

8. The electronic device of claim 7, wherein the third circuit is configured to decouple the resistor from the antenna in response to a change in the binary signal from the second state to the first state.

9. The electronic device of claim 7, wherein the third circuit is configured to decouple the resistor from the antenna in response to the end of a constant duration after the resistor has been coupled to the antenna.

10. The electronic device of claim 6, wherein the third circuit comprises: An analog-to-digital converter (ADC) is configured to convert the demodulated signal into a first digital signal; A fourth circuit is configured to generate a second digital signal based on the first digital signal, the second digital signal being equal to the first digital signal with a delay; A fifth circuit is configured to generate a third digital signal that has a constant digital value in response to the binary signal being in a first state, and has a digital value equal to the value of the second digital signal in response to the binary signal changing from the first state to a second state. as well as A resistive digital-to-analog converter (DAC) is configured to convert the third digital signal into the value of the resistor.

11. The electronic device of claim 10, wherein the ADC is timed by a first clock signal, and wherein the fourth circuit includes a trigger circuit that is timed by a second clock signal, the frequency of the second clock signal being a divisor of the frequency of the first clock signal.

12. The electronic device of claim 10, wherein the fifth circuit comprises: A trigger circuit, timed by the inversion of a second binary signal, is configured to receive the second digital signal; as well as AND logic gates, each AND logic gate is configured as follows: Output the different bits of the multiple bits of the third digital signal. Receive the second binary signal at the first input, and The outputs of different flip-flops of the flip-flop circuit are received at the second input.

13. The electronic device of claim 12, wherein the second binary signal is equal to the binary signal.

14. The electronic device of claim 12, wherein each rising edge of the second binary signal is synchronized with a corresponding falling edge of the binary signal, and wherein each falling edge of the second binary signal follows the rising edge of the second binary signal, the rising edge of the second binary signal preceding each falling edge of the second binary signal by a constant duration.

15. A contactless reader card, comprising: The antenna is configured to receive an amplitude-modulated analog signal associated with an electromagnetic field generated by an external device, the electromagnetic field having a minimum horizontal spacing; A first circuit, coupled to the antenna, is configured to generate a demodulated signal based on the amplitude-modulated analog signal, the demodulated signal comprising a rectified, filtered, and demodulated signal of the amplitude-modulated analog signal; The second circuit is configured to generate a binary signal based on the demodulated signal; as well as A third circuit is configured to couple a resistor to the antenna during a pause, the value of which is based on the maximum amplitude of the electromagnetic field before the pause, the maximum amplitude being determined based on the binary signal.

16. The contactless reader card of claim 15, wherein the third circuit is configured to couple the resistor to the antenna in response to a change in the binary signal from a first state to a second state.

17. The contactless reader card of claim 16, wherein the third circuit is configured to decouple the resistor from the antenna in response to a change in the binary signal from the second state to the first state.

18. The contactless reader card of claim 16, wherein the third circuit is configured to decouple the resistor from the antenna in response to the end of a constant duration after the resistor has been coupled to the antenna.

19. The contactless reader card according to claim 16, wherein the third circuit comprises: An analog-to-digital converter (ADC) is configured to convert the demodulated signal into a first digital signal; A fourth circuit is configured to generate a second digital signal based on the first digital signal, the second digital signal being equal to the first digital signal with a delay; A fifth circuit is configured to generate a third digital signal that has a constant digital value in response to the binary signal being in a first state, and has a digital value equal to the value of the second digital signal in response to the binary signal changing from the first state to a second state. as well as A resistive digital-to-analog converter (DAC) is configured to convert the third digital signal into the value of the resistor.

20. The contactless reader card of claim 19, wherein the ADC is timed by a first clock signal, and wherein the fourth circuit includes a trigger circuit timed by a second clock signal, the frequency of the second clock signal being a divisor of the frequency of the first clock signal.

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