A shift register unit, a gate driving circuit and a display device

Abstract

The present disclosure provides a shift register unit, a gate drive circuit and a display device, and relates to the technical field of display. In the present disclosure, the oxide semiconductor layer of the oxide thin film transistor can be partitioned according to the total channel width and the channel length required by the oxide thin film transistor in the shift register unit, and the sum of the widths of each independent semiconductor branch divided is equal to the total channel width required. In this way, one oxide thin film transistor can realize the total channel width required by one or more semiconductor branches, ensure the normal operation of the oxide thin film transistor, so that the purpose of reducing the frame of the display device can be achieved by designing different oxide semiconductor layers for different oxide thin film transistors. At the same time, the smaller size of the semiconductor branch and the gap between the semiconductor branches can also be used for heat dissipation, thereby avoiding the failure of the oxide thin film transistor caused by the heat accumulation of the oxide semiconductor.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register unit, a gate driving circuit, and a display device. Background Technology

[0002] Oxide thin film transistors (Oxide TFTs) have high electron mobility and low leakage current characteristics, and can be used in display products with high resolution, high refresh rate, low power consumption, low frequency drive, and large size to meet the ever-increasing display requirements.

[0003] The semiconductor region in an oxide thin-film transistor is an oxide semiconductor layer. The heat generated in the semiconductor region can cause the threshold voltage of the oxide thin-film transistor to drift too quickly, which can lead to the failure of the oxide thin-film transistor. Summary of the Invention

[0004] This disclosure discloses a shift register unit located on a substrate of a display panel in a non-display area, comprising multiple oxide thin-film transistors. Each oxide thin-film transistor includes an oxide semiconductor layer and source and drain electrodes connected to and spaced apart from the oxide semiconductor layer. The unit is characterized by...

[0005] At least a portion of the oxide thin-film transistors have multiple branches at their source and drain; wherein the source includes multiple source branches extending along a first direction, and the drain includes multiple drain branches extending along the first direction; the source branches and drain branches are arranged facing each other and are sequentially intersected in a second direction;

[0006] The oxide semiconductor layer has at least one or more spaced and parallel semiconductor branches, each semiconductor branch extending in a second direction perpendicular to the drain extension direction and overlapping and electrically connected with the source and drain branches, and the width of the semiconductor branch overlapping with any adjacent source and drain branches is the distance W from one end of the semiconductor branch to the other end in the first direction.

[0007] In this embodiment, at least some of the oxide thin-film transistors are multiple oxide thin-film transistors, and the widths of the semiconductor branches belonging to different oxide thin-film transistors are not exactly the same.

[0008] Optionally, in the at least partially oxide thin-film transistor, the width W of the semiconductor branch is not less than 3 μm and not more than 60 μm.

[0009] Optionally, the shift register unit includes a pull-down control circuit, which includes a first oxide thin-film transistor located between the pull-down node and the high-level reference voltage terminal, and a second oxide thin-film transistor located between the pull-down node and the low-level reference voltage terminal.

[0010] Each oxide thin-film transistor satisfies the following formula: W 总 =D 沟道总数 *W;

[0011] W is the width of a semiconductor branch, D 沟道总数 W is the sum of the number of channels in an oxide thin-film transistor, representing the semiconductor branches between each source branch and the adjacent drain branch. 总 This is the total width of the channel;

[0012] W of the first oxide thin film transistor 总 and W with the second oxide thin film transistor 总 The ratio is between 0.05 and 0.17.

[0013] Optionally, the W of the first oxide thin-film transistor 总 The W of the second oxide thin-film transistor is not less than 3μm. 总 No larger than 60μm.

[0014] Optionally, the pull-down control circuit has one or two pull-down nodes, the number of the first oxide thin film transistors is one or two oxide thin film transistors connected to the pull-down nodes one by one, and the number of the second oxide thin film transistors is one or two oxide thin film transistors connected to the pull-down nodes one by one.

[0015] The two first oxide thin film transistors have the same channel length, the same width of semiconductor branches, the same number of semiconductor branches, and the same spacing between adjacent semiconductor branches;

[0016] The two second oxide thin-film transistors have the same channel length, the same width of semiconductor branches, the same number of semiconductor branches, and the same spacing between adjacent semiconductor branches.

[0017] Optionally, each of the first oxide thin film transistors has one semiconductor branch, one source branch and one drain branch, the width of the semiconductor branch is 3-6 μm, and the width of the semiconductor branch is the total width of the channel of the first oxide thin film transistor.

[0018] Optionally, the W of the second oxide thin-film transistor 总The thickness is between 37 and 43 μm; the second oxide thin-film transistor has four semiconductor branches, two source branches, and one drain branch. 沟道总数 There are eight, and the width of one semiconductor branch is (1 / 8)*W 总 The gap between semiconductor branches is between 6 and 10 μm;

[0019] The semiconductor branch extends from one source branch through the drain branch to another source branch, contacting both the source branch and the drain branch; or

[0020] The W of the second oxide thin film transistor 总 The thickness is between 48 and 52 μm; the second oxide thin-film transistor has one semiconductor branch, two source branches, and one drain branch. Each semiconductor branch extends from one source branch through the drain branch to another source branch, contacting both the source and drain branches. The width of each semiconductor branch is W of the second oxide thin-film transistor. 总 One-half of D 沟道总数 There are two semiconductor branches, and the width of the branches is between 24 and 26 μm.

[0021] Optionally, the shift register unit includes a third oxide thin-film transistor located between the pull-down node and the low-level reference voltage terminal. The gate of the third oxide thin-film transistor is connected to the input terminal of the shift register unit, and the source and drain of the third oxide thin-film transistor are connected to the pull-down node and the low-level reference voltage terminal, respectively.

[0022] The number of the third oxide thin-film transistors is one or two;

[0023] Each of the third oxide thin-film transistors includes a source branch, a drain branch, and a semiconductor branch, wherein the width W of the semiconductor branch is between 18 and 22 μm.

[0024] Optionally, the shift register unit includes a fourth oxide thin-film transistor, wherein the source and drain of the fourth oxide thin-film transistor are connected to a pull-up node and a low-level reference voltage terminal, respectively, and the gate is connected to a pull-down node;

[0025] The number of the fourth oxide thin-film transistor is one or two;

[0026] The fourth oxide thin-film transistor has one to two semiconductor branches, with two source branches and two drain branches each. 沟道总数 Three or six;

[0027] The semiconductor branch has two branches, with a width between 20 and 25 μm and a gap between the branches between 10 and 14 μm; or it has one branch, with a width between 40 and 50 μm.

[0028] Optionally, the shift register unit includes a fifth oxide thin-film transistor, the source and drain of which are connected to the first output terminal and the low-level reference voltage terminal of the shift register unit, respectively, and the gate is connected to a pull-down node.

[0029] The number of the fifth oxide thin-film transistor is one or two;

[0030] Each of the fifth oxide thin-film transistors includes a source branch, a drain branch, and a semiconductor branch, wherein the width W of the semiconductor branch is between 8 and 12 μm.

[0031] Optionally, the shift register unit includes a sixth oxide thin-film transistor, the source and gate of which are respectively connected to the input terminal of the shift register unit, and the drain is connected to a pull-up node.

[0032] The sixth oxide thin-film transistor is one in number, and it includes three source branches and two drain branches. 沟道总数 Four or eight;

[0033] The semiconductor branch has two branches, with a branch width W between 15 and 20 μm and a gap between the branches between 10 and 14 μm; or the semiconductor branch has one branch, with a branch width W between 30 and 40 μm.

[0034] Optionally, the shift register unit includes a seventh oxide thin-film transistor, the source and drain of which are connected to the pull-up node and low-level reference voltage terminal of the shift register unit, respectively, and the gate is connected to the frame reset terminal of the shift register unit.

[0035] The seventh oxide thin-film transistor is one in number, and the seventh oxide thin-film transistor includes a source branch, a drain branch, and a semiconductor branch, the width W of which is between 8 and 12 μm.

[0036] Optionally, the shift register unit includes an eighth oxide thin-film transistor, the source and drain of which are connected to the pull-up node and low-level reference voltage terminal of the shift register unit, respectively, and the gate is connected to the first reset terminal of the shift register unit.

[0037] The number of the eighth oxide thin-film transistors is one, and the eighth oxide thin-film transistor includes a source branch, a drain branch, and a semiconductor branch, the width W of which is between 22 and 28 μm.

[0038] Optionally, the shift register unit includes a ninth oxide thin-film transistor, the source and drain of which are connected to the second output terminal and the low-level reference voltage terminal of the shift register unit, respectively, and the gate is connected to a pull-down node.

[0039] The number of the ninth oxide thin-film transistor is one or two;

[0040] Each of the ninth oxide thin-film transistors has one or two semiconductor branches, with one source branch and one drain branch each. 沟道总数 One or two;

[0041] The semiconductor branch has two branches, with a branch width W between 18 and 22 μm and a gap between the branches between 6 and 10 μm; or the semiconductor branch has one branch, with a branch width W between 36 and 44 μm.

[0042] Optionally, the shift register unit includes a tenth oxide thin-film transistor, the source and drain of which are connected to the clock signal terminal and the first output terminal of the shift register unit, respectively, and the gate is connected to a pull-up node.

[0043] The number of the tenth oxide thin-film transistor is one or two;

[0044] The tenth oxide thin-film transistor includes six source branches and five drain branches, as well as two semiconductor branches, D 沟道总数 Ten or twenty;

[0045] The semiconductor branch has two branches, with a branch width W between 18 and 22 μm and a gap between the branches between 10 and 14 μm; or the semiconductor branch has one branch, with a branch width W between 36 and 44 μm.

[0046] Optionally, the shift register unit includes an eleventh oxide thin-film transistor, the source and drain of which are connected to the clock signal terminal and the second output terminal of the shift register unit, respectively, and the gate is connected to a pull-up node.

[0047] The number of the eleventh oxide thin-film transistor is one, and the eleventh oxide thin-film transistor includes seven source branches, seven drain branches, and sixteen semiconductor branches, D 沟道总数There are 120 semiconductor branches, with the width W of the semiconductor branches ranging from 3 to 6 μm and the gap between the semiconductor branches ranging from 6 to 10 μm.

[0048] The length of the eight semiconductor branches in the eleventh oxide thin film transistor that are far from the display area of ​​the display panel along the extension direction of the semiconductor branches is greater than the length of the eight semiconductor branches in the eleventh oxide thin film transistor that are close to the display area of ​​the display panel along the extension direction of the semiconductor branches.

[0049] In the eleventh oxide thin-film transistor, among the eight semiconductor branches away from the display area of ​​the display panel, each semiconductor branch has 13 channels, and in the eight semiconductor branches close to the display area of ​​the display panel, each semiconductor branch has 12 channels.

[0050] Optionally, the shift register unit includes a twelfth oxide thin-film transistor, the source and drain of which are connected to the second output terminal and the low-level reference voltage terminal of the shift register unit, respectively, and the gate is connected to the second reset terminal of the shift register unit.

[0051] The number of the twelfth oxide thin-film transistors is one, and the twelfth oxide thin-film transistor includes a source branch, a drain branch, and a semiconductor branch, the width W of which is between 18 and 22 μm.

[0052] Optionally, the gate of the oxide thin-film transistor extends along the extension direction of the corresponding semiconductor branch and overlaps with the semiconductor branch.

[0053] Optionally, at least a portion of the oxide thin-film transistor's gate includes one or more gate branches, each gate branch corresponding to at least one semiconductor branch, and one gate branch extends along the extension direction of a corresponding semiconductor branch and overlaps with the semiconductor branch; the gate branches belonging to one oxide thin-film transistor are electrically connected to each other.

[0054] Optionally, the sum of the widths of the gate branches and the semiconductor branches belonging to one of the oxide thin-film transistors is slightly greater than the sum of the widths of the semiconductor branches.

[0055] Optionally, it may also include one or more dummy electrodes;

[0056] The dummy electrode is located between at least some adjacent source and drain branches of at least a portion of the oxide thin-film transistor. The dummy electrode is formed using the same film pattern as the source and drain branches. The dummy electrode is not electrically connected to any conductive pattern.

[0057] Optionally, at least the first oxide thin-film transistor, the second oxide thin-film transistor, and the third oxide thin-film transistor in the shift register unit are located in the frame region of the substrate of the display panel;

[0058] The source and drain branches of the first oxide thin-film transistor, the second oxide thin-film transistor, and the third oxide thin-film transistor extend along the edge direction perpendicular to the substrate;

[0059] The first oxide thin-film transistor and the second oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate;

[0060] The first oxide thin-film transistor and the third oxide thin-film transistor are each one, and are both located on the same side of the second oxide thin-film transistor; or the first oxide thin-film transistor and the third oxide thin-film transistor are each two, one pair of the first oxide thin-film transistors and the third oxide thin-film transistors are located on one side of the second oxide thin-film transistor, and the other pair of the first oxide thin-film transistors and the third oxide thin-film transistors are located on the other side of the second oxide thin-film transistor;

[0061] The pair of first oxide thin-film transistors and the third oxide thin-film transistor located on one side of the second oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate, and the other pair of first oxide thin-film transistors and the third oxide thin-film transistor located on the other side of the second oxide thin-film transistor are arranged sequentially along the edge direction of the substrate; the two pairs of first oxide thin-film transistors and the third oxide thin-film transistors are arranged sequentially along the edge direction of the substrate.

[0062] Optionally, there are two of each of the first oxide thin-film transistor, the second oxide thin-film transistor, and the third oxide thin-film transistor;

[0063] One of the first oxide thin-film transistors, the electrode terminals of the shift register unit, another of the first oxide thin-film transistors, and one of the third oxide thin-film transistors are arranged in a row along the edge of the substrate.

[0064] The third oxide thin-film transistor, the second oxide thin-film transistor, the second oxide thin-film transistor, and the electrode terminals of the shift register unit are arranged in a row along the edge direction of the substrate.

[0065] Optionally, the sixth oxide thin-film transistor, the seventh oxide thin-film transistor, and the ninth oxide thin-film transistor are arranged sequentially along the edge direction of the substrate;

[0066] The sixth oxide thin-film transistor, the eighth oxide thin-film transistor, and the ninth oxide thin-film transistor are arranged sequentially along the edge direction of the substrate;

[0067] The seventh oxide thin-film transistor and the eighth oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate;

[0068] The fifth oxide thin-film transistor and the sixth oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate. The fifth oxide thin-film transistor and the seventh oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate. The fifth oxide thin-film transistor and the eighth oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate. The fifth oxide thin-film transistor and the ninth oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate.

[0069] Optionally, there are two fifth oxide thin-film transistors, and the electrode terminals of the shift register unit, one fifth oxide thin-film transistor, and the other fifth oxide thin-film transistor are arranged in a row along the edge direction of the substrate.

[0070] Optionally, the tenth oxide thin-film transistor and the eleventh oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate, and the tenth oxide thin-film transistor and the twelfth oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate.

[0071] The eleventh oxide thin-film transistor and the twelfth oxide thin-film transistor are arranged sequentially along the edge direction of the substrate.

[0072] Optionally, the electrode terminals of the shift register unit and the tenth oxide thin-film transistor are arranged in a row along the edge direction of the substrate.

[0073] This disclosure also discloses a gate drive circuit including multiple cascaded shift register units, wherein the shift register units are the shift register units described above.

[0074] This disclosure also discloses a display device, including a pixel circuit and the gate driving circuit described above.

[0075] Compared with the prior art, this disclosure includes the following advantages:

[0076] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0077] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0078] Figure 1 A top view of the membrane layer of a shift register unit according to an embodiment of the present disclosure is shown;

[0079] Figure 2 A circuit diagram corresponding to a shift register unit according to an embodiment of the present disclosure is shown;

[0080] Figure 3 Experimental voltage results for a portion of a node in a shift register unit according to an embodiment of this disclosure are shown;

[0081] Figure 4 The diagram shows the output waveform of a shift register unit according to an embodiment of the present disclosure;

[0082] Figure 5 A top view of the membrane layer of another shift register unit according to an embodiment of the present disclosure is shown;

[0083] Figure 6 A partial cross-sectional view of a display device according to an embodiment of the present disclosure is shown;

[0084] Figure 7 A top view of the membrane layer of another shift register unit according to an embodiment of the present disclosure is shown;

[0085] Figure 8 A schematic diagram of a dummy electrode according to an embodiment of the present disclosure is shown. Specific Implementation

[0086] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0087] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The directional terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships based on the accompanying drawings; these relative positional relationships may also change accordingly when the absolute position of the described objects changes.

[0088] Table 1 shows a parameter comparison between polycrystalline silicon and oxide, where the polycrystalline silicon is a-Si and the oxide is IGZO (indium gallium zinc oxide). Referring to Table 1, oxide exhibits higher mobility, lower leakage current (Ioff, also known as off-state current), and better uniformity, making it suitable for display products with higher PPI (pixel density). When using oxide as a semiconductor material, it is necessary to avoid the impact of heat generation on the semiconductor.

[0089] Table 1

[0090] a-Si IGZO <![CDATA[Mobility (cm 2 / V.S)]]> ＜1 1～50 Ion (on-state current) / Ioff (leakage current) <![CDATA[10 6 ]]> <![CDATA[10 8 ]]> Uniformity good good Applicable resolution ≤350PPI ≤450PPI

[0091] Figure 1 A top view of a shift register unit (Gate On Array, GOA) according to an embodiment of this disclosure is shown, which is used to drive pixel circuitry. (Refer to...) Figure 1 The shift register unit 1000 is located on the substrate of the display panel in the non-display area and includes multiple oxide thin film transistors M. Each oxide thin film transistor M includes an oxide semiconductor layer 30 and a source 10 and a drain 20 connected to and spaced apart from the oxide semiconductor layer 30.

[0092] At least some of the oxide thin film transistors have a source 10 and a drain 20 each having multiple branches; wherein the source 10 includes multiple source branches 101 extending along a first direction D1, and the drain 20 includes multiple drain branches 201 extending along the first direction D1; the source branches 101 and drain branches 201 are arranged facing each other and are arranged in a crisscrossing manner in a second direction D2.

[0093] The oxide semiconductor layer 30 has at least one or more spaced and parallel semiconductor branches 301, each semiconductor branch 301 extending in a second direction perpendicular to the extension direction of the drain 20 and overlapping and electrically connected with each source branch 101 and drain branch 201. The width of the semiconductor branch 301 overlapping with any adjacent source branch 101 and drain branch 201 is the distance W from one end of the semiconductor branch 301 to the other end in the first direction D1.

[0094] Among them, at least some oxide thin film transistors M are multiple oxide thin film transistors, and the width W of the semiconductor branches 301 belonging to different oxide thin film transistors M is not exactly the same.

[0095] In practical applications, the required oxide semiconductor width W can be determined based on the oxide thin-film transistor M. 总 The oxide semiconductor layer of the oxide thin-film transistor M is divided into one or more semiconductor branches, and the sum of the widths W of each discrete semiconductor branch is equal to W0. 总 Thus, an oxide thin-film transistor can achieve the required total channel width W through one or more semiconductor branches. 总 This ensures the normal operation of the oxide thin-film transistor (MT), allowing for the reduction of display device bezels by designing different oxide semiconductor layers for different MTs. Simultaneously, the smaller semiconductor branches and the gaps between them can be used for heat dissipation, thus preventing MT failure caused by heat accumulation in the oxide semiconductor.

[0096] In some alternative implementations, the oxide semiconductor layer may be an IGZO semiconductor layer.

[0097] Optionally, in some embodiments, at least a portion of the oxide thin-film transistor M has a semiconductor branch 301 with a width W of not less than 3 μm and not more than 60 μm.

[0098] The width of the gate of the oxide thin film transistor M determines the curing effect of the encapsulant in the non-display area. The width of the gate is related to the width of the oxide semiconductor layer (i.e., the width of the semiconductor branch). Therefore, when the width W of the semiconductor branch 301 is not less than 3μm and not more than 60μm, the gate width can be slightly larger than 60μm at most. In this way, the curing effect of the encapsulant in the non-display area can be guaranteed.

[0099] Figure 2 for Figure 1 The circuit diagram corresponding to the shift register unit shown is referenced. Figure 2 Optionally, in some embodiments, the shift register unit includes a pull-down control circuit 300, which includes a first oxide thin-film transistor M5 located between the pull-down node PD and the high-level reference voltage terminal VDD, and a second oxide thin-film transistor M6 located between the pull-down node PD and the low-level reference voltage terminal LVGL.

[0100] Each oxide thin-film transistor satisfies the following formula: W 总 =D 沟道总数 *W;

[0101] W is the width of a semiconductor branch, D 沟道总数 W is the sum of the number of channels in an oxide thin-film transistor, representing the semiconductor branches between each source branch and the adjacent drain branch. 总 This is the total width of the channel;

[0102] The W of the first oxide thin-film transistor M5 总 and W with the second oxide thin film transistor M6 总 The ratio is between 0.05 and 0.17.

[0103] In this configuration, the source and gate of the first oxide thin-film transistor M5 are connected to the high-level reference voltage terminal VDD, and the drain is connected to the pull-down node PD, respectively. The source and drain of the second oxide thin-film transistor M6 are connected to the pull-down node PD and the low-level reference voltage terminal LVGL, respectively, and the gate is connected to the pull-up node PU.

[0104] In some embodiments, the shift register unit may include an input circuit 100, a reset circuit 200, a pull-down control circuit 300, a pull-down circuit 400, and an output circuit 500. (The following will use...) Figure 2 The shift register unit of the 18T1C (18 oxide thin film transistors, 1 capacitor) architecture shown is used as an example for detailed explanation. Each oxide thin film transistor in the 18T1C shift register unit is an oxide thin film transistor with oxide semiconductor provided in this disclosure.

[0105] Reference Figure 2 The input circuit 100 includes an oxide thin-film transistor M1, which can control the voltage of the pull-up node PU in response to an input signal from the input terminal INPUT.

[0106] Reference Figure 2 The reset circuit 200 includes oxide thin-film transistors M2, M4 and M15. The reset circuit 200 can reset the pull-up node PU in response to the reset signal from the first reset terminal RST_1, reset the second output terminal OUT_2 in response to the reset signal from the second reset terminal RST_2, and reset the pull-up node PU in response to the frame reset signal from the frame reset terminal TGOA_RST.

[0107] Reference Figure 2 The pull-down circuit 400 includes oxide thin-film transistors M8, M12 and M13. The pull-down circuit 400 can pull down the voltage of the pull-up node PU, the voltage of the second output terminal OUT_2 and the voltage of the first output terminal OUT_1 in response to the effective voltage of the pull-down node PD.

[0108] Reference Figure 2 The output circuit 500 consists of oxide thin-film transistors M3 and M11 and capacitor C1. This output circuit 500 can respond to the clock signal from the clock signal terminal CLK, outputting the clock signal to the first output terminal OUT_1 and the second output terminal OUT_2, thus providing a gate drive signal to the pixel circuit in the row where the shift register unit is located. The output circuit 500 can also respond to the clock signal from the clock signal terminal CLK, providing a reset signal to the next-level shift register unit and an input signal to the next-level shift register unit.

[0109] Reference Figure 2 The pull-down control circuit 300 includes oxide thin-film transistors M5, M6, and M7. This circuit can control the voltage of the pull-down node PD in response to a first power supply signal at the first power supply terminal VDD, an input signal at the input terminal INPUT, the voltage of the pull-up node PU, and a second power supply signal at the second power supply terminal LVGL. Oxide thin-film transistor M5 is the same as the first oxide thin-film transistor M5 mentioned above, and oxide thin-film transistor M6 is the same as the second oxide thin-film transistor M6 mentioned above.

[0110] Among them, the total channel width W of the first oxide thin film transistor M5 总 The total channel width W of the second oxide thin-film transistor M6 总 The ratio can be greater than or equal to 1:8.

[0111] Optionally, the W of the first oxide thin-film transistor 总Not less than 3μm, W of the second oxide thin film transistor 总 No larger than 60μm.

[0112] Experiments showed that the semiconductor width ratio of oxide thin-film transistors M5 and M6 (represented as M5 / 6 in the chart) has a significant impact on the maintenance of the bootstrap voltage of the pull-up node PU. Relevant experimental results can be found in [link to relevant experimental results]. Figure 3 Table 2 below also shows the highest point of bootstrap voltage and PU retention rate data of the pull-up node PU when using different semiconductor width ratios (1:6, 1:7, 1:8, 1:10, 1:12 and 1:14) of M5 and M6 respectively. Figure 3 In Figure 3 Figure a shows the waveforms of the pull-up node PU and the pull-down node PD when using different semiconductor width ratios (1:6, 1:8, 1:10, 1:12, and 1:14) for M5 and M6 respectively. Figure 3 b、 Figure 3 c. Figure 3 d and Figure 3 e is Figure 3 A detailed view of the local waveform of a.

[0113] Table 2

[0114]

[0115] Reference Figure 3 b. When the semiconductor width ratios of M5 and M6 are different, the low level of the pull-down node PD is around -10V or -11V, refer to... Figure 3 d. When the semiconductor width ratios of M5 and M6 are different, the high-level phase of the pull-down node PD is basically the same. Therefore, when the semiconductor width ratios of M5 and M6 are different, there is basically no adverse effect on the voltage of the pull-down node PD.

[0116] Reference Figure 3 a. The pull-up node PU boots up after a period of high level. (Refer to...) Figure 3 e. When the semiconductor width ratios of M5 and M6 are different, the high-level phase before the pull-up node PU boots up differs. Specifically, when M5 / 6 = 1:6, the high-level phase before the pull-up node PU boots up is significantly reduced. (Refer to...) Figure 3As shown in Table c and Table 2, when the semiconductor width ratio of M5 and M6 is different, the bootstrap peak voltage and PU retention rate of the pull-up node PU also differ. Specifically, when M5 / 6 < 1:8, the PU retention rate is below 88%, while when M5 / 6 ≥ 1:8, the PU retention rate is above 90%. In practical applications, the PU retention rate needs to be maintained above 88%; otherwise, differences in the output of shift register units in different rows will occur. Therefore, in this embodiment, the semiconductor width ratio of M5 and M6 needs to be greater than or equal to 1:8. When it is less than 1:8, the pull-up node PU voltage is prone to insufficient retention.

[0117] Figure 4 The output waveform of the 18T1C shift register unit is shown below. Figure 4 The time reliability test shows that the OUT_1 output waveform of the 18T1C shift register unit is basically the same at 100H, 200H, 500H, 1000H and 5000H respectively, and there is no abnormality in the noise part. This shows that the 18T1C shift register unit can work normally after the semiconductor design disclosed in this paper.

[0118] Alternatively, in some embodiments, the total channel width W of the first oxide thin-film transistor M5 is... 总 The total channel width W of the second oxide thin-film transistor M6 总 The ratio can be less than or equal to 1:14. Wherein, the total channel width W of the first oxide thin-film transistor M5 and the second oxide thin-film transistor M6... 总 The ratio does not need to be too large while meeting the voltage holding requirements of the pull-up node PU. This reduces the space occupied by the shift register unit and avoids waste of oxide thin-film transistor material. Considering the frame lifetime, in some specific embodiments, the total channel width W of the first oxide thin-film transistor M5 and the second oxide thin-film transistor M6 is... 总 The ratio can be 1:8.

[0119] Optionally, the pull-down control circuit has one or two pull-down nodes, the number of the first oxide thin film transistors is one or two oxide thin film transistors connected to the pull-down nodes one-to-one, and the number of the second oxide thin film transistors is one or two oxide thin film transistors connected to the pull-down nodes one-to-one.

[0120] The two first oxide thin film transistors have the same channel length, the same width of semiconductor branches, the same number of semiconductor branches, and the same spacing between adjacent semiconductor branches;

[0121] The two second oxide thin-film transistors have the same channel length, the same width of semiconductor branches, the same number of semiconductor branches, and the same spacing between adjacent semiconductor branches.

[0122] That is, in some embodiments, the shift register unit may include two pull-down nodes PD and two pull-down control circuits 300, with the pull-down control circuits 300 connected one-to-one with the pull-down nodes PD, and the two pull-down control circuits 300 used to work alternately.

[0123] In some embodiments, the shift register unit can be a dual VDD architecture, that is, the shift register unit can include two high-level reference voltage terminals VDD (e.g., Figure 2 The effective levels of VDD_A and VDD_B alternate, thus enabling the two pull-down control circuits 300 to operate alternately. Correspondingly, the shift register unit may also include two pull-down nodes PD (such as...). Figure 2 The circuit includes PD_A and PD_B, and two pull-down control circuits 300, where the pull-down control circuit 300, the pull-down node PD, and the high-level reference voltage terminal VDD are all connected in a one-to-one correspondence. Specifically, oxide thin-film transistor M5 is further divided into oxide thin-film transistors M5A and M5B, oxide thin-film transistor M6 is further divided into oxide thin-film transistors M6A and M6B, and oxide thin-film transistor M7 is further divided into oxide thin-film transistors M7A and M7B. In addition, since there are two pull-down nodes PD, oxide thin-film transistors M8, M12, and M13 in the pull-down circuit 400 can also be further divided into oxide thin-film transistors M13A and M13B.

[0124] In some alternative embodiments, such as Figure 1 Each first oxide thin film transistor M5 has one semiconductor branch, with one source branch and one drain branch. The width of the semiconductor branch is 3-6 μm, and the width of the semiconductor branch is the total width of the channel of the first oxide thin film transistor M5.

[0125] In some alternative embodiments, such as Figure 1 W of the second oxide thin film transistor 总 The thickness is between 37 and 43 μm; the second oxide thin-film transistor has four semiconductor branches, two source branches, and one drain branch. 沟道总数 There are eight, and the width of one semiconductor branch is (1 / 8)*W 总 The gap between semiconductor branches is between 6 and 10 μm;

[0126] A semiconductor branch extends from one source branch through a drain branch to another source branch, making contact with both the source and drain branches respectively; or

[0127] W of the second oxide thin-film transistor 总 The width is between 48 and 52 μm; in one case, the second oxide thin-film transistor has one semiconductor branch, two source branches, and one drain branch. One semiconductor branch extends from one source branch through a drain branch to another source branch, contacting both the source and drain branches. In another case, the width of the semiconductor branch is W of the second oxide thin-film transistor. 总 One-half of D 沟道总数 There are two, and the width of the semiconductor branches is between 24 and 26 μm.

[0128] Optionally, in some embodiments, the shift register unit includes a third oxide thin film transistor M7 located between the pull-down node PD and the low-level reference voltage terminal LVGL. The gate of the third oxide thin film transistor M7 is connected to the input terminal INPUT of the shift register unit, and the source and drain of the third oxide thin film transistor M7 are connected to the pull-down node PD and the low-level reference voltage terminal LVGL, respectively.

[0129] The number of third oxide thin-film transistors M7 is one or two;

[0130] Each third oxide thin-film transistor M7 includes a source branch, a drain branch, and a semiconductor branch, with the width W of the semiconductor branch being between 18 and 22 μm.

[0131] In addition to the oxide thin-film transistors mentioned above, other oxide thin-film transistors in the shift register unit can also be customized with oxide semiconductor layers, which will be described in detail below.

[0132] In some embodiments, the shift register unit includes a fourth oxide thin film transistor M8, the source and drain of which are connected to the pull-up node PU and the low-level reference voltage terminal LVGL, respectively, and the gate is connected to the pull-down node PD.

[0133] The number of fourth oxide thin-film transistors M8 is one or two;

[0134] The fourth oxide thin-film transistor M8 has one to two semiconductor branches, with two source branches and two drain branches each. 沟道总数 Three or six;

[0135] The semiconductor branch has two branches, with a width between 20 and 25 μm and a gap between the branches between 10 and 14 μm; or it has one branch, with a width between 40 and 50 μm.

[0136] In some embodiments, the shift register unit includes a fifth oxide thin film transistor M12, the source and drain of the fifth oxide thin film transistor M12 are respectively connected to the first output terminal OUT_1 and the low-level reference voltage terminal LVGL of the shift register unit, and the gate is connected to the pull-down node PD.

[0137] The number of fifth oxide thin-film transistors M12 is one or two;

[0138] Each fifth oxide thin-film transistor M12 includes a source branch, a drain branch, and a semiconductor branch, with the width W of the semiconductor branch being between 8 and 12 μm.

[0139] In some embodiments, the shift register unit includes a sixth oxide thin film transistor M1, the source and gate of the sixth oxide thin film transistor M1 are connected to the input terminal INPUT of the shift register unit, and the drain is connected to the pull-up node PU.

[0140] The sixth oxide thin-film transistor M1 has one component, which includes three source branches and two drain branches. 沟道总数 Four or eight;

[0141] The semiconductor branch has two branches, with a branch width W between 15 and 20 μm and a gap between the branches between 10 and 14 μm; or the semiconductor branch has one branch, with a branch width W between 30 and 40 μm.

[0142] In some embodiments, the shift register unit includes a seventh oxide thin film transistor M15, the source and drain of the seventh oxide thin film transistor M15 are connected to the pull-up node PU and the low-level reference voltage terminal LVGL of the shift register unit, respectively, and the gate is connected to the frame reset terminal TGOA_RST of the shift register unit.

[0143] The seventh oxide thin film transistor M15 is of one size. The seventh oxide thin film transistor M15 includes a source branch, a drain branch, and a semiconductor branch. The width W of the semiconductor branch is between 8 and 12 μm.

[0144] In some embodiments, the shift register unit includes an eighth oxide thin film transistor M2, the source and drain of the eighth oxide thin film transistor M2 are connected to the pull-up node PU and the low-level reference voltage terminal LVGL of the shift register unit, respectively, and the gate is connected to the first reset terminal RST_1 of the shift register unit.

[0145] The eighth oxide thin film transistor M2 is one in number. The eighth oxide thin film transistor M2 includes a source branch, a drain branch, and a semiconductor branch. The width W of the semiconductor branch is between 22 and 28 μm.

[0146] In some embodiments, the shift register unit includes a ninth oxide thin film transistor M13, the source and drain of the ninth oxide thin film transistor M13 are connected to the second output terminal OUT_2 and the low-level reference voltage terminal VGL of the shift register unit, respectively, and the gate is connected to the pull-down node PD.

[0147] The number of ninth oxide thin-film transistors M13 is one or two;

[0148] Each ninth oxide thin-film transistor M13 has one or two semiconductor branches, with one source branch and one drain branch each. 沟道总数 One or two;

[0149] The semiconductor branch has two branches, with a branch width W between 18 and 22 μm and a gap between the branches between 6 and 10 μm; or the semiconductor branch has one branch, with a branch width W between 36 and 44 μm.

[0150] Both the low-level reference voltage terminal VGL and the low-level reference voltage terminal LVGL are used to provide a low-level reference voltage. In practical applications, they have the same function and can be connected according to the actual situation. This disclosure is not intended to limit the two.

[0151] In some embodiments, the shift register unit includes a tenth oxide thin film transistor M11, the source and drain of the tenth oxide thin film transistor M11 are connected to the clock signal terminal CLK and the first output terminal of the shift register unit, respectively, and the gate is connected to the pull-up node PU.

[0152] The number of tenth oxide thin-film transistors M11 is one or two;

[0153] The tenth oxide thin-film transistor M11 contains six source branches and five drain branches, as well as two semiconductor branches, D 沟道总数 Ten or twenty;

[0154] The semiconductor branch has two branches, with a branch width W between 18 and 22 μm and a gap between the branches between 10 and 14 μm; or the semiconductor branch has one branch, with a branch width W between 36 and 44 μm.

[0155] In some embodiments, the shift register unit includes an eleventh oxide thin film transistor M3, the source and drain of the eleventh oxide thin film transistor M3 are connected to the clock signal terminal CLK and the second output terminal OUT_2 of the shift register unit, respectively, and the gate is connected to the pull-up node PU.

[0156] The eleventh oxide thin-film transistor M3 has one component. M3 contains seven source branches, seven drain branches, and sixteen semiconductor branches. 沟道总数 There are 120 semiconductor branches, with the width W of the semiconductor branches ranging from 3 to 6 μm and the gap between the semiconductor branches ranging from 6 to 10 μm.

[0157] Reference Figure 1 The length of the eight semiconductor branches in the eleventh oxide thin film transistor M3 that are far from the display area of ​​the display panel along the semiconductor branch extension direction is greater than the length of the eight semiconductor branches in the eleventh oxide thin film transistor M3 that are close to the display area of ​​the display panel along the semiconductor branch extension direction.

[0158] In the eleventh oxide thin film transistor M3, the number of channels in each of the eight semiconductor branches in the display area away from the display panel is 13, and the number of channels in each of the eight semiconductor branches in the display area close to the display panel is 12.

[0159] In some embodiments, the shift register unit includes a twelfth oxide thin film transistor M4, the source and drain of the twelfth oxide thin film transistor M3 are respectively connected to the second output terminal OUT_2 and the low-level reference voltage terminal VGL of the shift register unit, and the gate is connected to the second reset terminal RST_2 of the shift register unit.

[0160] The number of twelfth oxide thin film transistors M3 is one. The twelfth oxide thin film transistor M3 includes a source branch, a drain branch, and a semiconductor branch. The width W of the semiconductor branch is between 18 and 22 μm.

[0161] The following describes the positional relationships between the oxide thin-film transistors in the shift register unit.

[0162] Further optionally, in some embodiments, at least the first oxide thin-film transistor M5, the second oxide thin-film transistor M6, and the third oxide thin-film transistor M7 in the shift register unit are located in the frame region of the substrate of the display panel;

[0163] The source and drain branches of the first oxide thin film transistor M5, the second oxide thin film transistor M6 and the third oxide thin film transistor M7 extend along the direction perpendicular to the edge of the substrate.

[0164] The first oxide thin-film transistor M5 and the second oxide thin-film transistor M6 are arranged sequentially along the edge direction perpendicular to the substrate.

[0165] The first oxide thin-film transistor M5 and the third oxide thin-film transistor M7 are each one, both located on the same side of the second oxide thin-film transistor M6; or the first oxide thin-film transistor M5 and the third oxide thin-film transistor M7 are each two, with one pair of first oxide thin-film transistors M5A and third oxide thin-film transistors M7A located on one side of the second oxide thin-film transistor M6A, and another pair of first oxide thin-film transistors M5B and third oxide thin-film transistors M7B located on the other side of the second oxide thin-film transistor M6B.

[0166] A pair of first oxide thin film transistors M5A and third oxide thin film transistors M7A located on one side of the second oxide thin film transistor MA5 are arranged sequentially along the edge direction perpendicular to the substrate. Another pair of first oxide thin film transistors M5B and third oxide thin film transistors M7B located on the other side of the second oxide thin film transistor M5B are arranged sequentially along the edge direction of the substrate. Two pairs of first oxide thin film transistors M5 and third oxide thin film transistors M7 are arranged sequentially along the edge direction of the substrate.

[0167] Further optionally, in some embodiments, there are two of each of the first oxide thin-film transistor M5, the second oxide thin-film transistor M6, and the third oxide thin-film transistor M7;

[0168] A first oxide thin film transistor M6, the electrode terminal 60 of the shift register unit, another first oxide thin film transistor M6, and a third oxide thin film transistor M7 are arranged in a row along the edge direction of the substrate (i.e., the second direction D2).

[0169] Another third oxide thin film transistor M7, a second oxide thin film transistor M6, another second oxide thin film transistor M6, and the electrode terminals 60 of the shift register unit are arranged in a row along the edge direction of the substrate (i.e., the second direction D2).

[0170] Further optionally, in some embodiments, the sixth oxide thin-film transistor M1, the seventh oxide thin-film transistor M15, and the ninth oxide thin-film transistor M13 are arranged sequentially along the edge direction of the substrate (i.e., the second direction D2).

[0171] The sixth oxide thin-film transistor M1, the eighth oxide thin-film transistor M2, and the ninth oxide thin-film transistor M13 are arranged sequentially along the edge direction of the substrate (i.e., the second direction D2);

[0172] The seventh oxide thin-film transistor M15 and the eighth oxide thin-film transistor M2 are arranged sequentially along the edge direction perpendicular to the substrate (i.e., the first direction D1);

[0173] The fifth oxide thin-film transistor M12 and the sixth oxide thin-film transistor M1 are arranged sequentially along the edge direction perpendicular to the substrate. The fifth oxide thin-film transistor M12 and the seventh oxide thin-film transistor M15 are arranged sequentially along the edge direction perpendicular to the substrate (i.e., the first direction D1). The fifth oxide thin-film transistor M12 and the eighth oxide thin-film transistor M2 are arranged sequentially along the edge direction perpendicular to the substrate (i.e., the first direction D1). The fifth oxide thin-film transistor M12 and the ninth oxide thin-film transistor M13 are arranged sequentially along the edge direction perpendicular to the substrate (i.e., the first direction D1).

[0174] Further optionally, in some embodiments, there are two fifth oxide thin film transistors M12, with the electrode terminals 60 of the shift register unit, one fifth oxide thin film transistor M12, and the other fifth oxide thin film transistor M12 arranged in a row along the edge direction of the substrate.

[0175] Further optionally, in some embodiments, the tenth oxide thin film transistor M11 and the eleventh oxide thin film transistor M3 are arranged sequentially along the edge direction perpendicular to the substrate, and the tenth oxide thin film transistor M11 and the twelfth oxide thin film transistor M4 are arranged sequentially along the edge direction perpendicular to the substrate.

[0176] The eleventh oxide thin-film transistor M3 and the twelfth oxide thin-film transistor M4 are arranged sequentially along the edge of the substrate.

[0177] Further optionally, in some embodiments, the electrode terminals 60 of the shift register unit and the tenth oxide thin film transistor M11 are arranged in a row along the edge direction of the substrate.

[0178] In the above embodiments, the width of the gap j between two adjacent semiconductor branches can be greater than 6 μm.

[0179] When the gap j is less than or equal to 6 μm, the oxide thin film transistor will cause the Vth (threshold voltage) to drift faster due to heat generation. Therefore, a gap greater than 6 μm needs to be set between two adjacent semiconductor branches.

[0180] By setting oxide semiconductor layer patterns with different semiconductor branch widths under the same total channel width, oxide thin film transistors with different oxide semiconductor layer patterns were tested, and their stress (bias) characteristics were tested. The comparison results of Vth drift speed of different oxide thin film transistors are shown in Table 3 below. Wherein, W / L=1500 / 8.5=176.5.

[0181] It is understood that Table 3 only shows, by way of example, the test results of oxide thin-film transistors with some oxide semiconductor layer patterns.

[0182] Table 3

[0183]

[0184] The data in Table 3 show that when w is 5μm, 10μm, 20μm, and 50μm, Vth shows no significant acceleration in drift after 1 hour, 2 hours, 4 hours, and 8 hours, and Ion shows no significant acceleration in decrease after 8 hours. Therefore, for oxide thin-film transistors with W / L = 1500 / 8.5 = 176.5, where L is the channel length of the oxide thin-film transistor, there is no significant difference in stress characteristics between oxide thin-film transistors with different oxide semiconductor layer patterns. Since the higher the W, the more significant the heating phenomenon of the oxide thin-film transistor, it can be inferred that for oxide thin-film transistors with W / L ≤ 176.5, oxide semiconductor layer patterns with different semiconductor branch widths can be used according to the required total channel width.

[0185] Therefore, optionally, in some oxide thin-film transistors M, the total channel width W 总 The ratio of W / L to the channel length L can be less than or equal to 176.5. For oxide thin-film transistors with W / L ≤ 176.5, different oxide semiconductor layer patterns can be used without significantly affecting Vth and Ion, thus ensuring the stress characteristics of the oxide thin-film transistor.

[0186] However, for oxide thin-film transistors with W / L > 176.5, the oxide semiconductor layer pattern with w = 5 μm and a gap j = 7 μm between two adjacent semiconductor branches can currently only be determined experimentally, which has no significant effect on the Vth drift velocity.

[0187] Additionally, as mentioned earlier, W 总The higher the value, the more significant the heat generation phenomenon of oxide thin-film transistors. Therefore, optionally, W... 总 It can be less than or equal to 1500μm to avoid significant heat generation in oxide thin-film transistors, which could lead to failure.

[0188] In an alternative embodiment, the required total channel width W for each oxide thin-film transistor M in the circuit can be determined according to... 总 With the channel length L, the oxide semiconductor layer of each oxide thin film transistor M is set to one or more semiconductor branches with a width of 5μm, and a gap of 7μm can be set between two adjacent semiconductor branches.

[0189] In another alternative embodiment, such as Figure 1 As shown, both M5A and M5B include a semiconductor branch 301, and the width of the semiconductor branch 301 is W = 5 μm.

[0190] Both M7A and M7B include one semiconductor branch 301, and the semiconductor width w of the semiconductor branch 301 is 20 μm.

[0191] Both M6A and M6B include four semiconductor branches 301, with a gap j = 7 μm between two adjacent semiconductor branches 301 and a width W = 5 μm for each semiconductor branch 301.

[0192] Among them, W of M5 and M6 总 The ratio can be greater than 1:8. If M5 selects one semiconductor branch 301 with W = 5μm, each semiconductor branch 301 has one channel, that is, W of M5 总 =5μm, then according to the 1:8 ratio, the W of M6 总 =Requires to be 40μm.

[0193] If M6 selects two semiconductor branches 301 with W = 20μm, and the process variation deviation is 1μm, then W of M5... 总 The minimum is 4μm, and the W of M6 总 The minimum is (20-1)*2 = 38, the ratio M5 / 6 = 4 / 38 = 1:9.5, and the W of M5 总 The maximum is 6μm, and the W of M6 总 The maximum is (20+1)*2=42, and the ratio M5 / 6=6 / 42=1:7. The M5 / 6 ratio fluctuates within the range of 1:7 to 1:9.5, which poses a risk of abnormal PU retention rate. Therefore, M6 can be selected as four semiconductor branches 301 with W=5μm, each semiconductor branch 301 having two channels. In this way, regardless of process fluctuations, the M5 / 6 ratio will always remain at 1:8.

[0194] Both M8A and M8B include two semiconductor branches 301, each semiconductor branch 301 has 3 channels, the gap between two adjacent semiconductor branches 301 is j = 13 μm, and the width of each semiconductor branch 301 is W = 23.5 μm.

[0195] Both M12A and M12B include one semiconductor branch 301, each semiconductor branch 301 having one channel, and the width of the semiconductor branch 301 is W = 10 μm.

[0196] M1 includes two semiconductor branches 301, each semiconductor branch 301 has four channels, the gap between two adjacent semiconductor branches 301 is j = 13 μm, and the width of each semiconductor branch 301 is W = 18.75 μm.

[0197] M15 includes one semiconductor branch 301, each semiconductor branch 301 having one channel, and the width of the semiconductor branch 301 is W = 10 μm.

[0198] M2 includes one semiconductor branch 301, each semiconductor branch 301 having one channel, and the width of the semiconductor branch 301 is W = 25 μm.

[0199] Both M13A and M13B include two semiconductor branches 301, each semiconductor branch 301 having one channel, the gap between two adjacent semiconductor branches 301 being j = 7 μm, and the width of the semiconductor branch 301 being W = 20 μm.

[0200] M11 includes two semiconductor branches 301, each semiconductor branch 301 having 10 channels, the gap between two adjacent semiconductor branches 301 is j = 13 μm, and the width of the semiconductor branch 301 is W = 20 μm.

[0201] M3 includes 16 semiconductor branches 301. In the first 8 semiconductor branches 301, each semiconductor branch 301 includes 13 channels. In the last 8 semiconductor branches 301, each semiconductor branch 301 includes 12 channels. The gap between two adjacent semiconductor branches 301 is j = 7 μm, and the width of the semiconductor branch 301 is W = 5 μm.

[0202] Each M4 includes one semiconductor branch 301, and each semiconductor branch 301 includes one channel. The width of the semiconductor branch 301 is Ww = 20 μm.

[0203] exist Figure 1 In the optional embodiment shown, the total channel width W of each oxide thin-film transistor is... 总 The ratio to the channel length L can be found in Table 4 below.

[0204] Table 4

[0205]

[0206] After experimentation, the following method was adopted. Figure 1 The 18T1C shift register unit shown and the parameters mentioned above can reduce the bezel of the display device by 0.1mm (compared to the design where all oxide thin-film transistors in the 18T1C shift register unit are selected with W = 5μm multiples).

[0207] In yet another alternative embodiment, such as Figure 5 As shown, except for oxide thin-film transistor M6, the oxide semiconductor region layout of the other oxide thin-film transistors is the same as... Figure 1 The embodiments shown are the same.

[0208] Reference Figure 5 The total trench width W required for M6 总 =50μm, the oxide semiconductor layer of M6 can be composed of a semiconductor branch with W=25μm, which has two channels. The total channel width W required for oxide thin film transistor M5 is... 总 =5μm, the oxide semiconductor layer of M5 can be composed of a semiconductor branch with W = 5μm, which has a channel. M5 and M6 W 总 The designed ratio is 5:50 = 1:10. If the process fluctuation deviation is 1μm, the W of M5 总 The minimum is 4μm, and the W of M6 总 The minimum is (25-1)*2=48, then the W of M5 and M6 总 Ratio = 4 / 48 = 1:12. M5's W 总 The maximum is 6μm, and the W of M6 总 The maximum value is (25+1)*2=52, then the W of M5 and M6 总 The ratio is approximately 1:8.6, which is 6 / 52.

[0209] exist Figure 5 In the illustrated embodiment, W of M5 and M6 总 The ratio fluctuates within the range of 1:8.6 to 1:12, which can keep the voltage of the pull-up node PU normal.

[0210] In some optional embodiments, the width W of the semiconductor branch in the first direction D1 is greater than or equal to 5 μm and less than or equal to 50 μm. According to the relevant test results including Table 2, when 5 μm ≤ W ≤ 50 μm, different oxide semiconductor layer patterns can guarantee the stress characteristics of the oxide thin-film transistor. Therefore, in practical applications, the required total channel width W of the oxide thin-film transistor can be selected based on its specific dimensions. 总A suitable semiconductor branch width W is selected within the range of [5μm, 50μm] to fabricate the oxide semiconductor layer pattern.

[0211] Alternatively, the width W of each semiconductor branch belonging to an oxide thin-film transistor M can be the same in the first direction D1. That is, the semiconductor in the oxide thin-film transistor can be equally divided into semiconductor branches with an equal width W, thus simplifying the fabrication process of the semiconductor branches.

[0212] In addition, the following implementations may also exist for the gates of each oxide thin-film transistor in the shift register unit.

[0213] In some alternative embodiments, the gate of the oxide thin-film transistor extends along the extension direction of the corresponding semiconductor branch and overlaps with the semiconductor branch.

[0214] In some alternative embodiments, at least a portion of the gate of the oxide thin film transistor includes one or more gate branches, each gate branch being disposed corresponding to at least one semiconductor branch, a gate branch extending along the extension direction of a corresponding semiconductor branch and overlapping the semiconductor branch; the gate branches belonging to an oxide thin film transistor are electrically connected to each other.

[0215] In some alternative embodiments, the gate branches and semiconductor branches belonging to an oxide thin-film transistor have a sum of widths that is slightly greater than the sum of widths of the semiconductor branches.

[0216] In practical applications, refer to Figure 6 The partial cross-sectional view of the display device shown indicates that the pixel circuit 2000 can be disposed in the display area AA of the display panel, and the shift register unit 1000 can be disposed in the non-display area VA of the display panel. During encapsulation, an encapsulating adhesive layer 001 is applied to the frame area of ​​the non-display area VA. The encapsulating adhesive layer 001 needs to be cured by UV (ultraviolet) light, which needs to be incident from the side of the oxide semiconductor layer away from the gate to achieve curing. However, in some semiconductor solutions, such as those where the oxide semiconductor layer is an integral structure, and... Figure 5 The oxide semiconductor layer shown is a discrete semiconductor branch pattern, but each semiconductor branch has a width W = 5μm, and there is a 7μm gap between the semiconductor branches. During the UV curing process of the encapsulating adhesive layer 001, the gate size, composed of a single piece of metal, is too large, resulting in insufficient UV light transmittance. This leads to incomplete curing of the encapsulating adhesive layer 001, which can easily cause liquid crystal contamination around the display area and encapsulating adhesive layer detachment under high temperature, high pressure, and high humidity conditions. Furthermore, an excessively large gate width increases the overlap area between the gate metal and the source / drain metals, correspondingly increasing the parasitic capacitance of the thin-film transistor and leading to increased power consumption.

[0217] To ensure the UV light transmittance of the frame area meets curing requirements, the width of the gate needs to be controlled. The inventors, through experiments, determined that within a certain W... 总 In this case, using an oxide semiconductor layer pattern with W=5μm results in a gate width of 73μm, which cannot meet the UV light transmittance requirements. However, using an oxide semiconductor region pattern with W=10μm results in a gate width of only 50μm, which can meet the UV light transmittance requirements. Therefore, by customizing the oxide semiconductor layer pattern design, the needs for heat dissipation, reducing the bezel size, and curing the encapsulating adhesive in the frame area can be simultaneously met.

[0218] Additionally, optionally, in some embodiments, reference is made to Figure 7 Each oxide thin-film transistor in the shift register unit can include only one semiconductor branch. In a single semiconductor branch, the channels can be arranged in a column along the arrangement direction of the shift register units. In a multiplexed gate drive circuit architecture, one shift register unit can be used to drive at least two rows of pixel circuits. Therefore, in a multiplexed gate drive circuit architecture, fewer shift register units are required, and each shift register unit has more space to occupy in the arrangement direction of the cascaded shift register units. In this case, the channels of each semiconductor branch contained in each oxide thin-film transistor can be arranged in a column along the arrangement direction of the shift register units. This reduces the space occupied by the shift register units in the direction from the non-display area to the display area (i.e., the first direction D1), thereby further reducing the bezel size of the display device.

[0219] Alternatively, in some embodiments, reference is made to Figure 8 The shift register unit may also include one or more dummy electrodes 50;

[0220] The dummy electrode 50 is located between at least a portion of the adjacent source branch 101 and drain branch 102 of the oxide thin film transistor M. The dummy electrode 50 is formed using the same film pattern as the source branch 101 and drain branch 201. The dummy electrode 50 is not electrically connected to any conductive pattern.

[0221] The dummy electrode 50 is not charged, but it can provide better support for the oxide semiconductor layer and also increase the flatness of the non-display area of ​​the display panel.

[0222] It should be noted that, Figure 1 , Figure 5 and Figure 7The figures only exemplarily illustrate some shift register units and the arrangement of some oxide semiconductor layers of the shift register units. This disclosure is not intended to limit the specific shift register units and the arrangement of oxide semiconductor layers. Furthermore, the figures in this disclosure only exemplarily illustrate some film layers and some connections between film layers, and do not constitute a limitation on this disclosure.

[0223] Of course, in practical applications, the shift register unit provided in this disclosure embodiment can also be used for... Figure 1 The 22T1C architecture is based on the 18T1C architecture with the addition of four oxide thin-film transistors M. The four added oxide thin-film transistors M can all be used to increase the voltage of the pull-up node PU. In this 22T1C architecture, the W of M5 and M6... 总 The ratio has little impact on the pull-up node PU retention rate. Therefore, in this 22T1C architecture, the W ratio of M5 and M6... 总 The ratio need not be limited to 1:8 or higher, and the embodiments of the present invention do not impose specific limitations on this.

[0224] The 18T1C architecture described above is merely an example illustrating a W-type architecture affected by M5 and M6. 总 The shift register cell architecture affected by the ratio, as illustrated above with the 22T1C architecture, is merely an example of a W shift register cell architecture unaffected by M5 and M6. 总 The shift register cell architecture affected by the ratio is understood to be applicable not only to the aforementioned 18T1C and 22T1C shift register cells, but also to the W... 总 The ratios affecting the shift register cells of oxide thin-film transistors are not limited to M5 and M6 as described above, and this disclosure is not intended to limit them.

[0225] It is understandable that for W, which is not affected by any two or more oxide thin-film transistors 总 For shift register cells affected by ratios, there is no need to consider the W values ​​of these oxide thin-film transistors. 总 The ratio is specially designed, and for W which will be affected by two or more oxide thin-film transistors 总 The shift register cells affected by the ratio require W values ​​from these oxide thin-film transistors. 总 A special formulation design is employed. The specific formulation can be verified through experiments, guided by the various embodiments of this disclosure.

[0226] In the embodiments of this disclosure, based on the gate size required to meet the curing requirements of the encapsulation adhesive layer and the requirement for bezel reduction, different width semiconductor branch patterns can be used for oxide thin film transistors with different total channel width requirements in the shift register unit. This not only compresses the bezel and reduces the parasitic capacitance of the oxide thin film transistor, saving power consumption, but also solves the problem of insufficient curing of the encapsulation adhesive layer caused by a large gate metal width.

[0227] It should also be noted that in this disclosure, the source and drain are only relative terms. In the specific implementation of this disclosure, the source and drain can be interchanged depending on the specific thin-film transistor.

[0228] This disclosure also discloses a gate driving circuit, including multiple cascaded shift register units, wherein the shift register units are those described above.

[0229] This disclosure also discloses a display device including the above-described gate driving circuit.

[0230] In some embodiments, the display device can be a dual-side gate driving architecture, that is, in the display device, gate driving circuits can be provided on both sides of the display area, wherein the gate driving circuit on one side can be used to drive a portion of the pixel circuits (e.g., the pixel circuits in odd-numbered rows), and the gate driving circuit on the other side can be used to drive the remaining pixel circuits (e.g., the pixel circuits in even-numbered rows). This disclosure does not specifically limit this aspect.

[0231] In this embodiment, the oxide semiconductor layer of the oxide thin-film transistor (OTFT) can be partitioned according to the required total channel width and channel length of the OTFT in the shift register unit. The sum of the widths of each independent semiconductor branch equals the required total channel width. Thus, an OTFT can achieve the required total channel width through one or more semiconductor branches, ensuring normal operation. This allows for the reduction of display device bezels by designing different oxide semiconductor layers for different OTFTs. Simultaneously, the smaller semiconductor branches and the gaps between them can be used for heat dissipation, preventing OTFT failure due to heat accumulation in the oxide semiconductor.

[0232] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0233] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0234] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0235] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A shift register unit located on a substrate of a display panel, in a non-display area, comprising a plurality of oxide thin-film transistors, each oxide thin-film transistor comprising an oxide semiconductor layer and source and drain electrodes connected to and spaced apart from the oxide semiconductor layer, characterized in that... At least a portion of the oxide thin-film transistors have multiple branches at their source and drain; wherein the source includes multiple source branches extending along a first direction, and the drain includes multiple drain branches extending along the first direction; the source branches and drain branches are arranged facing each other and are sequentially intersected in a second direction; The oxide semiconductor layer has at least one or more spaced and parallel semiconductor branches, each semiconductor branch extending in a second direction perpendicular to the drain extension direction and overlapping and electrically connected with the source and drain branches, and the width of the semiconductor branch overlapping with any adjacent source and drain branches is the distance W from one end of the semiconductor branch to the other end in the first direction. In this embodiment, at least some of the oxide thin-film transistors are multiple oxide thin-film transistors, and the widths of the semiconductor branches belonging to different oxide thin-film transistors are not exactly the same; The width W of the semiconductor branch in the at least partially oxide thin-film transistor is not less than 3 μm and not more than 60 μm. The shift register unit includes a pull-down control circuit, which includes a first oxide thin-film transistor located between the pull-down node and the high-level reference voltage terminal, and a second oxide thin-film transistor located between the pull-down node and the low-level reference voltage terminal. Each oxide thin-film transistor satisfies the following formula: W 总 =D 沟道总数 *W; W is the width of a semiconductor branch, D 沟道总数 W is the sum of the number of channels in an oxide thin-film transistor, representing the semiconductor branches between each source branch and the adjacent drain branch. 总 This is the total width of the channel; W of the first oxide thin film transistor 总 and W with the second oxide thin film transistor 总 The ratio is between 0.05 and 0.

17.

2. The shift register unit according to claim 1, characterized in that, W of the first oxide thin film transistor 总 The W of the second oxide thin-film transistor is not less than 3μm. 总 No larger than 60μm.

3. The shift register unit according to claim 1, characterized in that, The pull-down control circuit has one or two pull-down nodes, the number of the first oxide thin film transistors is one or two oxide thin film transistors connected to the pull-down nodes one by one, and the number of the second oxide thin film transistors is one or two oxide thin film transistors connected to the pull-down nodes one by one. The two first oxide thin film transistors have the same channel length, the same width of semiconductor branches, the same number of semiconductor branches, and the same spacing between adjacent semiconductor branches; The two second oxide thin-film transistors have the same channel length, the same width of semiconductor branches, the same number of semiconductor branches, and the same spacing between adjacent semiconductor branches.

4. The shift register unit according to claim 2, characterized in that, Each of the first oxide thin-film transistors has one semiconductor branch, one source branch and one drain branch, and the width of the semiconductor branch is 3-6 μm, and the width of the semiconductor branch is the total width of the channel of the first oxide thin-film transistor.

5. The shift register unit according to claim 2, characterized in that, The W of the second oxide thin film transistor 总 The thickness is between 37 and 43 μm; the second oxide thin-film transistor has four semiconductor branches, two source branches, and one drain branch. 沟道总数 There are eight, and the width of one semiconductor branch is (1 / 8) * W. 总 The gap between semiconductor branches is between 6 and 10 μm; The semiconductor branch extends from one source branch through the drain branch to another source branch, and contacts the source branch and the drain branch respectively; or The W of the second oxide thin film transistor 总 The thickness is between 48 and 52 μm; the second oxide thin-film transistor has one semiconductor branch, two source branches, and one drain branch. Each semiconductor branch extends from one source branch through the drain branch to another source branch, contacting both the source and drain branches. The width of each semiconductor branch is W of the second oxide thin-film transistor. 总 One-half of D 沟道总数 There are two semiconductor branches, and the width of the branches is between 24 and 26 μm.

6. The shift register unit according to claim 1 or 5, characterized in that, The shift register unit includes a third oxide thin-film transistor located between a pull-down node and a low-level reference voltage terminal. The gate of the third oxide thin-film transistor is connected to the input terminal of the shift register unit, and the source and drain of the third oxide thin-film transistor are connected to the pull-down node and the low-level reference voltage terminal, respectively. The number of the third oxide thin-film transistors is one or two; Each of the third oxide thin-film transistors includes a source branch, a drain branch, and a semiconductor branch, wherein the width W of the semiconductor branch is between 18 and 22 μm.

7. The shift register unit according to claim 1 or 5, characterized in that, The shift register unit includes a fourth oxide thin-film transistor, the source and drain of which are connected to a pull-up node and a low-level reference voltage terminal, respectively, and the gate is connected to a pull-down node. The number of the fourth oxide thin-film transistor is one or two; The fourth oxide thin-film transistor has one to two semiconductor branches, with two source branches and two drain branches each. 沟道总数 Three or six; The semiconductor branch has two branches, with a branch width of 20-25 μm and a gap between the branches of 10-14 μm; or it has one branch, with a branch width of 40-50 μm.

8. The shift register unit according to claim 1 or 5, characterized in that, The shift register unit includes a fifth oxide thin-film transistor, the source and drain of which are connected to the first output terminal and the low-level reference voltage terminal of the shift register unit, respectively, and the gate is connected to a pull-down node. The number of the fifth oxide thin-film transistor is one or two; Each of the fifth oxide thin-film transistors includes a source branch, a drain branch, and a semiconductor branch, wherein the width W of the semiconductor branch is between 8 and 12 μm.

9. The shift register unit according to claim 8, characterized in that, The shift register unit includes a sixth oxide thin-film transistor, the source and gate of which are connected to the input terminal of the shift register unit, and the drain is connected to a pull-up node. The sixth oxide thin-film transistor is one in number, and it includes three source branches and two drain branches. 沟道总数 Four or eight; The semiconductor branch has two branches, with a branch width W between 15 and 20 μm and a gap between the branches between 10 and 14 μm; or the semiconductor branch has one branch, with a branch width W between 30 and 40 μm.

10. The shift register unit according to claim 9, characterized in that, The shift register unit includes a seventh oxide thin-film transistor, the source and drain of which are connected to the pull-up node and low-level reference voltage terminal of the shift register unit, respectively, and the gate is connected to the frame reset terminal of the shift register unit. The seventh oxide thin-film transistor is one in number, and the seventh oxide thin-film transistor includes a source branch, a drain branch, and a semiconductor branch, the width W of which is between 8 and 12 μm.

11. The shift register unit according to claim 10, characterized in that, The shift register unit includes an eighth oxide thin-film transistor, the source and drain of which are connected to the pull-up node and low-level reference voltage terminal of the shift register unit, respectively, and the gate is connected to the first reset terminal of the shift register unit. The number of the eighth oxide thin film transistors is one, and the eighth oxide thin film transistor includes a source branch, a drain branch and a semiconductor branch, the width W of the semiconductor branch being between 22 and 28 μm.

12. The shift register unit according to claim 11, characterized in that, The shift register unit includes a ninth oxide thin-film transistor, the source and drain of which are connected to the second output terminal and the low-level reference voltage terminal of the shift register unit, respectively, and the gate is connected to a pull-down node. The number of the ninth oxide thin-film transistor is one or two; Each of the ninth oxide thin-film transistors has one or two semiconductor branches, with one source branch and one drain branch each. 沟道总数 One or two; The semiconductor branch has two branches, with a branch width W between 18 and 22 μm and a gap between the branches between 6 and 10 μm; or the semiconductor branch has one branch, with a branch width W between 36 and 44 μm.

13. The shift register unit according to claim 1, characterized in that, The shift register unit includes a tenth oxide thin-film transistor, the source and drain of which are connected to the clock signal terminal and the first output terminal of the shift register unit, respectively, and the gate is connected to a pull-up node. The number of the tenth oxide thin-film transistor is one or two; The tenth oxide thin-film transistor includes six source branches and five drain branches, as well as two semiconductor branches, D 沟道总数 Ten or twenty; The number of semiconductor branches is two, the width W of the semiconductor branches is between 18 and 22 μm, and the gap between the semiconductor branches is between 10 and 14 μm; or the number of semiconductor branches is one, and the width W of the semiconductor branch is between 36 and 44 μm.

14. The shift register unit according to claim 13, characterized in that, The shift register unit includes an eleventh oxide thin-film transistor, the source and drain of which are connected to the clock signal terminal and the second output terminal of the shift register unit, respectively, and the gate is connected to a pull-up node. The number of the eleventh oxide thin-film transistor is one, and the eleventh oxide thin-film transistor includes seven source branches, seven drain branches, and sixteen semiconductor branches, D 沟道总数 There are 120 semiconductor branches, with the width W of the semiconductor branches being between 3 and 6 μm and the gap between the semiconductor branches being between 6 and 10 μm. The length of the eight semiconductor branches in the eleventh oxide thin film transistor that are far from the display area of ​​the display panel along the extension direction of the semiconductor branches is greater than the length of the eight semiconductor branches in the eleventh oxide thin film transistor that are close to the display area of ​​the display panel along the extension direction of the semiconductor branches. In the eleventh oxide thin-film transistor, among the eight semiconductor branches away from the display area of ​​the display panel, each semiconductor branch has 13 channels, and in the eight semiconductor branches close to the display area of ​​the display panel, each semiconductor branch has 12 channels.

15. The shift register unit according to claim 14, characterized in that, The shift register unit includes a twelfth oxide thin-film transistor, the source and drain of which are connected to the second output terminal and the low-level reference voltage terminal of the shift register unit, respectively, and the gate is connected to the second reset terminal of the shift register unit. The number of the twelfth oxide thin film transistors is one, and the twelfth oxide thin film transistor includes a source branch, a drain branch, and a semiconductor branch, the width W of which is between 18 and 22 μm.

16. The shift register unit according to claim 1, characterized in that, The gate of the oxide thin-film transistor extends along the extension direction of the corresponding semiconductor branch and overlaps with the semiconductor branch.

17. The shift register unit according to claim 16, characterized in that, At least a portion of the oxide thin-film transistors have gates comprising one or more gate branches, each gate branch corresponding to at least one semiconductor branch, and one gate branch extending along the extension direction of a corresponding semiconductor branch and overlapping the semiconductor branch; the gate branches belonging to one oxide thin-film transistor are electrically connected to each other.

18. The shift register unit according to claim 17, characterized in that, The gate branches and semiconductor branches belonging to one of the oxide thin-film transistors have a sum of widths of the gate branches that is slightly greater than the sum of widths of the semiconductor branches.

19. The shift register unit according to claim 1, characterized in that, It also includes one or more dummy electrodes; The dummy electrode is located between at least some adjacent source and drain branches of at least a portion of the oxide thin-film transistor. The dummy electrode is formed using the same film pattern as the source and drain branches. The dummy electrode is not electrically connected to any conductive pattern.

20. The shift register unit according to claim 6, characterized in that, At least the first oxide thin-film transistor, the second oxide thin-film transistor, and the third oxide thin-film transistor in the shift register unit are located in the frame region of the substrate of the display panel; The source and drain branches of the first oxide thin film transistor, the second oxide thin film transistor, and the third oxide thin film transistor extend along the edge direction perpendicular to the substrate; The first oxide thin-film transistor and the second oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate; The first oxide thin-film transistor and the third oxide thin-film transistor are each one, and are both located on the same side of the second oxide thin-film transistor; or the first oxide thin-film transistor and the third oxide thin-film transistor are each two, one pair of the first oxide thin-film transistors and the third oxide thin-film transistors are located on one side of the second oxide thin-film transistor, and the other pair of the first oxide thin-film transistors and the third oxide thin-film transistors are located on the other side of the second oxide thin-film transistor; The pair of first oxide thin-film transistors and the third oxide thin-film transistor located on one side of the second oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate, and the other pair of first oxide thin-film transistors and the third oxide thin-film transistor located on the other side of the second oxide thin-film transistor are arranged sequentially along the edge direction of the substrate; the two pairs of first oxide thin-film transistors and the third oxide thin-film transistors are arranged sequentially along the edge direction of the substrate.

21. The shift register unit according to claim 20, characterized in that, There are two of each of the first oxide thin-film transistor, the second oxide thin-film transistor, and the third oxide thin-film transistor; One of the first oxide thin-film transistors, the electrode terminals of the shift register unit, another of the first oxide thin-film transistors, and one of the third oxide thin-film transistors are arranged in a row along the edge of the substrate. Another third oxide thin-film transistor, one second oxide thin-film transistor, another second oxide thin-film transistor, and the electrode terminals of the shift register unit are arranged in a row along the edge direction of the substrate.

22. The shift register unit according to claim 12, characterized in that, The sixth oxide thin-film transistor, the seventh oxide thin-film transistor, and the ninth oxide thin-film transistor are arranged sequentially along the edge direction of the substrate; The sixth oxide thin-film transistor, the eighth oxide thin-film transistor, and the ninth oxide thin-film transistor are arranged sequentially along the edge direction of the substrate; The seventh oxide thin-film transistor and the eighth oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate; The fifth oxide thin-film transistor and the sixth oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate. The fifth oxide thin-film transistor and the seventh oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate. The fifth oxide thin-film transistor and the eighth oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate. The fifth oxide thin-film transistor and the ninth oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate.

23. The shift register unit according to claim 22, characterized in that, There are two fifth oxide thin-film transistors. The electrode terminals of the shift register unit, one fifth oxide thin-film transistor, and the other fifth oxide thin-film transistor are arranged in a row along the edge direction of the substrate.

24. The shift register unit according to claim 15, characterized in that, The tenth oxide thin-film transistor and the eleventh oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate, and the tenth oxide thin-film transistor and the twelfth oxide thin-film transistor are arranged sequentially along the edge direction perpendicular to the substrate. The eleventh oxide thin-film transistor and the twelfth oxide thin-film transistor are arranged sequentially along the edge direction of the substrate.

25. The shift register unit according to claim 24, characterized in that, The electrode terminals of the shift register unit and the tenth oxide thin-film transistor are arranged in a row along the edge direction of the substrate.

26. A gate driving circuit, characterized in that, It includes multiple cascaded shift register units, wherein the shift register unit is the shift register unit as described in any one of claims 1-25.

27. A display device, characterized in that, It includes pixel circuitry and the gate drive circuitry as described in claim 26.

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