Gate driving circuit and display device including the same

Abstract

A gate driving circuit capable of being stably driven by improving output characteristics of a last output buffer unit and a display device including the same are disclosed. The gate driving circuit includes a plurality of stages connected in cascade, an Nth (N is a natural number) stage including a node controller configured to control voltages of a first node and a second node according to a set signal and a reset signal, and a plurality of scan pulse output units configured to receive a plurality of scan clocks and output each of the scan clocks as a scan pulse according to the voltages of the first node and the second node, wherein a last scan pulse output unit of the plurality of scan pulse output units further outputs a corresponding scan clock as a scan pulse according to a first node voltage of an (N+1)th stage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2021-0191874, filed on December 29, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a gate driving circuit that uses a shift register to shift a gate signal, and a display device including the gate driving circuit. Background Technology

[0004] In the information society, numerous technologies have been developed in the field of display devices for displaying visual information as images or videos. The driving circuitry of a display device includes data driving circuitry for providing data signals to data lines, gate driving circuitry for sequentially providing gate signals (or scan signals) to gate lines (or scan lines), and so on. The gate driving circuitry can be directly formed on the display area of ​​the same substrate along with the circuit elements of the pixel array included in the screen.

[0005] The circuit elements of the pixel array are included in the pixel circuitry formed in each pixel, which is defined by a matrix of data lines and gate lines of the pixel array. Each circuit element of the pixel array and gate drive circuitry includes multiple transistors. Hereinafter, the gate drive circuitry formed directly on the display area of ​​the display panel, together with the circuit elements of the pixel array, will be referred to as the "GIP circuitry".

[0006] Most display devices use a progressive scan method to write data to pixels. In this method, pixel data of the input image is sequentially written to all rows of the pixel array during the vertical active period of a frame cycle. For example, pixel data is written to the pixels of the first row simultaneously, then to the pixels of the second row simultaneously, and so on, until the pixels of the third row are written to the pixels of the third row simultaneously. In this way, pixel data is sequentially written to the pixels of all rows of the display panel. To implement this progressive scan method, the GIP circuitry uses a shift register to shift the output signal and sequentially provides the gate signal to the gate lines. Here, the output signal can be interpreted as either a gate signal or a scan signal.

[0007] The shift register includes multiple slave-connected stages, and each stage has an output buffer that generates a gate signal and provides the generated gate signal to a gate line.

[0008] In recent years, since the gate drive circuit (GIP circuit) is formed directly in the display area of ​​the display panel along with the circuit elements of the pixel array, there is a requirement to minimize the configuration of the GIP circuit.

[0009] Accordingly, a shift register for outputting a plurality of gate signals in a stage has been developed. That is, a stage has a plurality of output buffers each for generating one gate signal, called "NSDC".

[0010] As described above, since the stage includes a plurality of output buffers, there is a problem in that the voltage of the set node decreases at the time of output of the gate signal (scan signal) of the last output buffer among the plurality of output buffers, and thus the fall time (TF) of the gate signal (scan signal) of the last output buffer increases. SUMMARY

[0011] Accordingly, the present application is directed to a gate driving circuit and a display device using the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0012] An object of the present application is to provide a gate driving circuit capable of being stably driven by improving the output characteristics of a last output buffer unit and a display device including the same.

[0013] Additional advantages, objects, and features of the application will be set forth in part in the description which follows and will become apparent to those having ordinary skill in the art upon examination of the following or can be learned from practice of the application. The objects and other advantages of the application can be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0014] To achieve these objects and other advantages and in accordance with the purpose of the present application, as embodied and broadly described herein, a gate driving circuit includes a plurality of stages connected in cascade, wherein: an Nth (n is a natural number) stage includes: a node controller configured to control voltages of a first node and a second node according to a set signal and a reset signal; and a plurality of scan pulse output units configured to receive a plurality of scan clocks and output each of the scan clocks as a scan pulse according to the voltages of the first node and the second node, and a last scan pulse output unit among the plurality of scan pulse output units is further configured to output a corresponding scan clock as a scan pulse according to a first node voltage of an (N+1)th stage.

[0015] The Nth stage can further include a carry signal output unit configured to output a carry clock as a carry pulse signal according to the voltages of the first node and the second node.

[0016] The last scan pulse output unit can include a first pull-up transistor turned on or off according to a voltage of the first node to output a corresponding scan clock to the output terminal, a second pull-up transistor turned on or off according to a voltage of the first node of the (N+1)th stage to output a corresponding scan clock to the output terminal, and a pull-down transistor turned on or off according to a voltage of the second node to output a low voltage power to the output terminal.

[0017] The last scan pulse output unit can further include a capacitor connected between a gate electrode of the first pull-up transistor and the output terminal to bootstrap the first node.

[0018] In another aspect of the present application, a display apparatus includes a display panel including data lines, gate lines, and sub-pixels, a data driving circuit configured to provide a data signal of an input image to the data lines, and a gate driving circuit configured to provide a gate signal to the gate lines, wherein the gate driving circuit includes a plurality of slave-connected stages, an Nth stage includes a node controller configured to control voltages of a first node and a second node according to a set signal and a reset signal, and a plurality of scan pulse output units configured to receive a plurality of scan clocks and output each of the scan clocks as a scan pulse according to the voltages of the first node and the second node, and a last scan pulse output unit of the plurality of scan pulse output units further outputs a corresponding scan clock as a scan pulse according to a voltage of a first node of an (N+1)th stage.

[0019] It is to be understood that both the foregoing general description and the following detailed description of the present application are exemplary and explanatory and are intended to provide further explanation of the application as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:

[0021] Figure 1 is a configuration diagram of a display apparatus according to an embodiment of the present application;

[0022] Figure 2 is a principle configuration diagram of a shift register of the gate driving circuit 120;

[0023] Figure 3 is a detailed circuit diagram of an Nth stage according to a comparative example of the present application;

[0024] Figure 4 is an input / output waveform diagram of a gate driving circuit according to a comparative example of the present application;

[0025] Figure 5 is a specific circuit diagram of the Nth and (N+l)th stages according to an embodiment of the present application;

[0026] Figure 6 is an input / output waveform diagram of a gate driving circuit according to an embodiment of the present application; and

[0027] Figure 7 is a graph comparing the scan pulse output of the fourth scan pulse output unit 16 according to the comparative example and the embodiment of the present application. DETAILED DESCRIPTION

[0028] Advantages and features of the present application and methods of achieving the advantages and features will become apparent from the embodiments described below in detail in conjunction with the accompanying drawings. However, the present application is not limited to the embodiments disclosed below and can be implemented in various different forms, and these embodiments make the present application complete and are provided only to give those of ordinary skill in the art to which the present application pertains a full disclosure. Furthermore, the present application is limited only by the scope of the claims.

[0029] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present application are exemplary, and thus the present application is not limited to the illustrated elements. The same reference numbers denote the same elements throughout the specification. Also, in describing the present application, when it is determined that a detailed description of the related known technology can unnecessarily obscure the subject matter of the present application, such a detailed description will be omitted.

[0030] When "provided with", "including", "having", "comprising", etc. are used in the present specification, other parts can also exist unless "only" is used. When an element is expressed in a singular form, the element can be interpreted as a plural number unless explicitly stated otherwise.

[0031] In explaining an element, even if there is no separate explicit description, it will be interpreted to include an error range.

[0032] In describing a positional relationship, for example, when "upper", "above", "lower", "adjacent", etc. are used to describe the positional relationship between two parts, one or more other parts can be located between the two parts unless "immediately" or "directly" is used.

[0033] Although "first", "second", etc. can be used to distinguish elements, the functions or structures of the elements are not limited by the serial number or the name of the element in front of the element. Since the claims are described based on the essential elements, the serial number in front of the name of the element in the claims can not match the serial number in front of the name of the element in the embodiments.

[0034] The following embodiments can be partially or wholly combined with each other or combined, and various types of interlocking and driving are technically possible. Each embodiment can be implemented independently of each other or together in association with each other.

[0035] In the present application, the GIP circuit of the gate drive circuit and the pixel circuit each include a plurality of transistors, respectively. The transistors can be implemented as thin film transistors (TFTs) of a metal-oxide-semiconductor FET (MOSFET) structure, and can be oxide TFTs including oxide semiconductors or low-temperature polysilicon (LTPS) TFTs including LTPS. The oxide TFTs can be implemented as n-type TFTs (NMOS), and the LTPS TFTs can be implemented as p-type TFTs (PMOS). In each of the GIP circuit of the gate drive circuit and the pixel circuit, n-type TFTs (NMOS) and p-type TFTs (PMOS) can be formed.

[0036] A MOSFET is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a transistor with carriers. In a MOSFET, carriers start to flow out from the source. The drain is an electrode through which carriers exit the MOSFET. In a MOSFET, carriers flow from the source to the drain. In the case of an n-type TFT (NMOS), since the carriers are electrons, the source voltage is lower than the drain voltage, and thus the electrons can flow from the source to the drain. In an n-type TFT (NMOS), current flows in the direction from the drain to the source. In the case of a p-type TFT (PMOS), since the carriers are holes, the source voltage is higher than the drain voltage, and thus the holes can flow from the source to the drain. In a p-type TFT (PMOS), since the holes flow from the source to the drain, current flows from the source to the drain. Note that the source and the drain of a TFT are not fixed. For example, the source and the drain can change depending on the applied voltage. Therefore, the present application is not limited by the source and the drain of a TFT. In the following description, the source and the drain of a TFT will be referred to as a first electrode and a second electrode, respectively.

[0037] A gate signal output from the GIP circuit of the gate drive circuit swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is a voltage set to be higher than the threshold voltage of a TFT, and the gate-off voltage is a voltage set to be lower than the threshold voltage of a TFT. A TFT turns on in response to the gate-on voltage, and turns off in response to the gate-off voltage.

[0038] Hereinafter, various embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following embodiments, an electroluminescent display will be mainly described with respect to an organic light emitting diode display including an organic light emitting material. It should be noted that the technical concept of the present specification is not limited to the organic light emitting diode display. For example, the present application is applicable to a gate driving circuit of a digital flat panel display requiring a gate driving circuit, such as a liquid crystal display (LCD) or a quantum dot display (QD), without significant changes.

[0039] Figure 1 is a block diagram illustrating a display apparatus according to an embodiment of the present application.

[0040] The display apparatus according to the embodiment of the present specification includes a display panel 100 and a display panel driving circuit.

[0041] The display panel 100 includes an active area AA that displays data of an input image. The active area AA is a screen that displays video data of an input image. The pixel array of the active area AA includes a plurality of data lines DL, a plurality of gate lines GL crossing the data lines DL, and pixels arranged in a matrix. In addition to the matrix, the pixels can be arranged in various forms, such as a form in which pixels emitting the same color are shared, a stripe form, and a diamond form.

[0042] Each pixel can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each pixel can further include a white sub-pixel. Each sub-pixel 101 includes a pixel circuit. In the case of an electroluminescent display, the pixel circuit includes a light emitting element, a plurality of TFTs, and a capacitor. The pixel circuit is connected to the data line DL and the gate line GL. In the case of an electroluminescent display, the pixel circuit further includes a storage capacitor. Figure 1 In FIG. 1, "D1 to D3" indicated in the circle are data lines, and "Gn-2 to Gn" indicated in the circle are gate lines.

[0043] A touch sensor can be provided on the display panel 100. A separate touch sensor can be used to sense a touch input, or a touch input can be sensed through a pixel. The touch sensor can be provided on the screen of the display panel as an on-cell or an out-cell touch sensor, or can be implemented as an in-cell touch sensor embedded in the pixel array.

[0044] A driving circuit for driving the display panel 100 includes a data driving circuit 110 and a gate driving circuit 120. The display panel driving circuit writes data of an input image to the pixels of the display panel 100 under the control of a timing controller (TCON) 130.

[0045] The data driver circuit 110 converts the digital data V-DATA, which is the pixel data of the input image received from the timing controller 130 in each frame, into a gamma-compensated voltage and outputs a data signal. The data driver circuit 110 provides the voltage of the data signal (hereinafter referred to as the "data voltage") to the data line DL. The data driver circuit 110 uses a digital-to-analog converter (hereinafter referred to as the "DAC") that converts the digital data VDATA into a gamma-compensated voltage to output the data voltage.

[0046] Gate driving circuit 120 may be formed in the border area BZ on the display panel 100 where no image is displayed. Under the control of timing controller 130, gate driving circuit 120 outputs a gate signal through gate line GL to select pixels charged with data voltage. Gate driving circuit 120 uses one or more shift registers to output and shift the gate signal. During the vertical activation period, gate driving circuit 120 shifts the gate signal provided to the gate line to a predetermined specific gate line in a specific shift timing sequence, and then temporarily holds the voltage of the specific gate line in response to a line control signal. Subsequently, gate driving circuit 120 provides a gate signal (scan pulse signal) to the specific gate line, and then shifts the gate signals (scan pulse signals) provided to the remaining gate lines in a specific shift timing sequence. Therefore, during the vertical activation period, the first gate signal and the second gate signal are applied only to the specific gate line, with a predetermined hold time interspersed, and one gate signal is applied to each of the other gate lines.

[0047] The timing controller 130 receives pixel data of the input image and timing signals synchronized with the pixel data from the host system. The pixel data of the input image received by the timing controller 130 is digital data. The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. Since the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted.

[0048] The host system can be a television (TV), set-top box, navigation system, personal computer (PC), home theater, mobile device, and wearable device. In mobile devices and wearable devices, the data driver unit 110, timing controller 130, level shifter 140, etc., can be integrated into a single driver IC.

[0049] The timing controller 130 can control the operating timing of the data drive circuit 110 and the gate drive circuit 120 by multiplying the input frame frequency by i to obtain a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the Phase Alternating Line (PAL) scheme.

[0050] The timing controller 130 can lower the driving frequency of the data driving circuit 110 and the gate driving circuit 120 in the low-speed driving mode. For example, the timing controller 130 can lower the driving frequency of the display panel driving circuit to a level of 1 Hz, thereby writing data to the pixels once per second. The frequency of the low-speed driving mode is not limited to 1 Hz. Thus, the pixels of the display panel 100 can maintain the data voltage with which the pixels were previously charged for most of the time in the low-speed driving mode, without being charged with new data voltage.

[0051] The timing controller 130 generates a data timing control signal DDC for controlling the operation timing of the data driving circuit 110 and a gate timing control signal GDC for controlling the operation timing of the gate driving circuit 120, based on a timing signal received from the host system.

[0052] The level shifter 140 converts a high-level voltage of the gate timing control signal GDC output from the timing controller 130 into a gate-on voltage, converts a low-level voltage of the gate timing control signal GDC into a gate-off voltage, and supplies the voltages to the gate driving circuit 120. In the case of an n-channel TFT (NMOS), the gate-on voltage can be a gate high voltage VGH, and the gate-off voltage can be a gate low voltage VGL. In the case of a p-channel TFT (PMOS), the gate-on voltage can be a gate low voltage VGL, and the gate-off voltage can be a gate high voltage VGH. Hereinafter, a high potential power voltage Vdd can be explained as the gate-on voltage. A low potential power voltage Vss can be set to a voltage lower than the high potential power voltage Vdd. The low potential power voltage Vss can be explained as the gate-off voltage.

[0053] The gate timing control signal GDC includes a gate start pulse VST, a line selection pulse LSP, a carry clock signal CRCLK, a scan clock signal SCCLK, etc. In each frame period, the start pulse VST is generated once at the beginning of the frame period and is input to the gate driving circuit 120.

[0054] The start pulse VST controls the start timing of the gate driving circuit 120 in each frame period. The carry clock signal CRCLK and the scan clock signal SCCLK control the shift timing of carry pulses and scan pulses output from the gate driving circuit 120.

[0055] Figure 2 FIG. 2 is a diagram schematically showing a shift register of the gate driving circuit 120.

[0056] First, the gate driving circuit 120 can be driven by three carry clocks and 12 scan clocks.

[0057] Each carry clock and each scan clock is kept high for two horizontal cycles (2H).

[0058] In addition, the 12 scan clocks are shifted by one horizontal cycle by the high level of the scan clock that overlaps with the adjacent scan clock.

[0059] like Figure 2 As shown, the shift register of the gate drive circuit 120 includes stages SR(N-2) to SR(N+2) connected by wires. The shift register receives a start pulse VST, or a carry pulse CP from the previous stage and a carry pulse CP from the next stage, and outputs a carry pulse CP and i scan pulses SP according to the input clock timing CLK. Here, N and i are natural numbers, preferably natural numbers greater than or equal to 2.

[0060] The carry pulse CP output from the previous stage can be a set signal, and the carry pulse CP output from the next stage can be a reset signal.

[0061] Figure 2 An example is given where the Nth stage SR(N) is set by the carry pulse CP output from the (N-2)th stage SR(N-2) and reset by the carry pulse CP output from the (N+2)th stage SR(N+2). However, the invention is not limited thereto and can be modified in various ways depending on the number of clocks and the phase between them.

[0062] Figure 3 This is a specific circuit diagram of the Nth stage SR(N) according to a comparative example of the present invention.

[0063] exist Figure 3 In this context, the set signal Set can be the start pulse VST, the carry pulse CP output from the previous stage, or the set signal input from an external source. Similarly, the reset signal Reset can be the carry pulse CP output from the next stage or the reset signal input from an external source.

[0064] In addition, the Set and Reset signals can use either the carry clock signal CRCLK or the scan clock signal SCCLK.

[0065] The configuration for level N based on the comparative example will be described below.

[0066] like Figure 3As shown, the Nth stage includes: a node controller 11 that controls the voltages of the first node Q-node and the second node QB-node in accordance with the above-mentioned set signal Set and reset signal Reset; a carry pulse output unit 12 that outputs a first carry clock CRCLK1 as a carry pulse CP in accordance with the voltages of the first node Q-node and the second node QB-node; a first scan pulse output unit 13 that outputs a first scan clock SCCLK1 as a first scan pulse SP(1) in accordance with the voltages of the first node Q-node and the second node QB-node; a second scan pulse output unit 14 that outputs a second scan clock SCCLK2 as a second scan pulse SP(2) in accordance with the voltages of the first node Q-node and the second node QB-node; a third scan pulse output unit 15 that outputs a third scan clock SCCLK3 as a third scan pulse SP(3) in accordance with the voltages of the first node Q-node and the second node QB-node; and a fourth scan pulse output unit 16 that outputs a fourth scan clock SCCLK4 as a fourth scan pulse SP(4) in accordance with the voltages of the first node Q-node and the second node QB-node.

[0067] The node controller 11 performs a control operation so that the voltage phase of the first node Q-node and the voltage phase of the second node QB-node become opposite to each other, and performs a control operation so that the high level portion of the voltage of the first node Q-node is shorter than the high level portion of the voltage of the second node QB-node.

[0068] Each of the carry pulse output unit 12 and the first to fourth scan pulse output units 13 to 16 has the same configuration.

[0069] That is, each of the carry pulse output unit 12 and the first to fourth scan pulse output units 13 to 16 includes: a pull-up transistor T6cr, T6-1, T6-2, T6-3, or T6-4 that turns on or off to output the carry clock or the corresponding scan clock to an output terminal in accordance with the voltage of the first node Q-node; a pull-down transistor T7cr, T7-1, T7-2, T7-3, or T7-4 that turns on or off to output a low voltage power GVSS to the output terminal in accordance with the voltage of the second node QB-node; and a capacitor Cq0, Cq1, Cq2, Cq3, or Cq4 connected between the first node Q-node and the output terminal to bootstrap the gate voltage of each pull-up transistor.

[0070] The operation of the gate drive circuit according to the comparative example of the present application configured in this way will be described below.

[0071] Figure 4is an input / output waveform diagram of a gate drive circuit illustrating a comparative example according to the present application.

[0072] As shown in Figure 4 When the start signal VST or the carry pulse CP output from the preceding two stages is input at a high level, the node controller 11 applies a high-level voltage GVDD to the first node Q-node and a low-level voltage GVSS2 to the second node QB-node.

[0073] In this state, the pull-up transistor T6cr of the carry pulse output unit 12 is turned on, and the pull-down transistor T7cr is turned off. Therefore, the first carry clock CRCLK1 is output as the carry pulse CP.

[0074] When the first scan clock SCCLK1 is input at a high level, the first node Q-node is bootstrapped by the first capacitor Cq1 of the first scan pulse output unit 13, the pull-up transistor T6-1 of the first scan pulse output unit 13 is turned on, and the pull-down transistor T7-1 is turned off. Therefore, the first scan clock SCCLK1 is output as the first scan pulse SP(1).

[0075] When the second scan clock SCCLK2 is input at a high level, the first node Q-node is bootstrapped by the second capacitor Cq2 of the second scan pulse output unit 14, the pull-up transistor T6-2 of the second scan pulse output unit 14 is turned on, and the pull-down transistor T7-2 is turned off. Therefore, the second scan clock SCCLK2 is output as the second scan pulse SP(2).

[0076] When the third scan clock SCCLK3 is input at a high level, the first node Q-node is bootstrapped by the third capacitor Cq3 of the third scan pulse output unit 15, the pull-up transistor T6-3 of the third scan pulse output unit 15 is turned on, and the pull-down transistor T7-3 is turned off. Therefore, the third scan clock SCCLK3 is output as the third scan pulse SP(3).

[0077] When the fourth scan clock SCCLK4 is input at a high level, the first node Q-node is bootstrapped by the fourth capacitor Cq4 of the fourth scan pulse output unit 16, the pull-up transistor T6-4 of the fourth scan pulse output unit 16 is turned on, and the pull-down transistor T7-4 is turned off. Therefore, the fourth scan clock SCCLK4 is output as the fourth scan pulse SP(4).

[0078] However, since the second scan clock SCCLK2 is inverted to the low level when the fourth scan clock SCCLK4 is inverted to the high level, the voltage of the first node Q-node becomes lower than the bootstrap voltage when the third scan clock SCCLK3 is inputted at the high level when the fourth scan clock SCCLK4 is inputted at the high level.

[0079] Further, the voltage of the first node Q-node becomes lower when the third scan clock SCCLK3 is inverted to the low level, and the voltage of the first node Q-node is lowered again when the fourth scan clock SCCLK4 is inverted to the low level.

[0080] To this end, the falling time of the fourth scan pulse SP(4) outputted from the fourth scan pulse output unit 16 is increased. As a result, since the falling time of the scan pulse is increased in each last scan pulse output unit of each stage, the driving of the display device can become unstable.

[0081] Therefore, there is a need to improve the characteristics of the last scan pulse output unit of each stage.

[0082] Although Figure 4 The first carry clock CRCLK1 is exemplified to be synchronized with the first scan clock SCCLk1, but the present application is not limited thereto. That is, since the Nth stage is set by the carry pulse CP outputted from the (N-2)th stage, and the carry pulse outputted from the Nth stage sets the (N+2)th stage and resets the (N-2)th stage, the first carry clock CRCLK1 can be changed between the first scan clock SCCLk1 to the fourth scan clock SCCLk4 according to the situation.

[0083] Figure 5 is a detailed circuit diagram of the Nth stage SR(N) and the (N+1)th stage SR(N+1) according to the embodiment of the present application.

[0084] In Figure 5 , the set signal Set can be the start pulse VST, can be the carry pulse CP outputted from the previous stage, or can be a set signal inputted from the outside, and the reset signal Reset can be the carry pulse CP outputted from the next stage or a reset signal inputted from the outside.

[0085] Further, the set signal Set and the reset signal Reset can use the carry clock signal CRCLK or the scan clock signal SCCLK.

[0086] That is, the node controller 11 of the Nth stage can be set by the carry pulse CP(N-2) outputted from the (N-2)th stage, and can be reset by the carry pulse CP(N+2) outputted from the (N+2)th stage.

[0087] As described above, since the gate driving circuit is driven by 3 carry clocks and 12 scan clocks, when 1 carry pulse output unit and 4 scan pulse output units are provided at the Nth stage, the Nth stage is driven by 1 carry clock and 4 scan clocks.

[0088] The Nth stage and the (N+1)th stage have the same configuration. However, for the same reason as described above, the carry clock and the scan clock provided to the Nth stage are different from the carry clock and the scan clock provided to the (N+1)th stage.

[0089] Therefore, the Nth stage includes a node controller 11 that controls voltages of a first node Q-node and a second node QB-node according to the set signal Set and the reset signal Reset described above; a first carry pulse output unit 12 that outputs a first carry clock CRCLK1 as a carry pulse CP according to the voltages of the first node Q-node and the second node QB-node; a first scan pulse output unit 13 that outputs a first scan clock SCCLK1 as a first scan pulse SP(1) according to the voltages of the first node Q-node and the second node QB-node; a second scan pulse output unit 14 that outputs a second scan clock SCCLK2 as a second scan pulse SP(2) according to the voltages of the first node Q-node and the second node QB-node; a third scan pulse output unit 15 that outputs a third scan clock SCCLK3 as a third scan pulse SP(3) according to the voltages of the first node Q-node and the second node QB-node; and a fourth scan pulse output unit 16 that outputs a fourth scan clock SCCLK4 as a fourth scan pulse SP(4) according to the voltages of the first node Q-node and the second node QB-node and the voltage of the first node Q-node of the (N+1)th stage.

[0090] The (N+1)th stage includes: a node controller 11 that controls voltages of a first node Q-node and a second node QB-node according to a set signal Set and a reset signal Reset; a second carry pulse output unit 22 that outputs a second carry clock CRCLK2 as a carry pulse CP according to the voltages of the first node Q-node and the second node QB-node; a fifth scan pulse output unit 23 that outputs a fifth scan clock SCCLK5 as a fifth scan pulse SP(5) according to the voltages of the first node Q-node and the second node QB-node; a sixth scan pulse output unit 24 that outputs a sixth scan clock SCCLK6 as a sixth scan pulse SP(6) according to the voltages of the first node Q-node and the second node QB-node; a seventh scan pulse output unit 25 that outputs a seventh scan clock SCCLK7 as a seventh scan pulse SP(7) according to the voltages of the first node Q-node and the second node QB-node; and an eighth scan pulse output unit 26 that outputs an eighth scan clock SCCLK8 as an eighth scan pulse SP(8) according to the voltages of the first node Q-node and the second node QB-node and the voltage of the first node Q-node of the (N+1)th stage.

[0091] The node controller 11 performs a control operation so that the voltage phase of the first node Q-node and the voltage phase of the second node QB-node become opposite to each other, and performs a control operation so that the high level portion of the voltage of the first node Q-node is shorter than the high level portion of the voltage of the second node QB-node.

[0092] Each of the first carry pulse output unit 12 and the second carry pulse output unit 22 and the first scan pulse output unit 13 to the third scan pulse output unit 15 and the fifth scan pulse output unit 23 to the seventh scan pulse output unit 25 has the same configuration as described in the comparative example.

[0093] That is, each of the first carry pulse output unit 12 and the second carry pulse output unit 22 and the first scan pulse output unit 13 to the third scan pulse output unit 15 and the fifth scan pulse output unit 23 to the seventh scan pulse output unit 25 includes: a pull-up transistor T6cr, T6-1, T6-2, or T6-3 that turns on or off according to the voltage of the first node Q-node to output a carry clock or a corresponding scan clock to an output terminal; a pull-down transistor T7cr, T7-1, T7-2, or T7-3 that turns on or off according to the voltage of the second node QB-node to output a low voltage power GVSS to the output terminal; a capacitor Cq0, Cq1, Cq2, or Cq3 connected between the first node Q-node and the output terminal to bootstrap the gate voltage of each pull-up transistor.

[0094] Meanwhile, the fourth scan pulse output unit 16 and the eighth scan pulse output unit 26 are configured differently from the first to third scan pulse output units 13 to 15 and the fifth to seventh scan pulse output units 23 to 25.

[0095] That is, the fourth scan pulse output unit 16 includes a first pull-up transistor T6-4 turned on or off according to a voltage of a first node Q-node to output a corresponding scan clock SCCLK4 to an output terminal, a second pull-up transistor T6-5 turned on or off according to a voltage of a first node Q_(N+1) of a next stage to output the corresponding scan clock SCCLK4 to the output terminal, a pull-down transistor T7-4 turned on or off according to a voltage of a second node QB-node to output a low voltage power GVSS to the output terminal, and a capacitor Cq4 connected between the first node Q-node and the output terminal to bootstrap a gate voltage of the first pull-up transistor T6-4.

[0096] The eighth scan pulse output unit 26 includes a first pull-up transistor T6-4 turned on or off according to a voltage of a first node Q-node to output a corresponding scan clock SCCLK8 to an output terminal, a second pull-up transistor T6-5 turned on or off according to a voltage of a first node Q_(N+2) of a next stage to output the corresponding scan clock SCCLK8 to the output terminal, a pull-down transistor T7-4 turned on or off according to a voltage of a second node QB-node to output a low voltage power GVSS to the output terminal, and a capacitor Cq4 connected between the first node Q-node and the output terminal to bootstrap a gate voltage of the first pull-up transistor T6-4.

[0097] The operation of the gate driving circuit according to the embodiment of the present application configured as described above will be described below.

[0098] Figure 6 is an input / output waveform diagram of the gate driving circuit according to the embodiment of the present application.

[0099] As shown in FIG. 10, in the Nth stage, when the start signal VST or the carry pulse CP output from the (N-2)th stage is input at a high level, the node controller 11 applies a high level voltage GVDD to the first node Q-node and a low level voltage GVSS2 to the second node QB-node. Figure 6 In this state, the pull-up transistor T6cr of the carry pulse output unit 12 is turned on, and the pull-down transistor T7cr is turned off, thereby outputting the carry clock CRCLK as the carry pulse CP.

[0100]

[0101] ​When the first scan clock SCCLK1 is input at a high level, the first node Q-node is boosted by the first capacitor Cq1 of the first scan pulse output unit 13, the pull-up transistor T6-1 of the first scan pulse output unit 13 is turned on, and the pull-down transistor T7-1 is turned off, thereby outputting the first scan clock SCCLK1 as the first scan pulse SP(1).

[0102] When the second scan clock SCCLK2 is input at a high level, the first node Q-node is boosted by the second capacitor Cq2 of the second scan pulse output unit 14, the pull-up transistor T6-2 of the second scan pulse output unit 14 is turned on, and the pull-down transistor T7-2 is turned off, thereby outputting the second scan clock SCCLK2 as the second scan pulse SP(2).

[0103] When the third scan clock SCCLK3 is input at a high level, the first node Q-node is boosted by the third capacitor Cq3 of the third scan pulse output unit 15, the pull-up transistor T6-3 of the third scan pulse output unit 15 is turned on, and the pull-down transistor T7-3 is turned off, thereby outputting the third scan clock SCCLK3 as the third scan pulse SP(3).

[0104] When the fourth scan clock SCCLK4 is input at a high level, the first node Q-node is boosted by the fourth capacitor Cq4 of the fourth scan pulse output unit 16, the pull-up transistor T6-4 of the fourth scan pulse output unit is turned on, and the pull-down transistor T7-4 is turned off, thereby outputting the fourth scan clock SCCLK4 as the fourth scan pulse SP(4).

[0105] However, since the second scan clock SCCLK2 is turned to a low level when the fourth scan clock SCCLK4 is turned to a high level, the voltage of the first node Q-node when the fourth scan clock SCCLK4 is input at a high level becomes lower than the boosted voltage when the third scan clock SCCLK3 is input at a high level.

[0106] In addition, the voltage of the first node Q-node becomes lower when the third scan clock SCCLK3 is turned to a low level, and the voltage of the first node Q-node is lowered again when the fourth scan clock SCCLK4 is turned to a low level.

[0107] To this end, the falling time of the fourth scan pulse SP(4) output from the fourth scan pulse output unit 16 can be increased.

[0108] However, the second pull-up transistor T6-5 of the fourth scan pulse output unit 16 is turned on according to the voltage Q_(N+1) of the first node of the (N+1)th stage to output the fourth scan clock SCCLK4 as the fourth scan pulse SP(4).

[0109] As Figure 6 shown, when the fourth scan clock SCCLK4 becomes a falling edge, since the voltage Q_(N+1) of the first node of the (N+1)th stage remains at a level higher than the voltage Q_N of the first node of the Nth stage SR(N), the falling time of the fourth scan pulse SP(4) is reduced.

[0110] Therefore, the present application can improve the output characteristics of the fourth scan pulse output unit 16.

[0111] Since the operation of the (N+1)th stage is only different in the provided scan clock, and is performed as described in Figure 6 , the description of the operation of the (N+1)th stage is omitted.

[0112] Figure 6 It is shown that the first carry clock CRCLK1 is synchronized with the first scan clock SCCLK1. However, the present application is not limited thereto. That is, since the Nth stage is set by the carry pulse CP output from the (N-2)th stage, and the carry pulse output from the Nth stage sets the (N+2)th stage and resets the (N-2)th stage, the first carry clock CRCLK1 can vary between the first scan clock SCCLk1 to the fourth scan clock SCCLk4 according to the situation.

[0113] Figure 7 is a graph comparing the scan pulse output of the fourth scan pulse output unit 16 according to the comparative example and the embodiment of the present application.

[0114] As Figure 7 shown, the falling time of the fourth scan pulse SP(4) according to the embodiment of the present application can be reduced more than the falling time of the fourth scan pulse SP(4) according to the comparative example.

[0115] The gate driving circuit of the present application having the above features and the display device using the same have the following effects.

[0116] According to the present application, since the last scan pulse output unit also outputs the corresponding scan clock as the scan pulse according to the voltage of the Q node of the next stage, the falling time of the scan pulse can be reduced, and the output characteristics of the scan pulse output unit can be improved.

[0117] Therefore, the gate driving circuit can be stably driven, and the display quality can be improved.

[0118] It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A gate drive circuit comprising a plurality of slave-connected stages, wherein: Level N, where n is a natural number, includes: A node controller is configured to control the voltages of a first node and a second node based on set and reset signals; and Multiple scan pulse output units are configured to receive multiple scan clocks and output each scan clock as a scan pulse based on the voltages of the first node and the second node. Among them, the last scan pulse output unit of the plurality of scan pulse output units also outputs the corresponding scan clock as the scan pulse based on the first node voltage of the (N+1)th stage. The final scan pulse output unit includes: The first pull-up transistor is turned on or off according to the voltage of the first node to output the corresponding scan clock to the output terminal; The second pull-up transistor is turned on or off according to the first node voltage of the (N+1)th stage to output the corresponding scan clock to the output terminal. The first pull-up transistor and the second pull-up transistor are connected in parallel.

2. The gate drive circuit according to claim 1 further includes a carry signal output unit, configured to output a carry clock as a carry pulse based on the voltages of the first node and the second node.

3. The gate driving circuit according to claim 1, wherein, The final scan pulse output unit also includes: The pull-down transistor is turned on or off according to the voltage of the second node to output low-voltage power to the output terminal.

4. The gate driving circuit according to claim 1, wherein, The final scan pulse output unit also includes a capacitor connected between the gate electrode and the output terminal of the first pull-up transistor to bootstrap the first node.

5. A display device, comprising: The display panel includes data lines, gate lines, and sub-pixels; The data driving circuit is configured to provide the data line with a data signal of the input image; as well as A gate drive circuit is configured to provide a gate signal to the gate line, wherein: The gate drive circuit includes multiple slave-connected stages. Level N, where n is a natural number, includes: A node controller is configured to control the voltages of a first node and a second node based on set and reset signals; and Multiple scan pulse output units are configured to receive multiple scan clocks and output each scan clock as a scan pulse based on the voltage of the first node and the second node. Among them, the last scan pulse output unit of the plurality of scan pulse output units also outputs the corresponding scan clock as the scan pulse based on the first node voltage of the (N+1)th stage. The final scan pulse output unit includes: The first pull-up transistor is turned on or off according to the voltage of the first node to output the corresponding scan clock to the output terminal; The second pull-up transistor is turned on or off according to the first node voltage of the (N+1)th stage to output the corresponding scan clock to the output terminal. The first pull-up transistor and the second pull-up transistor are connected in parallel.

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