Display panel and display

Abstract

The embodiments of the present application provide a display panel and a display, wherein each display partition includes multiple rows of pixels, each row of pixels includes multiple pixel circuits; each display partition corresponds to multiple gating units, each gating unit is connected to a row of pixels in its corresponding display partition; a gate drive circuit is connected to the gating units in a one-to-one correspondence; a timing control chip is used to generate a local update signal and a corresponding timing initialization voltage Vinit signal according to the partition refresh status of the frame to be displayed; the gate drive circuit is used to provide a gate drive signal for a data signal switch to the corresponding gating unit; the gating unit is used to output the gate drive signal to the pixel circuit connected to it or not output the gate drive signal in response to the control of the local update signal; the pixel circuit refreshes the display in response to receiving the gate drive signal and the initialization voltage signal; or maintains the display of the previous frame in response to receiving the initialization voltage signal. The flicker problem of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display. Background Art

[0002] In the current display industry, to save power, many manufacturers have proposed a zoned frequency conversion solution. This involves dividing a display panel into multiple zones, each with a different refresh rate. This allows the refreshed zone to update while the non-refreshed zone retains the previous frame's data, further conserving power.

[0003] However, for zone-based variable frequency display, a display panel has multiple refresh rates. This means that each zone requires an independently controlled initialization Vinit voltage when debugging VRR (Variable Refresh Rate, often referring to display panel frequency switching flicker) and Flicker (often referring to static flicker in a display panel). For example, the 8T1C pixel circuit of LTPO (Low Temperature Polycrystalline Oxide) uses three sets of Vinit voltages. When the display panel is divided into three zones, nine sets of Vinit voltages are required. However, currently developed driver chips do not support four or more Vinit voltages. Therefore, using independently controlled Vinit voltages for each zone to debug display panel flicker has become an urgent problem that needs to be solved. Summary of the Invention

[0004] An object of the embodiments of the present application is to provide a display panel and a display to improve the flicker problem of the display panel.

[0005] The specific technical solutions are as follows:

[0006] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0007] A timing control chip, a plurality of gate drive circuits, a plurality of gating units and a plurality of display partitions; each of the display partitions includes a plurality of pixel rows, and each of the pixel rows includes a plurality of pixel circuits;

[0008] Each display partition corresponds to a plurality of gating units, each of which is connected to a row of pixels in its corresponding display partition; the gate driving circuit is connected to the gating units in a one-to-one correspondence;

[0009] The timing control chip is used to generate a local update signal of a corresponding timing and an initialization voltage Vinit signal of a corresponding timing according to the partition refresh status of the frame to be displayed, wherein the partition refresh status indicates whether each display partition is refreshed; different partition refresh statuses correspond to local update signals of different timings and initialization voltage signals of different timings;

[0010] The gate driving circuit is used to provide a gate driving signal of a data signal switch to the corresponding gating unit;

[0011] The gating unit is configured to output the gate driving signal to the pixel circuit connected thereto or not output the gate driving signal in response to the control of the local update signal;

[0012] The pixel circuit is used to refresh the display in response to receiving a gate drive signal and an initialization voltage signal; or to maintain the previous frame display in response to receiving an initialization voltage signal.

[0013] In one possible embodiment, the number of display partitions is N, each image frame includes N timing stages, and the local update signal of the i-th timing stage is used to control the on and off of each selection unit connected to the i-th display partition, where N is an integer greater than 1, i∈N.

[0014] In one possible implementation, the pixel circuit includes a first initialization voltage signal input terminal, a second initialization voltage signal input terminal, and a third initialization voltage signal input terminal; the timing control chip includes a first initialization voltage signal output terminal, a second initialization voltage signal output terminal, and a third initialization voltage signal output terminal;

[0015] The first initialization voltage signal output terminal of the timing control chip is connected to the first initialization voltage signal input terminal of each pixel circuit, the second initialization voltage signal output terminal of the timing control chip is connected to the second initialization voltage signal input terminal of each pixel circuit, and the third initialization voltage signal output terminal of the timing control chip is connected to the third initialization voltage signal input terminal of each pixel circuit.

[0016] In a possible implementation, the pixel circuit further includes:

[0017] A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a capacitor, and a light-emitting device;

[0018] The control terminal of the first transistor is connected to the first initialization signal control terminal, the first terminal of the first transistor is respectively connected to the second terminal of the second transistor, the second terminal of the third transistor, and the first terminal of the sixth transistor, and the second terminal of the first transistor is connected to the first initialization voltage signal input terminal;

[0019] The control terminal of the second transistor is connected to the first gate drive signal terminal, and the first terminal of the second transistor is connected to the second terminal of the capacitor and the control terminal of the third transistor respectively;

[0020] The first end of the third transistor is respectively connected to the first end of the fourth transistor, the second end of the fifth transistor, and the first end of the eighth transistor;

[0021] The control terminal of the fourth transistor is connected to the second gate drive signal terminal, and the second terminal of the fourth transistor is connected to the data signal input terminal;

[0022] The control terminal of the fifth transistor is connected to the light emitting control signal terminal, and the first terminal of the fifth transistor is connected to the positive terminal of the power supply;

[0023] The control terminal of the sixth transistor is connected to the light emitting control signal terminal, and the second terminal of the sixth transistor is connected to the anode of the light emitting device and the first terminal of the seventh transistor respectively;

[0024] The control terminal of the seventh transistor is connected to the second initialization signal control terminal, and the second terminal of the seventh transistor is connected to the second initialization voltage signal input terminal;

[0025] The control terminal of the eighth transistor is connected to the second initialization signal control terminal, and the second terminal of the eighth transistor is connected to the third initialization voltage signal input terminal.

[0026] In one possible embodiment, the timing control chip is specifically used to generate a first initialization voltage signal, a second initialization voltage signal, and a third initialization voltage signal corresponding to the timing according to the partition refresh status of the frame to be displayed, and output the first initialization voltage signal through the first initialization voltage signal output end, output the second initialization voltage signal through the second initialization voltage signal output end, and output the third initialization voltage signal through the third initialization voltage signal output end.

[0027] In a possible implementation, the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal in the i-th timing phase are used to provide a refresh voltage or a hold voltage for the i-th display partition;

[0028] Wherein, when the i-th display partition is a refresh area, the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal in the i-th timing phase are used to provide a refresh voltage for the i-th display partition;

[0029] When the i-th display partition is a holding area, the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal in the i-th timing phase are used to provide a holding voltage for the i-th display partition;

[0030] For any one of the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal, a refresh voltage of the initialization voltage signal and a hold voltage thereof have different voltage values.

[0031] In a possible implementation, for any one of the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal, an absolute value of a voltage difference between a refresh voltage and a hold voltage of the initialization voltage signal is a preset debugging value.

[0032] In a possible implementation, for any one of the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal, the refresh voltage of the initialization voltage signal is the same as the absolute value of the hold voltage;

[0033] or;

[0034] The voltage value of the refresh voltage of the initialization voltage signal is zero;

[0035] or;

[0036] The voltage value of the holding voltage of the initialization voltage signal is zero.

[0037] In a possible implementation, the timing control chip is further configured to provide timing signals for the first initialization signal control terminal, the second initialization signal control terminal, the light emitting control signal terminal, the first gate drive signal terminal, and the second gate drive signal terminal.

[0038] In a second aspect, an embodiment of the present application provides a display, comprising the display panel described in any one of the first aspects above.

[0039] Beneficial effects of the embodiments of the present application:

[0040] The embodiments of the present application provide a display panel and a display, wherein the display panel includes: a timing control chip, multiple gate drive circuits, multiple gating units, and multiple display partitions; each display partition includes multiple rows of pixels, each row of pixels includes multiple pixel circuits; each display partition corresponds to multiple gating units, each gating unit is connected to a row of pixels in its corresponding display partition; the gate drive circuits are connected to the gating units in a one-to-one correspondence; the timing control chip is used to generate a local update signal of the corresponding timing and an initialization voltage Vinit signal of the corresponding timing according to the partition refresh status of the frame to be displayed , wherein the partition refresh status indicates whether each display partition is refreshed; different partition refresh statuses correspond to local update signals with different timings and initialization voltage signals with different timings; the gate drive circuit is used to provide a gate drive signal for a data signal switch to the corresponding selection unit; the selection unit is used to output the gate drive signal to the pixel circuit connected to it, or not output the gate drive signal, in response to the control of the local update signal; the pixel circuit is used to refresh the display in response to receiving the gate drive signal and the initialization voltage signal; or to maintain the previous frame display in response to receiving the initialization voltage signal. The initialization voltage Vinit signal generated by the timing control chip is linked with the local update signal, that is, the timing of the initialization voltage Vinit signal can change with the timing of the local update signal. Therefore, for each display partition, the initialization voltage Vinit signal can change according to the refresh status of the display partition, without adding an additional initialization voltage Vinit signal, which can improve the flicker problem of the display panel.

[0041] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0043] Figure 1 A schematic diagram of controlling refresh of different partitions through multiple control signals STV signals in the related art;

[0044] Figure 2 A schematic diagram of a first structure of a display panel provided in an embodiment of the present application;

[0045] Figure 3a This is a timing diagram of the local update signal controlling the refresh / hold of each display partition when the number of display partitions is 3;

[0046] Figure 3b Schematic diagram of the relationship between the local update signal and the gate drive signal output;

[0047] Figure 4 A schematic diagram of a second structure of a display panel provided in an embodiment of the present application;

[0048] Figure 5 A schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0049] Figure 6 is a schematic diagram showing how the timing of the first initialization voltage signal Vinit1, the second initialization voltage signal Vinit2, and the third initialization voltage signal Vinit3 changes with the timing of the local update signal;

[0050] Figure 7 Schematic diagram of the corresponding relationship between Vinit1 and P-Reset when the timing of Vinit1 changes with the timing of the local update signal;

[0051] Figure 8 Based on Figure 5 Schematic diagram of the timing of each signal in the pixel circuit;

[0052] Figure 9 A schematic diagram of the structure of a display provided in an embodiment of the present application; DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0054] First, a brief description of the partition frequency conversion in the related art is given. The partition frequency conversion solution is to divide a display panel into multiple areas, each area can be set with a different refresh rate, specifically through multiple control signals STV signals to control the refresh of different areas, such as Figure 1As shown, taking the display panel as divided into three areas (partition 1, partition 2, and partition 3) as an example, for each partition, when the partition needs to be refreshed, the partial update signal corresponding to the partition is pulled high (the high level of the partial update signal is on, and the low level is off), and the STV signal is input (STV1 signal corresponds to partition 1, STV 2 signal corresponds to partition 2, and STV 3 signal corresponds to partition 3) to refresh the display; when the partition does not need to be refreshed, the partial update signal corresponding to the partition is turned off, there is no STV signal input, and no refresh is performed.

[0055] In conventional display panel debugging, there is a brightness difference between the refresh frame and the hold frame. The brightness of the hold frame and the refresh frame is made the same by debugging the Vinit voltage. However, for partition frequency conversion, a display panel has multiple refresh rates. When debugging VRR (Variable refresh rate, often refers to the display panel frequency switching flicker) and Flicker (often refers to the static flicker of the display panel), it means that each partition requires an independently controlled Vinit voltage. For example, the 8T1C pixel circuit of LTPO (Low Temperature Polycrystalline Oxide) uses 3 groups of Vinit voltages. When the display panel is divided into three areas, 9 groups of Vinit voltages are required. The currently developed driver chip does not support 4 or more Vinit voltages. Therefore, using an independently controlled Vinit voltage for each partition to debug the display panel flicker has become an urgent problem to be solved.

[0056] In order to solve the above problems, the present invention provides a display panel 1. Figure 2 , the display panel 1 includes:

[0057] A timing control chip 11, a plurality of gate driving circuits 12, a plurality of gating units 13 and a plurality of display partitions 14; each of the display partitions 14 includes a plurality of pixel rows 141, and each of the pixel rows 141 includes a plurality of pixel circuits 1411;

[0058] Each display partition 14 corresponds to a plurality of gating units 13 , and each gating unit 13 is connected to a row of pixels 141 in its corresponding display partition 14 ; the gate driving circuit 12 is connected to the gating units 13 in a one-to-one correspondence;

[0059] The timing control chip 11 is used to generate a local update signal of a corresponding timing and an initialization voltage Vinit signal of a corresponding timing according to the partition refresh status of the frame to be displayed, wherein the partition refresh status indicates whether each display partition is refreshed; different partition refresh statuses correspond to local update signals of different timings and initialization voltage signals of different timings;

[0060] The gate drive circuit 12 is used to provide a gate drive signal of a data signal switch to the corresponding gating unit;

[0061] The gating unit 13 is configured to output the gate driving signal to the pixel circuit connected thereto or not output the gate driving signal in response to the control of the local update signal;

[0062] The pixel circuit 1411 is configured to refresh the display in response to receiving a gate driving signal and an initialization voltage signal; or to maintain the previous frame display in response to receiving an initialization voltage signal.

[0063] It is understood that this application does not specifically limit the number of display partitions. Figure 2 The layout of the display partition, gating unit, gate drive circuit, pixel circuit, etc. shown in is not unique. Figure 2 The concept of "multiple" is just given as an illustration.

[0064] In an embodiment of the present application, the initialization voltage Vinit signal generated by the timing control chip is linked with the local update signal, that is, the timing of the initialization voltage Vinit signal can change with the timing of the local update signal, so that for each display partition, the initialization voltage Vinit signal can change according to the refresh situation of the display partition, without adding an additional initialization voltage Vinit signal, which can improve the flickering problem of the display panel.

[0065] In one possible embodiment, the number of display partitions is N, each image frame includes N timing stages, and the local update signal of the i-th timing stage is used to control the on and off of each selection unit connected to the i-th display partition, where N is an integer greater than 1, i∈N.

[0066] The number of display partitions can be 3, 5, 10, etc. In an example, when the number of display partitions is 3, there are 2 3 =8 refresh methods, Figure 3aThree of the refresh modes are shown as examples. The first is: the first display partition (display partition 1) is refreshed, the second display partition (display partition 2) is maintained, and the third display partition (display partition 3) is refreshed; the second is: the first display partition (display partition 1) is maintained, the second display partition (display partition 2) is maintained, and the third display partition (display partition 3) is refreshed; the third is: the first display partition (display partition 1) is maintained, the second display partition (display partition 2) is refreshed, and the third display partition (display partition 3) is maintained. Figure 3a Each image frame includes three timing stages. The local update signal in the first timing stage is used to control the on / off of each gating unit connected to the first display partition. When the local update signal in the first timing stage is at a high level, the gating units connected to the first display partition are controlled to be turned on, and the gate drive signal is output to the pixel circuit of the first display partition, and the first display partition is refreshed. When the local update signal in the first timing stage is at a low level, the gating units connected to the first display partition are controlled to be turned off, and the gate drive signal is not output to the pixel circuit of the first display partition, and the first display partition maintains the previous frame display. The local update signal in the second timing stage is used to control the on / off of each gating unit connected to the second display partition. The local update signal in the third timing stage is used to control the on / off of each gating unit connected to the third display partition. The analysis process is similar.

[0067] The relationship between the local update signal and the gate drive signal output is shown in the following figure: Figure 3b As shown, Nout is the gate drive signal received by each pixel row, N-mode indicates a frame in which each display partition needs to be refreshed, L-mode indicates a frame in which at least one display partition does not need to be refreshed, and Frame indicates "frame".

[0068] In an embodiment of the present application, different partition refresh conditions correspond to local update signals with different timings. The local update signal of the i-th timing stage is used to control the on and off of each selection unit connected to the i-th display partition. When the local update signal is at a high level, the selection unit is controlled to be turned on for refreshing; when the local update signal is at a low level, the selection unit is controlled to be turned off for maintenance.

[0069] In one possible implementation, see Figure 4 The pixel circuit 1411 includes a first initialization voltage signal Vinit1 input terminal, a second initialization voltage signal Vinit2 input terminal, and a third initialization voltage signal Vinit3 input terminal; the timing control chip 11 includes a first initialization voltage signal Vinit1 output terminal, a second initialization voltage signal Vinit2 output terminal, and a third initialization voltage signal Vinit3 output terminal;

[0070] The first initialization voltage signal Vinit1 output end of the timing control chip 11 is connected to the first initialization voltage signal Vinit1 input end of each pixel circuit 1411, the second initialization voltage signal Vinit2 output end of the timing control chip 11 is connected to the second initialization voltage signal Vinit2 input end of each pixel circuit 1411, and the third initialization voltage signal Vinit3 output end of the timing control chip 11 is connected to the third initialization voltage signal Vinit3 input end of each pixel circuit 1411.

[0071] In the embodiment of the present application, the pixel circuit includes three initialization voltage signal input terminals, the timing control chip includes three corresponding initialization voltage signal output terminals, and the timing control chip is used to generate the initialization voltage Vinit signal.

[0072] In one possible implementation, see Figure 5 , the pixel circuit 1411 further includes:

[0073] a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a capacitor C, and a light-emitting device OLED;

[0074] The control end of the first transistor T1 is connected to the first initialization signal control N-Reset end, the first end of the first transistor T1 is respectively connected to the second end of the second transistor T2, the second end of the third transistor T3, and the first end of the sixth transistor T6, and the second end of the first transistor T1 is connected to the first initialization voltage signal Vinit1 input end;

[0075] The control terminal of the second transistor T2 is connected to the first gate drive signal Gate_N terminal, and the first terminal of the second transistor T2 is connected to the second terminal of the capacitor C and the control terminal of the third transistor T3 respectively;

[0076] The first end of the third transistor T3 is respectively connected to the first end of the fourth transistor T4, the second end of the fifth transistor T5, and the first end of the eighth transistor T8;

[0077] The control terminal of the fourth transistor T4 is connected to the second gate drive signal Gate_P terminal, and the second terminal of the fourth transistor T4 is connected to the data signal Vdata input terminal;

[0078] The control end of the fifth transistor T5 is connected to the light emitting control signal EM end, and the first end of the fifth transistor T5 is connected to the positive power supply terminal VDD;

[0079] The control terminal of the sixth transistor T6 is connected to the light emitting control signal EM terminal, and the second terminal of the sixth transistor T6 is connected to the anode of the light emitting device OLED and the first terminal of the seventh transistor T7 respectively;

[0080] The control terminal of the seventh transistor T7 is connected to the second initialization signal control P-Reset terminal, and the second terminal of the seventh transistor T7 is connected to the second initialization voltage signal Vinit2 input terminal;

[0081] The control terminal of the eighth transistor T8 is connected to the second initialization signal control P-Reset terminal, and the second terminal of the eighth transistor T8 is connected to the third initialization voltage signal Vinit3 input terminal.

[0082] The cathode of the light emitting device OLED is connected to the negative power terminal VSS.

[0083] It is understood that for any transistor in the pixel circuit of the present application, the transistor can be an N-type transistor or a P-type transistor, and the specific selection can be made according to the actual situation; the first end of the transistor is the source or drain, and the second end of the transistor is the drain or source corresponding to the first end. It is understood that the transistor can be a P-type transistor or an N-type transistor, and the specific selection can be made according to the actual situation, but the device connection method of the circuit needs to be adjusted accordingly. Such replacement schemes are still within the scope of protection of the present application.

[0084] It can be understood that the transistors used in the circuit of the present application can be MOS tubes (Metal-Oxide-Semiconductor Field-Effect Transistors), or TFT tubes (Thin Film Transistors) or other types of transistors. The specific selection can be made according to the actual situation. The replacement scheme is still within the scope of protection of the present application. The connection method of the TFT tube or other types of transistors can refer to the connection method of the MOS tube, and will not be repeated here.

[0085] In one possible embodiment, the timing control chip 11 is specifically used to generate a first initialization voltage signal Vinit1, a second initialization voltage signal Vinit2, and a third initialization voltage signal Vinit3 corresponding to the timing according to the partition refresh status of the frame to be displayed, and output the first initialization voltage signal through the first initialization voltage signal Vinit1 output end, output the second initialization voltage signal through the second initialization voltage signal Vinit2 output end, and output the third initialization voltage signal through the third initialization voltage signal Vinit3 output end.

[0086] In a possible implementation, the first initialization voltage signal Vinit1, the second initialization voltage signal Vinit2, and the third initialization voltage signal Vinit3 in the i-th timing phase are used to provide a refresh voltage or a hold voltage for the i-th display partition;

[0087] When the i-th display partition is a refresh area, the first initialization voltage signal Vinit1, the second initialization voltage signal Vinit2, and the third initialization voltage signal Vinit3 in the i-th timing phase are used to provide a refresh voltage for the i-th display partition;

[0088] When the i-th display partition is the holding area, the first initialization voltage signal Vinit1, the second initialization voltage signal Vinit2, and the third initialization voltage signal Vinit3 in the i-th timing phase are used to provide the holding voltage of the i-th display partition;

[0089] For any initialization voltage signal among the first initialization voltage signal Vinit1 , the second initialization voltage signal Vinit2 , and the third initialization voltage signal Vinit3 , the refresh voltage and the hold voltage of the initialization voltage signal are different in voltage value.

[0090] In an example, when the number of displayed partitions is 3, see Figure 6 The following example illustrates the process of refreshing the first display partition (display partition 1), maintaining the second display partition (display partition 2), and refreshing the third display partition (display partition 3). Specifically, the local update signal is high during the first timing phase of the frame to be displayed, low during the second timing phase, and high during the third timing phase. The timing control chip generates the first, second, and third initialization voltage signals Vinit1, Vinit2, and Vinit3 in corresponding timings based on the refresh conditions of the partitions of the frame to be displayed (the timing changes of the local update signal, high-low-high).

[0091] The first display partition is the refresh area. The first initialization voltage signal Vinit1, the second initialization voltage signal Vinit2, and the third initialization voltage signal Vinit3 in the first timing phase are used to provide the refresh voltage for the first display partition. The second display partition is the hold area. The first initialization voltage signal Vinit1, the second initialization voltage signal Vinit2, and the third initialization voltage signal Vinit3 in the second timing phase are used to provide the hold voltage for the second display partition. The third display partition is the refresh area. The first initialization voltage signal Vinit1, the second initialization voltage signal Vinit2, and the third initialization voltage signal Vinit3 in the third timing phase are used to provide the refresh voltage for the third display partition. Wherein, a2, b2, and c2 are refresh voltages, and a1, b1, and c1 are hold voltages. The voltage values ​​of a1 and a2 are different, the voltage values ​​of b1 and b2 are different, and the voltage values ​​of c1 and c2 are different.

[0092] In an embodiment of the present application, the timing of the first initialization voltage signal Vinit1, the second initialization voltage signal Vinit2, and the third initialization voltage signal Vinit3 can change with the timing of the local update signal. For each initialization voltage signal Vinit, a refresh voltage is used when the display partition is a refresh area, and a hold voltage is used when the display partition is a hold area. In one example, different settings can also be made for different DBVs (display brightness), that is, the initialization voltage signal Vinit can be dynamically adjusted.

[0093] In a possible implementation, for any one of the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal, an absolute value of a voltage difference between a refresh voltage and a hold voltage of the initialization voltage signal is a preset debugging value.

[0094] For any of the first, second, and third initialization voltage signals Vinit1, Vinit2, and Vinit3, there are only two voltage states (a refresh voltage and a hold voltage). Therefore, the absolute value of the voltage difference between the refresh voltage and the hold voltage of the initialization voltage signal is fixed. The preset debugging value can be selected based on the degree of flicker during the display panel debugging process to improve the flicker problem. The timing control chip is used to record the preset debugging value.

[0095] In the embodiment of the present application, for any initialization voltage signal, the absolute value of the voltage difference between the refresh voltage and the hold voltage of the initialization voltage signal is a preset debugging value.

[0096] In a possible implementation, for any one of the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal, the refresh voltage of the initialization voltage signal is the same as the absolute value of the hold voltage;

[0097] or;

[0098] The voltage value of the refresh voltage of the initialization voltage signal is zero;

[0099] or;

[0100] The voltage value of the holding voltage of the initialization voltage signal is zero.

[0101] See also Figure 6 For the first initialization voltage signal Vinit1, the absolute value of a1 can be equal to the absolute value of a2 (the high and low levels of a1 and a2 are opposite), or the voltage value of a2 can be zero and the absolute value of a1 can be a preset debugging value, or the voltage value of a1 can be zero and the absolute value of a2 can be a preset debugging value. For example, when the preset debugging value is 6V, a1 = -3V, a2 = 3V; or a2 = 0V, a1 = -6V; or a1 = 0V, a2 = 6V.

[0102] See also Figure 5 The initialization voltage signal Vinit is controlled by the first initialization signal control terminal N-Reset and the second initialization signal control terminal P-Reset. These two control signals are transmitted row by row from the first row down. When they reach the retention area, the Vinit voltage also corresponds to the retention voltage. The Vinit voltage acts on the entire AA area (the operational area), but it can only enter the pixel circuit for reset when P-reset and N-reset are turned on. Figure 7 Taking the first initialization voltage signal Vinit1 as an example, the corresponding relationship between Vinit1 and P-Reset is shown when the timing of Vinit1 changes with the timing of the local update signal. Figure 7 The refresh voltage from the first pixel row to the K-1 pixel row is Vinit1, which may be different from the hold voltage set for the K pixel row. The Vsync voltage refers to the column synchronization signal.

[0103] In an embodiment of the present application, for any initialization voltage signal, the refresh voltage of the initialization voltage signal is the same as the absolute value of the holding voltage; or, the voltage value of the refresh voltage of the initialization voltage signal is zero, and the absolute value of the voltage value of the holding voltage is a preset debugging value; or, the voltage value of the holding voltage of the initialization voltage signal is zero, and the absolute value of the voltage value of the refresh voltage is a preset debugging value.

[0104] In a possible embodiment, the timing control chip 11 is also used to provide timing signals for the first initialization signal to control the N-Reset terminal, the second initialization signal to control the P-Reset terminal, the light-emitting control signal EM terminal, the first gate drive signal Gate_N terminal, and the second gate drive signal Gate_P terminal. Figure 8 Schematic diagram of the timing of the above signals.

[0105] The present application also provides a display 2, see Figure 9 , the display 2 includes the display panel 1 described in any one of the above embodiments.

[0106] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0107] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0108] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel includes: A timing control chip, a plurality of gate drive circuits, a plurality of gating units and a plurality of display partitions; each of the display partitions includes a plurality of pixel rows, and each of the pixel rows includes a plurality of pixel circuits; Each display partition corresponds to a plurality of gating units, each of which is connected to a row of pixels in its corresponding display partition; the gate driving circuit is connected to the gating units in a one-to-one correspondence; The timing control chip is used to generate a local update signal of a corresponding timing and an initialization voltage Vinit signal of a corresponding timing according to the partition refresh status of the frame to be displayed, wherein the partition refresh status indicates whether each display partition is refreshed; different partition refresh statuses correspond to local update signals of different timings and initialization voltage signals of different timings; The gate driving circuit is used to provide a gate driving signal of a data signal switch to the corresponding gating unit; The gating unit is configured to output the gate driving signal to the pixel circuit connected thereto or not output the gate driving signal in response to the control of the local update signal; The pixel circuit is used to refresh the display in response to receiving a gate drive signal and an initialization voltage signal; or to maintain the previous frame display in response to receiving an initialization voltage signal.

2. The display panel according to claim 1, wherein: The number of display partitions is N, each image frame includes N timing stages, and the local update signal of the i-th timing stage is used to control the on and off of each selection unit connected to the i-th display partition, wherein N is an integer greater than 1, i∈N.

3. The display panel according to claim 2, wherein: The pixel circuit includes a first initialization voltage signal input terminal, a second initialization voltage signal input terminal, and a third initialization voltage signal input terminal; the timing control chip includes a first initialization voltage signal output terminal, a second initialization voltage signal output terminal, and a third initialization voltage signal output terminal; The first initialization voltage signal output terminal of the timing control chip is connected to the first initialization voltage signal input terminal of each pixel circuit, the second initialization voltage signal output terminal of the timing control chip is connected to the second initialization voltage signal input terminal of each pixel circuit, and the third initialization voltage signal output terminal of the timing control chip is connected to the third initialization voltage signal input terminal of each pixel circuit.

4. The display panel according to claim 3, wherein: The pixel circuit further includes: A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a capacitor, and a light-emitting device; The control terminal of the first transistor is connected to the first initialization signal control terminal, the first terminal of the first transistor is respectively connected to the second terminal of the second transistor, the second terminal of the third transistor, and the first terminal of the sixth transistor, and the second terminal of the first transistor is connected to the first initialization voltage signal input terminal; The control terminal of the second transistor is connected to the first gate drive signal terminal, and the first terminal of the second transistor is connected to the second terminal of the capacitor and the control terminal of the third transistor respectively; The first end of the third transistor is respectively connected to the first end of the fourth transistor, the second end of the fifth transistor, and the first end of the eighth transistor; The control terminal of the fourth transistor is connected to the second gate drive signal terminal, and the second terminal of the fourth transistor is connected to the data signal input terminal; The control terminal of the fifth transistor is connected to the light emitting control signal terminal, and the first terminal of the fifth transistor is connected to the positive terminal of the power supply; The control terminal of the sixth transistor is connected to the light emitting control signal terminal, and the second terminal of the sixth transistor is connected to the anode of the light emitting device and the first terminal of the seventh transistor respectively; The control terminal of the seventh transistor is connected to the second initialization signal control terminal, and the second terminal of the seventh transistor is connected to the second initialization voltage signal input terminal; The control terminal of the eighth transistor is connected to the second initialization signal control terminal, and the second terminal of the eighth transistor is connected to the third initialization voltage signal input terminal.

5. The display panel according to claim 3 or 4, characterized in that: The timing control chip is specifically used to generate a first initialization voltage signal, a second initialization voltage signal, and a third initialization voltage signal of corresponding timing according to the partition refresh status of the frame to be displayed, and output the first initialization voltage signal through the first initialization voltage signal output end, output the second initialization voltage signal through the second initialization voltage signal output end, and output the third initialization voltage signal through the third initialization voltage signal output end.

6. The display panel according to claim 5, wherein: The first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal in the i-th timing phase are used to provide a refresh voltage or a hold voltage for the i-th display partition; Wherein, when the i-th display partition is a refresh area, the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal in the i-th timing phase are used to provide a refresh voltage for the i-th display partition; When the i-th display partition is a holding area, the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal in the i-th timing phase are used to provide a holding voltage for the i-th display partition; For any one of the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal, a refresh voltage of the initialization voltage signal and a hold voltage thereof have different voltage values.

7. The display panel according to claim 6, wherein: For any one of the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal, an absolute value of a voltage difference between a refresh voltage and a hold voltage of the initialization voltage signal is a preset debugging value.

8. The display panel according to claim 7, wherein: For any one of the first initialization voltage signal, the second initialization voltage signal, and the third initialization voltage signal, the refresh voltage of the initialization voltage signal is the same as the absolute value of the hold voltage; or; The voltage value of the refresh voltage of the initialization voltage signal is zero; or; The voltage value of the holding voltage of the initialization voltage signal is zero.

9. The display panel according to claim 4, wherein: The timing control chip is further configured to provide timing signals for the first initialization signal control terminal, the second initialization signal control terminal, the light emitting control signal terminal, the first gate driving signal terminal, and the second gate driving signal terminal.

10. A display, characterized in that: The display comprises the display panel according to any one of claims 1 to 9.

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