Tiled display apparatus

Abstract

The present disclosure proposes a tiled display apparatus including a plurality of display modules connected to each other to configure a screen, a setting plate configured to output an input data enable signal and image data synchronized therewith to one of the plurality of display modules, and first to Nth (where N is a natural number of 3 or more) timing controllers configured for the plurality of display modules, the first to Nth timing controllers being sequentially connected to each other in a first direction through a first interface line based on a cascade scheme, and configured to receive the output data enable signal and the image data at different timings sequentially delayed, and synchronize a display time of the image data based on the output data enable signal independently generated.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0194727, filed on December 31, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to an expandable tiling display apparatus. Background Technology

[0004] Large-size displays can be used in various fields such as indoor and outdoor digital advertising. To meet the demand for large-size displays, scalable video wall displays have been proposed. In a video wall display, a single screen (display) is configured by connecting multiple display modules, and the desired screen size can be achieved by adjusting the number of display modules connected to each other.

[0005] In a video wall display device, because the display modules receive image data sequentially based on a cascading scheme, the time for receiving image data within each display module is gradually delayed. Due to input discrepancies in image data between display modules, output discrepancies may occur.

[0006] Various output synchronization techniques are known for correcting image output deviations between display modules. However, these techniques may not be suitable for splicing display devices where the interface connection lengths between display modules are non-standardized. Summary of the Invention

[0007] In order to overcome the above-mentioned problems of related technologies, this disclosure can provide a splicing display device that can automatically match the image output time of all display modules, regardless of whether the display modules are connected in a standardized or non-standardized manner.

[0008] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a tiled display apparatus includes a plurality of display modules connected to each other to configure a screen; a setboard configured to output an input data enable signal and image data synchronized therewith to one of the plurality of display modules; and first to Nth (where N is a natural number of 3 or more) timing controllers configured for the plurality of display modules, the first to Nth timing controllers being sequentially connected to each other in a first direction by a first interface line based on a cascade scheme, and configured to receive the input data enable signal and the image data at different timings sequentially delayed and synchronize a display time of the image data based on an independently generated output data enable signal.

[0009] At least one of the first to Nth timing controllers independently calculates an adjacent delay amount between itself and a next stage timing controller by using a current stage input data enable signal received from an adjacent previous stage timing controller via a first interface line and a next stage input data enable signal fed back from an adjacent next stage timing controller via a second interface line different from the first interface line, to generate the output data enable signal. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0011] Figure 1 is a graph schematically illustrating a tiled display apparatus according to an embodiment of the present disclosure;

[0012] Figure 2 is a graph illustrating a connection configuration of a display module;

[0013] Figure 3 and Figure 4 is a graph illustrating a micro light emitting diode (LED) based display panel;

[0014] Figure 5 is a schematic equivalent circuit diagram of a pixel included in a display panel;

[0015] Figure 6 is a graph illustrating an example of an irregular connection structure between display modules;

[0016] Figure 7 is a graph illustrating input data enable signals received by Figure 6 timing controllers of the setboard at different timings sequentially delayed in the first direction;

[0017] Figure 8 is a graph showing a connection configuration of a timing controller for independently calculating an adjacent delay amount between adjacent timing controllers; Figure 6

[0018] Figure 9 is a graph showing an internal connection configuration of some timing controllers shown in Figure 8

[0019] Figure 10 is a waveform graph for describing the operation of some timing controllers shown in Figure 9

[0020] Figure 11 is a graph showing an example in which output data enable signals are simultaneously generated by some timing controllers shown in Figure 8

[0021] Figure 12 is a graph showing an example in which an input image to be implemented by a display module is changed in two adjacent frames;

[0022] Figure 13A is a graph showing an example of an image quality defect caused by asynchronization of image output between display modules as a comparative example of the present embodiment; and

[0023] Figure 13B is a graph showing an example in which image quality is improved by synchronization of image output between display modules in the present embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0025] Advantages and features of the present disclosure and methods of accomplishing the same can be understood more readily by reference to the following examples. The present disclosure may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0026] ​​​​The shapes, sizes, proportions, angles, numbers, etc. disclosed in the accompanying drawings for describing the various embodiments of the present disclosure are merely exemplary for describing the embodiments of the present disclosure, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals refer to the same elements. Throughout the specification, the same elements are denoted by the same reference numerals. As used herein, the terms "include," "have," "comprise" and the like are meant to be interpreted inclusively, not exclusively, unless the context clearly indicates otherwise.

[0027] The elements in the various embodiments of the present disclosure will be construed to include error ranges (tolerances) even if not explicitly stated.

[0028] In describing positional relationships, for example, when the positional relationship between two components is described as "on", "above", "below", and "adjacent (close) to", one or more other components can be disposed between the two components unless "just" or "directly" is used.

[0029] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

[0030] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 is a graph schematically illustrating a tiled display apparatus 100 according to an embodiment of the present disclosure. Figure 2 is a graph illustrating a connection configuration of a display module.

[0032] Referring to Figure 1 and Figure 2 The tiled display apparatus 100 according to an embodiment of the present disclosure can include a set plate SET and a plurality of display modules CB. Each of the plurality of display modules CB can be referred to as a cabinet unit.

[0033] The plurality of display modules CB can be connected to each other through a serial interface circuit to configure (build) a large screen. The total resolution of the large screen can be determined as the sum of the unit resolution of each display module CB. For example, in the case where a screen is configured by 8 display modules having a unit resolution of 960*1080, the total resolution of the screen can be 3840*2160.

[0034] The setting plate SET can transmit configuration for implementing image data of an input image to one of the plurality of display modules CB through a serial interface circuit. The serial interface circuit can be implemented based on a V-by-One (Vx1) scheme capable of high-speed and large-capacity interface connection, but is not limited thereto.

[0035] Each display module CB can include a plurality of display panels PNL, a plurality of panel driving circuits for driving the plurality of display panels PNL, and a timing controller TCON for controlling operation timing of the panel driving circuits.

[0036] Each of the plurality of display panels PNL can be implemented as an electroluminescent display device based on micro light emitting diodes (LEDs), but is not limited thereto, and can be implemented as an electroluminescent display device based on organic or inorganic LEDs.

[0037] The plurality of timing controllers TCON configured for the plurality of display modules CB can be connected to each other through a serial interface circuit such as V-by-One (Vx1). The plurality of timing controllers TCON can be sequentially connected to each other through a cascading scheme, and can receive an input data enable signal and image data synchronized therewith at different timings (timings sequentially delayed). The timing controller TCON can match a display time (i.e., an image output time) of the image data using a new output synchronization technique compared to the related art.

[0038] The output synchronization technique according to the present embodiment can synchronize the image output times of all the display modules CB based on an output data enable signal independently generated by each of the plurality of timing controllers TCON. In the output synchronization technique according to the present embodiment, each timing controller TCON can independently calculate an adjacent delay amount corresponding to an adjacent later-stage timing controller to generate a synchronized (or post-synchronized) output data enable signal. Accordingly, the image output times of all the display modules CB can be automatically matched regardless of whether a normal (regular) splicing connection structure or a non-normal (irregular) splicing connection structure is employed between the plurality of display modules CB.

[0039] The timing controller TCON of each display module CB can be mounted on a control printed circuit board CPCB, and can be connected in parallel (in parallel) to the panel driving circuit of the corresponding display module CB through a branch cable CBL.

[0040] The panel driving circuit can be independently included in each of the plurality of display panels PNL configuring the same display module CB. The panel driving circuit can include a source printed circuit board SPCB connected to the timing controller TCON through a cable CBL, a memory circuit MEM mounted on the source printed circuit board SPCB, a conductive film COF electrically connecting the source printed circuit board SPCB to the display panel PNL, a data driver SIC bonded to the conductive film COF, and a gate driver and a power supply circuit electrically connected to the source printed circuit board SPCB.

[0041] The memory circuit MEM can be a non-volatile memory storing panel characteristic information, and can be a flash memory and / or an electrically erasable programmable read-only memory (EEPROM). The panel characteristic information can include a correction value for gamma setting, a first compensation value for compensating for a driving characteristic deviation / color deviation between pixels, a second compensation value for compensating for a boundary deviation between adjacent display panels PNL, various image quality and driving control data. In the panel characteristic information, a large amount of data can be stored in the flash memory, and a small amount of data can be stored in the EEPROM.

[0042] The timing controller TCON can operate the panel driving circuit based on a control command signal received through a control interface circuit such as a serial peripheral interface (SPI) to perform a target operation corresponding to the control command signal, and thus, can generate a control response signal including an execution result of the target operation. The target operation can include a reset, a mute (dark change), an average picture level (APL) range change, a gamma change, an image quality compensation value update, and a firmware update. The target operation can also include an operation of writing and storing control command data in a specific memory and an operation of reading control execution data from the specific memory.

[0043] Figure 3 and Figure 4 is a diagram showing a micro-LED-based display panel. Figure 5 is a schematic equivalent circuit diagram of a pixel included in a display panel.

[0044] Referring to Figure 3 and Figure 4 A pixel array for reproducing an input image can be provided in each display panel PNL. A plurality of pixels can be arranged in the pixel array, and a signal line for driving the pixels can be arranged in the pixel array. The signal line can include a plurality of data lines DL for supplying a data voltage Vdata to the pixels, a plurality of gate lines GL for supplying a gate signal GSIG to the pixels, and a plurality of power supply lines for supplying a source voltage to the pixels.

[0045] Each of the plurality of pixels may include a micro LED chip (μLED chip) as a light-emitting device (EL). The plurality of micro LED chips (μLED chips) may include a red chip (μLED chip_R), a green chip (μLED chip_G), and a blue chip (μLED chip_B) disposed on a thin-film transistor (TFT) backplane. The red (R) pixel may include a red chip (μLED chip_R) as a light-emitting device (EL), the green (G) pixel may include a green chip (μLED chip_G) as a light-emitting device (EL), and the blue (B) pixel may include a blue chip (μLED chip_B) as a light-emitting device (EL).

[0046] Micro LED chips (μLED chips) can be transferred from R / G / B donors and thus can be mounted on a TFT backplane. Red chips (μLED chip_R) can be transferred from the R donor, green chips (μLED chip_G) from the G donor, and blue chips (μLED chip_B) from the B donor. Transfer techniques can utilize electrostatic forces, lasers, velocity-dependent viscous forces, and load-dependent viscous forces. Transfer techniques are not limited to these and electrostatic force-based self-assembly can also be used.

[0047] TFT backplanes can be implemented as active matrix structures for efficient (or high-efficiency) driving. In a TFT backplane, pixels can be defined by data lines (DL), gate lines (GL), and power lines.

[0048] Multiple pixels can be configured (constructed) into a single unit pixel. For example, adjacent R, G, and B pixels can be configured into a single unit pixel along the extension direction of the gate line GL or the data line DL.

[0049] like Figure 5 As shown, the pixel PXL may include a light-emitting device EL, a driving TFT DT, and a node circuit NCON.

[0050] The node circuit NCON can be connected to the gate line GL and the data line DL. A data voltage Vdata can be provided to the node circuit NCON via the data line DL, and a gate signal GSIG can be provided to the node circuit NCON via the gate line GL. The node circuit NCON can apply the data voltage Vdata and the gate signal GSIG synchronously to the gate electrode of the driving TFT DT, and therefore, the gate-source voltage of the driving TFT DT can be set based on the conditions used to generate the drive current. The node circuit NCON may include internal compensation circuitry that senses and compensates for the threshold voltage and / or electron mobility of the driving TFT DT.

[0051] The drive TFT DT can be a drive element that generates a drive current based on a gate-source voltage thereof. A gate electrode of the drive TFT DT can be connected to the node circuit NCON, a first electrode (a drain electrode) thereof can be connected to the high-level pixel power supply VDD, and a second electrode (a source electrode) thereof can be connected to the light emitting device EL.

[0052] The light emitting device EL can be a light emitting device that emits light having an intensity corresponding to the drive current input to the drive TFT DT. The light emitting device EL can be implemented in a micro-LED including an inorganic light emitting layer. A first electrode of the light emitting device EL can be connected to the drive TFT DT, and a second electrode thereof can be connected to the low-level pixel power supply VSS.

[0053] The connection configuration and operation of one pixel PXL can be only one embodiment, and the spirit of the disclosure is not limited thereto. For example, each of the drive TFT DT and the node circuit NCON can be implemented based on a PMOS transistor, or can be implemented based on an NMOS transistor. In addition, the gate line GL connected to the node circuit NCON can be provided as a plurality of gate lines.

[0054] Figure 6 is a graph illustrating an example of a non-normal connection structure between display modules. Figure 7 is a graph illustrating a connection structure between display modules. Figure 6 is a graph illustrating input data enable signals sequentially delayed in a first direction received by a timing controller of

[0055] Referring to Figure 6 and Figure 7 , the first timing controller TCON#1, the second timing controller TCON#2, the third timing controller TCON#3, and the fourth timing controller TCON#4 can be sequentially connected to each other, and a setting plate SET can be connected to the first timing controller TCON#1. The connection type between the setting plate SET and the display modules can be implemented in different ways based on the type of the setting plate and / or the manufacturing method of the tiling system, and thus the number and positions of the timing controllers TCON#1 to TCON#4 can vary. The timing controllers TCON#1 to TCON#4 can be connected to each other through a first interface line such as Vx1, and in this case, a vertical connection length INT2 between the specific timing controllers TCON#2 and TCON#3 can be longer than a horizontal connection length INT1 between the specific timing controllers TCON#1 and TCON#2 and the specific timing controllers TCON#3 and TCON#4.

[0056] The data enable signal DE can be sequentially delayed in synchronization with the image data and can be transmitted to the first to fourth timing controllers TCON#1 to TCON#4. The set board SET can transmit the image data in synchronization with a rising edge (or a front edge) RE of a set output data enable signal (SET output DE) to the first timing controller TCON#1, but is not limited thereto. The first to fourth timing controllers TCON#1 to TCON#4 can receive the image data in synchronization with a rising edge RE of the first to fourth input data enable signals (#1 to #4 input DE) that are sequentially delayed and input thereto, but is not limited thereto. The synchronization scheme between the data enable signal DE and the image data can be modified in various ways.

[0057] Each of the first to fourth timing controllers TCON#1 to TCON#4 can decode the input data enable signal and the image data received through the first interface line through a clock and data recovery (CDR) process, and can perform a compensation process on the decoded image data by using an image quality compensation algorithm. Each of the first to fourth timing controllers TCON#1 to TCON#4 can encode the decoded image data and the input data enable signal DE, and can transmit the encoded image data and the input data enable signal DE to a later-stage timing controller through the first interface line. The image data and the input data enable signal DE can be delayed in the CDR process and an input / output process.

[0058] Further, when the first interface line between adjacent timing controllers is greater than a rated allowable value, interface connection efficiency can be reduced, and thus, a repeater REP can be added between specific timing controllers (for example, the second timing controller TCON#2 and the third timing controller TCON#3) in which the connection length INT2 is longer. The repeater REP can perform a CDR operation to re-transmit the image data, and thus, the delay of the image data and the input data enable signal DE between the second timing controller TCON#2 and the third timing controller TCON#3 can occur with a relatively high probability.

[0059] For example, as Figure 7 shown, when the adjacent delay amount between the first timing controller TCON#1 and the second timing controller TCON#2 is "A" and the adjacent delay amount between the third timing controller TCON#3 and the fourth timing controller TCON#4 is "C", the adjacent delay amount between the second timing controller TCON#2 and the third timing controller TCON#3 including an additional delay caused by the repeater REP can be "B". "B" can be greater than each of "A" and "C". "A" and "C" can be the same as or different from each other.

[0060] Since the first to fourth timing controllers TCON#1 to TCON#4 receive image data and input data enable signals DE under (or with) different timings, a synchronized output data enable signal for enabling image data to be applied to all display panels included in a display module at the same time can be required.

[0061] To generate the synchronized output data enable signal, a register scheme, a feedback line technique, and a synchronization line technique can be considered.

[0062] According to the register scheme, fixed delay values for each timing controller can be pre-stored in a register based on a transmission order, and each timing controller can generate an output data enable signal based on the fixed delay values. According to the feedback line technique, a first timing controller and a last timing controller based on a data interface connection order can be connected to each other through a feedback line, and the first timing controller can equally distribute a total delay obtained through the feedback line to each timing controller to adjust a generation time of an output data enable signal. In the synchronization line technique, a setup board can adjust a generation time of an output data enable signal with respect to the last timing controller by using a synchronization line commonly connected to all timing controllers.

[0063] The synchronization line technique should be redesigned every time the number of connections of the tiled timing controllers changes, and for this reason, the scalability of the synchronization line technique can be rather low. Since the number of connections of the timing controllers is applicable only when the delay consumed by each timing controller is pre-known, the register scheme cannot be applied to a non-normal tiled connection structure that is scalable and modifiable based on various (or different) user requirements. The register scheme can be applied only to a normal tiled connection structure in which the number of connections of the tiled timing controllers and the delay consumed by each timing controller are equal.

[0064] Similarly, the feedback line technique cannot be applied to a non-normal tiled connection structure in which the delay consumed in at least some of the timing controllers is different from the delay consumed in other timing controllers. In the non-normal tiled connection structure, the amount of input and output delay of each tiled timing controller can be different, and as shown in FIG. 2B, the length of a data interface connection between some of the timing controllers can be relatively long. Thus, when the feedback line technique of equally distributing a total delay based on the number of connections of the timing controllers is applied to the non-normal tiled connection structure, it can be difficult to correct image output deviation between the timing controllers. Figure 6

[0065] ​Hereinafter, the output synchronization technique according to the present embodiment can be a technique in which each timing controller independently calculates a delay deviation between the corresponding timing controller and the last timing controller by performing a delay feedback operation between adjacent timing controllers and synchronizes an output data enable signal based on the same.

[0066] In the output synchronization technique according to the present embodiment, each timing controller can automatically synchronize the image output times of all display modules regardless of a regular / irregular splicing connection structure, and thus, it is possible to improve the image quality of the splicing display apparatus.

[0067] Since each timing controller automatically synchronizes the image output times of all display modules, the output synchronization technique according to the present embodiment can be applied to an irregular splicing connection structure that is scalable and modifiable based on various user requirements, and thus, it is possible to improve the convenience of users.

[0068] Figure 8 is a diagram illustrating a connection configuration of timing controllers for independently calculating an adjacent delay amount between adjacent timing controllers. Figure 6 is a diagram illustrating a connection configuration of timing controllers for independently calculating an adjacent delay amount between adjacent timing controllers. Figure 9 is a diagram illustrating an internal connection configuration of some timing controllers illustrated in Figure 8 Figure 10 is a diagram illustrating an internal connection configuration of some timing controllers illustrated in Figure 9 Figure 11 is a diagram illustrating an internal connection configuration of some timing controllers illustrated in Figure 8

[0069] Referring to Figures 8 to 11 , the first to fourth timing controllers TCON#1 to TCON#4 can be sequentially connected to each other in a first direction through a first interface line Vx1 based on a cascading scheme, and can receive an input data enable signal (#1~#4 input DE) and image data at different timings sequentially delayed. Here, the first direction can be a direction of data interfacing and can not indicate one specific direction. Based on the first to fourth timing controllers TCON#1 to TCON#4 for implementing a splicing connection structure, the first direction can include one or more directions among four directions (for example, up, down, left, and right directions).

[0070] ​​​Each of the second to fourth timing controllers TCON#2 to TCON#4 can receive an input data enable signal (#2~#4 input DE) and image data from the preceding timing controller TCON#1 to TCON#3 adjacent thereto in a second direction through the first interface line Vx1. The second direction can be a direction of transmitting feedback interfacing and can be opposite to the first direction. Based on the first to fourth timing controllers TCON#1 to TCON#4 for implementing the stitching connection structure, the second direction can include one or more of four directions (e.g., up, down, left, and right directions).

[0071] Each of the first to third timing controllers TCON#1 to TCON#3 can receive a succeeding input data enable signal from the succeeding timing controller TCON#2 to TCON#4 adjacent thereto in a first direction through feedback, and can independently calculate an adjacent delay amount corresponding to the succeeding timing controller TCON#2 to TCON#4.

[0072] Each of the first to third timing controllers TCON#1 to TCON#3 can receive a succeeding input data enable signal (#2~#4 input DE) from the succeeding timing controller TCON#2 to TCON#4 adjacent thereto in the first direction through feedback through a second interface line TTL different from the first interface line Vx1.

[0073] The first timing controller TCON#1 can be illustrated as a first timing controller for data interface connection, and the fourth timing controller TCON#4 can be illustrated as a last timing controller for data interface connection.

[0074] Since the first timing controller TCON#1 is the first timing controller for data interface connection, only the delay input pins OD_I and PD_I can be used for delay feedback operation. Since the fourth timing controller TCON#4 is the last timing controller for data interface connection, only the delay output pins OD_O and PD_O can be used for delay feedback operation. In the first to fourth timing controllers TCON#1 to TCON#4, “DC_I” and “DC_O” can be I / O correction input / output pins for correcting input and output delay amounts (I / O delay) other than delay feedback operation.

[0075] Each of the second and third timing controllers TCON#2 and TCON#3 can use all of the delay input pins OD_I and PD_I and the delay output pins OD_O and PD_O for delay feedback operation.

[0076] The delay input pins OD_I and PD_I can include the adjacent delay input pin PD_I and the total delay input pin OD_I, and the delay output pins OD_O and PD_O can include the adjacent delay output pin PD_O and the total delay output pin OD_O.

[0077] The adjacent delay output pin PD_O and the adjacent delay input pin PD_I can be calculated to calculate the adjacent delay amount between the adjacent timing controllers. The adjacent delay output pin PD_O and the adjacent delay input pin PD_I can be connected to each other between the adjacent timing controllers through the second interface line TTL.

[0078] The total delay input pin OD_I can be used to receive a rear stage total delay amount generated by a rear stage timing controller from the rear stage timing controller through feedback. The rear stage total delay amount can represent a total delay amount between the rear stage timing controller and the last timing controller TCON#4. The total delay output pin OD_O can be used to feed back a current stage total delay amount generated by the current stage timing controller to a front stage timing controller. The current stage total delay amount can be a result obtained by adding the current stage adjacent delay amount and the rear stage total delay amount, and can represent a total delay amount between the current stage timing controller and the last timing controller TCON#4.

[0079] In the present embodiment, the first to third interface lines Vx1, TTL, and SPI can be included in the same transmission cable ICL and can be connected between the adjacent timing controllers, but the present embodiment is not limited thereto. As shown in FIG. 1, only the first interface line Vx1 and the second interface line TTL can be included in the same transmission cable ICL, and the third interface line SPI can be included in a separate (separated) transmission cable. Figure 8

[0080] In order to describe, for example, the second timing controller TCON#2, the configuration and operation of the timing controller for implementing the data interface connection, the feedback interface connection, and the output synchronization will be described below.

[0081] The second timing controller TCON#2 can receive the input data enable signal #2 input DE and the image data synchronized therewith from the first timing controller TCON#1 adjacent thereto in the second direction through the first interface line Vx1, and can receive the rear stage input data enable signal #3 input DE fed back (back) from the third timing controller TCON#3 through the second interface line TTL. The rear stage input data enable signal #3 input DE can be an input data enable signal received from the third timing controller TCON#3.

[0082] ​The second timing controller TCON#2 can include an adjacent delay input pin #2 PD_I, a Vx1 receiver #2 RX, a Vx1 transmitter #2 TX, and an adjacent delay calculator #2 DCHK.

[0083] The adjacent delay input pin #2 PD_I can be configured to receive a next stage input data enable signal #3 input DE received from the third timing controller TCON#3 and fed back from an adjacent delay output pin #3 PD_O of the third timing controller TCON#3. The adjacent delay input pin #2 PD_I of the second timing controller TCON#2 and the adjacent delay output pin #3 PD_O of the third timing controller TCON#3 can be connected to each other through a second interface line TTL. A repeater REP connected between the second timing controller TCON#2 and the third timing controller TCON#3 can be omitted.

[0084] The Vx1 receiver #2 RX can receive the input data enable signal #2 input DE and image data synchronized therewith from the first timing controller TCON#1 through a first interface line Vx1. The input data enable signal #2 input DE can be a current stage input data enable signal that is less delayed than the next stage data enable signal #3 input DE. The Vx1 receiver #2 RX can include a CDR circuit and can perform recovery and image quality compensation processing on the input data enable signal #2 input DE and the image data synchronized therewith.

[0085] The Vx1 transmitter #2 TX can encode the input data enable signal #2 input DE and the image data synchronized therewith and can transmit the encoded signals to the third timing controller TCON#3 through the first interface line Vx1.

[0086] The adjacent delay calculator #2 DCHK can be electrically connected to the adjacent delay input pin PD_I. The adjacent delay calculator #2 DCHK can receive the next stage data enable signal #3 input DE and the current stage input data enable signal #2 input DE to calculate and output an amount of adjacent delay between the second timing controller TCON#2 and the third timing controller TCON#3.

[0087] The input and output delay (I / O delay between #3 and #2) can be more reflected in the next stage data enable signal #3 input DE. The input and output delay can be accumulated with repetition of the feedback process, and can be transmitted to the previous stage timing controller, and thus, accuracy of the delay calculation can be reduced.

[0088] To offset the input and output delay (I / O delay between #3 and #2), the second timing controller TCON #2 can also use an I / O delay correction output pin #2DC_O and an I / O delay correction input pin #2DC_I. The I / O delay correction output pin #2DC_O and the I / O delay correction input pin #2DC_I can be configured to further delay the current stage input data enable signal #2 input DE more to reflect the input and output delay amount (I / O delay between #3 and #2) in the subsequent stage data enable signal #3 input DE. For accurate delay matching, the I / O delay correction output pin #2DC_O of the second timing controller TCON #2 can be designed to have the same characteristics as those of the adjacent delay output pin #3PD_O of the third timing controller TCON #3. Also, in the second timing controller TCON #2, the I / O delay correction input pin #2DC_I can be designed to have the same characteristics as those of the adjacent delay input pin #2PD_I.

[0089] The I / O delay correction output pin #2DC_O can be connected to the output end of the Vx1 receiver #2RX. The I / O delay correction output pin #2DC_O and the I / O delay correction input pin #2DC_I can be electrically connected to each other by a wire CW outside the second timing controller TCON #2. Accordingly, the current stage input data enable signal #2 input DE can pass through the I / O delay correction output pin #2DC_O, the wire CW, and the I / O delay correction input pin #2DC_I, and thus, can be input to the adjacent delay calculator #2DCHK in a state in which the input and output delay amount (I / O delay in #2) is reflected therein.

[0090] The wire CW can be patterned on a control printed circuit board (see Figure 2 CPCB) on which the second timing controller TCON #2 is mounted. Impedance matching can be performed between the wire CW and the second interface line TTL so that the input and output delay amount (I / O delay in #2) of the second timing controller TCON #2 is the same as the input and output delay amount (I / O delay between #3 and #2) in which the input and output delay amount (I / O delay in #3) of the subsequent stage third timing controller TCON #3 is reflected.

[0091] The adjacent delay calculator #2DCHK can calculate the difference between the input of the I / O delay correction input pin #2DC_I and the input of the adjacent delay input pin #2PD_I, and thus, can calculate the adjacent delay amount between the second timing controller TCON #2 and the third timing controller TCON #3.

[0092] The second timing controller TCON#2 can also use the total delay input pin #2OD_I, the total delay calculator #2DCON, the total delay output pin #2OD_O, and the output controller #2GEN.

[0093] The total delay input pin #2OD_I can be configured to receive the first total delay amount (#3) generated by the third timing controller TCON#3 and fed back from the third timing controller TCON#3 via the third interface line SPI. The first total delay amount (#3) can be obtained by summing the adjacent delay amounts from the third timing controller TCON#3 up to the fourth timing controller TCON#4. The fourth timing controller TCON#4 can be the last timing controller, and therefore, the first total delay amount (#3) can be the adjacent delay amount "C" between the third timing controller TCON#3 and the fourth timing controller TCON#4 (see [link to relevant documentation]). Figure 11 ).exist Figure 11 In this context, "XX" can be the internal process processing time of each timing controller and can be equal across all timing controllers.

[0094] Total Delay Calculator #2DCON can calculate the adjacent delay "B" between the second timing controller TCON#2 and the third timing controller TCON#3 (see...). Figure 11 Add to the first total delay amount "C" (see...) Figure 11 ), to calculate the second total delay (#2). Second total delay (#2) ( Figure 11 The OD_(B+C) can be obtained by accumulating the adjacent delays from the second timing controller TCON#2 to the fourth timing controller TCON#4.

[0095] The output controller #2GEN can delay the current stage input data enable signal #2 input DE based on the second total delay (#2), to generate the output data enable signal #2 output DE. The output data enable signal #2 output DE can be configured to control the timing (moment) of outputting image data to the corresponding display panel.

[0096] Furthermore, the second total delay (#2) can be fed back to the first timing controller TCON#1 via the total delay output pin #2OD_O. Then, the first timing controller TCON#1 can calculate the adjacent delay "A" between the first timing controller TCON#1 and the second timing controller TCON#2 based on the same scheme (see...). Figure 11 ), and can also include adjacent delay amounts "A" (see Figure 11 Add to the second total latency (#2) to calculate the final total latency (#1).Figure 11 OD_(A+B+C)).

[0097] Furthermore, the last timing controller TCON#4 can generate an output data enable signal #4 (output DE) after being delayed by an internal process processing time XX from the input data enable signal #4 (input DE). Each of the first timing controllers TCON#1 to the third timing controller TCON#3 can independently generate output data enable signals (#1, #2, #3 output DE) based on the input data enable signal #4 (input DE), wherein the final delay of the last timing controller TCON#4 is reflected in the input data enable signal #4 (input DE).

[0098] Since the output data enable signals (#1, #2, #3 output DE) are generated based on the final delay of the fourth timing controller TCON#4, the first timing controller TCON#1 to the fourth timing controller TCON#4 can be automatically synchronized between them.

[0099] Figure 12 This is a graphic illustrating an example where the input image, implemented by the display module, changes between two adjacent frames. Figure 13A This is a graphic illustrating an example of image quality defects caused by asynchrony in image output between display modules, serving as a comparative example of this embodiment. Figure 13B This is a graphic illustrating an example of improving image quality through synchronization of image output between display modules in this embodiment.

[0100] When image data is in, for example Figure 12 The case shown illustrates the mismatch between the output timing and the rapid changes in frames N and N+1 (see [reference]). Figure 13A In contrast, the output data synchronization enable signal is matched between display modules that sequentially receive image data based on a cascaded scheme during the image data output time (see [reference]). Figure 13B Under these conditions, image quality defects caused by output asynchrony can be greatly reduced.

[0101] The splicing display device according to embodiments of the present disclosure can be described as follows.

[0102] A tiled display apparatus according to an embodiment of the disclosure can include a plurality of display modules connected to each other to configure a screen, a setting plate configured to output an input data enable signal and image data synchronized therewith to one of the plurality of display modules, and first through Nth (where N is a natural number of 3 or more) timing controllers configured for the plurality of display modules, the first through Nth timing controllers being sequentially connected to each other in a first direction by a first interface line based on a cascade scheme, and being configured to receive the input data enable signal and the image data at different timings sequentially delayed, and to synchronize a display time of the image data based on an independently generated output data enable signal, wherein at least one of the first through Nth timing controllers independently calculates an adjacent delay amount between itself and a rear stage timing controller to generate the output data enable signal by using a current stage input data enable signal received from an adjacent front stage timing controller via the first interface line and a rear stage input data enable signal fed back from the adjacent rear stage timing controller via a second interface line different from the first interface line.

[0103] According to an embodiment of the disclosure, an Mth (where M is a natural number greater than 1 and less than N) timing controller can include an adjacent delay input pin configured to receive a rear stage input data enable signal received at an M+1th timing controller through the first interface line and fed back from an adjacent delay output pin of the M+1th timing controller through the second interface line, a receiver configured to receive a current stage input data enable signal that is less delayed than the rear stage input data enable signal through the first interface line, and an adjacent delay calculator configured to output an adjacent delay amount between the Mth timing controller and the M+1th timing controller based on the current stage input data enable signal and the rear stage input data enable signal.

[0104] According to an embodiment of the disclosure, the adjacent delay input pin of the Mth timing controller and the adjacent delay output pin of the M+1th timing controller can be connected to each other through the second interface line.

[0105] According to an embodiment of the disclosure, the Mth timing controller can further include an I / O delay correction output pin and an I / O delay correction input pin for further delaying the current stage input data enable signal by an input and output delay amount in which the rear stage input data enable signal is further reflected.

[0106] According to an embodiment of the disclosure, the I / O delay correction output pin and the I / O delay correction input pin can be connected to each other through a wire outside the Mth timing controller.

[0107] According to an embodiment of the disclosure, the current stage input data enable signal can pass through the I / O delay correction output pin, the wire, and the I / O delay correction input pin and be input to the adjacent delay calculator.

[0108] According to an embodiment of the disclosure, the wire can be patterned on a control printed circuit board on which the Mth timing controller is mounted.

[0109] According to an embodiment of the disclosure, impedance matching can be performed between the wire and the second interface line so that the input and output delay amount of the Mth timing controller is the same as the input and output delay amount in which the input and output delay amount of the M+1th timing controller of a next stage is reflected.

[0110] According to an embodiment of the disclosure, the Mth timing controller can further include a total delay input pin configured to receive a first total delay amount generated by the M+1th timing controller and fed back from the M+1th timing controller through a third interface line different from the first interface line, and the first total delay amount can be obtained by accumulating adjacent delay amounts from the M+1th timing controller to an Nth timing controller.

[0111] According to an embodiment of the disclosure, the Mth timing controller can further include a total delay calculator configured to add an adjacent delay amount between the Mth timing controller and the M+1th timing controller to the first total delay amount to generate a second total delay amount, and the second total delay amount can be obtained by accumulating adjacent delay amounts from the Mth timing controller to the Nth timing controller.

[0112] According to an embodiment of the disclosure, the Mth timing controller can further include an output controller configured to delay the current stage input data enable signal based on the second total delay amount to generate an output data enable signal, and the output data enable signal is configured to control a time at which the image data is output to a display panel and is generated simultaneously by the first to Nth timing controllers.

[0113] According to an embodiment of the disclosure, the Mth timing controller can further include an adjacent delay output pin configured to feed back the current stage input data enable signal to an adjacent delay input pin of an M-1th timing controller.

[0114] According to an embodiment of the disclosure, the Mth timing controller can further include a total delay output pin configured to feed back the second total delay amount generated by the total delay calculator to a total delay input pin of an M-1th timing controller.

[0115] According to an embodiment of the present disclosure, each of the first to Nth timing controllers can be connected to a plurality of display panels belonging to one of the plurality of display modules.

[0116] According to an embodiment of the present disclosure, the timing controller of each display module can be mounted on a control printed circuit board and connected in parallel to a panel driving circuit of the display module through a branch cable.

[0117] According to an embodiment of the present disclosure, the first, second, and third interface lines can be included in the same transmission cable and connected between adjacent timing controllers.

[0118] According to an embodiment of the present disclosure, the first and second interface lines can be included in the same transmission cable and the third interface line can be included in a separate transmission cable.

[0119] The present embodiment can achieve the following effects.

[0120] According to the present embodiment, each timing controller can automatically match the image output times of all display modules, and thus, image defects caused by asynchronization of image output can be effectively reduced.

[0121] Since each timing controller automatically matches the image output times of all display modules, the present embodiment can be applied to a non-standardized splicing connection structure that is scalable and modifiable based on various user needs, and thus, the convenience of users can be greatly improved.

[0122] Effects of the present disclosure are not limited to the above examples, and other various effects can be included in the present specification.

[0123] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A tiled display apparatus comprising: a plurality of display modules connected to each other to configure a screen; a setting board configured to output an input data enable signal and image data synchronized therewith to one of the plurality of display modules; and first through Nth timing controllers configured for the plurality of display modules, the first through Nth timing controllers being sequentially connected to each other in a first direction by a first interface line based on a cascading scheme, and configured to receive the input data enable signal and the image data at different timings sequentially delayed, and to synchronize a display time of the image data based on an independently generated output data enable signal, wherein at least one of the first through Nth timing controllers independently calculates an adjacent delay amount between itself and a next stage timing controller to generate the output data enable signal by using a current stage input data enable signal received from the adjacent previous stage timing controller via the first interface line and a next stage input data enable signal fed back from the adjacent next stage timing controller via a second interface line different from the first interface line. an Mth timing controller comprises:

2. The tiled display apparatus of claim 1, wherein, an adjacent delay input pin configured to receive a next stage input data enable signal received at an M+1th timing controller through the first interface line and fed back from an adjacent delay output pin of the M+1th timing controller through the second interface line; a receiver configured to receive a current stage input data enable signal delayed less than the next stage input data enable signal through the first interface line; and an adjacent delay calculator configured to output an adjacent delay amount between the Mth timing controller and the M+1th timing controller based on the current stage input data enable signal and the next stage input data enable signal, wherein M is a natural number greater than 1 and less than N. the adjacent delay input pin of the Mth timing controller and the adjacent delay output pin of the M+1th timing controller are connected to each other through the second interface line.

3. The tiled display apparatus of claim 2, wherein, the Mth timing controller further comprises an I / O delay correction output pin and an I / O delay correction input pin for delaying the current stage input data enable signal more with input and output delay amounts of the next stage input data enable signal further reflected therein.

4. The tiled display apparatus of claim 3, wherein, the I / O delay correction output pin and the I / O delay correction input pin are connected to each other through a wire outside the Mth timing controller.

5. The tiled display apparatus of claim 4, wherein, the current stage input data enable signal passes through the I / O delay correction output pin, the wire, and the I / O delay correction input pin and is input to the adjacent delay calculator.

6. The tiled display apparatus of claim 5, wherein, the wire is patterned on a control printed circuit board on which the Mth timing controller is mounted.

7. The tiled display apparatus of claim 5, wherein, impedance matching is made between the wire and the second interface line so that input and output delay amounts of the Mth timing controller are the same as input and output delay amounts in which input and output delay amounts of the M+1th timing controller of a next stage are reflected.

8. The tiled display apparatus of claim 5, wherein, ​ 9. The tiled display apparatus of claim 2, wherein, The Mth timing controller further includes a total delay input pin configured to receive a first total delay amount generated by and fed back from the M+1th timing controller through a third interface line different from the first interface line, and The first total delay amount is obtained by accumulating adjacent delay amounts from the M+1th timing controller to an Nth timing controller.

10. The tiled display apparatus of claim 9, wherein, The Mth timing controller further includes a total delay calculator configured to add an adjacent delay amount between the Mth timing controller and the M+1th timing controller to the first total delay amount to generate a second total delay amount, and The second total delay amount is obtained by accumulating adjacent delay amounts from the Mth timing controller to the Nth timing controller.

11. The tiled display apparatus of claim 10, wherein, The Mth timing controller further includes an output controller configured to delay the current stage input data enable signal based on the second total delay amount to generate an output data enable signal, and The output data enable signal is configured to control a time at which the image data is output to a display panel, and is generated simultaneously by the first to Nth timing controllers.

12. The tiled display apparatus of claim 2, wherein, The Mth timing controller further includes an adjacent delay output pin configured to feed back the current stage input data enable signal to an adjacent delay input pin of an M-1th timing controller.

13. The tiled display apparatus of claim 10, wherein, The Mth timing controller further includes a total delay output pin configured to feed back the second total delay amount generated by the total delay calculator to a total delay input pin of an M-1th timing controller.

14. The tiled display apparatus of claim 1, wherein, Each of the first to Nth timing controllers is connected to a plurality of display panels belonging to one of the plurality of display modules.

15. The tiled display apparatus of claim 1, wherein, The timing controller of each display module is mounted on a control printed circuit board and connected in parallel to a panel driving circuit of the display module through a branch cable.

16. The tiled display apparatus of claim 9, wherein, The first interface line, the second interface line, and the third interface line are included in the same transmission cable and connected between adjacent timing controllers.

17. The tiled display apparatus of claim 9, wherein, The first interface line and the second interface line are included in the same transmission cable, and the third interface line is included in a separate transmission cable.

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