Memory devices and their operation methods
By optimizing the voltage switching sequence of signal lines, serial select lines, and word lines in the memory device, the input/output bottleneck and inefficiency of multiply-accumulate-add operations in the AI architecture are solved, resulting in faster MAC operations and data processing speeds.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MACRONIX INTERNATIONAL CO LTD
- Filing Date
- 2022-01-26
- Publication Date
- 2026-05-26
Smart Images
Figure CN116417029B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a memory device with in-memory-computing (IMC) and a method of operating the same. Background Technology
[0002] Artificial intelligence (AI) has become a highly effective solution in many fields. The key operation of AI lies in multiplying and accumulating (MAC) a large amount of input data (such as input feature maps) with weight values.
[0003] However, current AI architectures are prone to I / O bottlenecks and inefficient MAC operation flows.
[0004] To achieve high accuracy, MAC operations with multi-bit inputs and multi-bit weight values can be performed. However, the input / output bottleneck becomes more severe, and efficiency will be lower.
[0005] In-Memory Computing (IMC) can be used to accelerate MAC operations because IMC reduces the number of complex arithmetic logic units (ALUs) required in a central processing architecture and provides high parallelism for in-memory MAC operations.
[0006] When performing IMC, speeding up the background setup time for multiplication operations can improve IMC performance. Summary of the Invention
[0007] According to an embodiment of the present invention, an operation method for a memory device is provided. The memory device includes a plurality of memory cells. The operation method includes: in a first stage, selecting a whole signal line to pull the whole signal line high from a first reference voltage to a second reference voltage; selecting a first select line to pull the first select line high from the first reference voltage to a third reference voltage; not selecting a second select line to maintain it at the first reference voltage; selecting a first word line to pull the first word line high from the first reference voltage to a fourth reference voltage; and not selecting a second select line. The second word line is pulled high from the first reference voltage to a fifth reference voltage; sensing occurs during a second stage; during a third stage, the entire signal line is maintained at the second reference voltage, the first string of select lines is not selected and the first string of select lines is pulled low from the third reference voltage to the first reference voltage, the second string of select lines is selected and the second string of select lines is pulled high from the first reference voltage to the third reference voltage, the selected first word line is maintained at the fourth reference voltage, and the unselected second word line is maintained at the fifth reference voltage; and sensing occurs during a fourth stage.
[0008] According to another embodiment of the present invention, an operation method for a memory device is provided. The memory device includes a plurality of memory cells. The operation method includes, in a first stage, selecting an integral signal line to pull the integral signal line high from a first reference voltage to a second reference voltage, selecting a first select line to pull the first select line high from the first reference voltage to a third reference voltage, not selecting a second select line to maintain it at the first reference voltage, selecting a first word line to pull the first word line high from the first reference voltage to a fourth reference voltage, and not selecting... A second word line is pulled high from the first reference voltage to a fifth reference voltage; sensing occurs during a second stage; during a third stage, the overall signal line is maintained at the second reference voltage, the selected first string of select lines is maintained at the third reference voltage, the unselected second string of select lines is maintained at the first reference voltage, the unselected first word line is pulled high from the fourth reference voltage to the fifth reference voltage, and the selected second word line is pulled low from the fifth reference voltage to the fourth reference voltage; sensing occurs during a fourth stage.
[0009] According to another embodiment of the present invention, a memory device is provided, comprising: a plurality of memory cells; a plurality of integral signal lines; a plurality of bit lines; a plurality of string select lines; a plurality of word lines coupled to the memory cells, the memory cells being further coupled to the bit lines; a plurality of first switches coupled to the string select lines and the bit lines; and a plurality of second switches coupled to the integral signal lines and the bit lines; wherein, in a first stage, a first integral signal line of the integral signal lines is selected to pull the first integral signal line high from a first reference voltage to a second reference voltage, a first string select line of the string select lines is selected to pull the first string select line high from the first reference voltage to a third reference voltage, and a second string select line of the string select lines is not selected to maintain the first string select line at the second reference voltage. A first reference voltage is selected, a first word line of these word lines is selected to pull the first word line high from the first reference voltage to a fourth reference voltage, and a second word line of these word lines is not selected to pull the second word line high from the first reference voltage to a fifth reference voltage; sensing is performed in a second stage; in a third stage, the first overall signal line is maintained at the second reference voltage, the first string of select lines is not selected and the first string of select lines is pulled low from the third reference voltage to the first reference voltage, the second string of select lines is selected and the second string of select lines is pulled high from the first reference voltage to the third reference voltage, the selected first word line is maintained at the fourth reference voltage, and the unselected second word line is maintained at the fifth reference voltage; sensing is performed in a fourth stage.
[0010] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description
[0011] Figure 1 A circuit diagram of a memory device according to an embodiment of the present invention is shown.
[0012] Figure 2 A schematic diagram and waveform diagram of a memory operation method according to an embodiment of the present invention are shown.
[0013] Figure 3 A schematic diagram and waveform diagram of a memory operation method according to another embodiment of the present invention are shown.
[0014] Figure 4 and Figure 5 This illustrates a method of operating a memory device according to yet another embodiment of the present invention.
[0015] Figure 6 This illustrates a method of operating a memory device according to yet another embodiment of the present invention.
[0016] Figure 7 This illustrates a method of operating a memory device according to yet another embodiment of the present invention.
[0017] Explanation of reference numerals in the attached figures
[0018] 100: Memory device; B0~BQ: Memory block
[0019] 120: Page buffer circuit; CSL: Common source line
[0020] GSL0~GSLQ: Overall source line; SSL0~SSLN: Serial select line
[0021] WL0~WLM: Word lines; BL0~BLP: Bit lines
[0022] SW1, SW2: Switches
[0023] SS: Memory String
[0024] 121_0~121_P: Page buffer
[0025] Id: Current
[0026] 150, 151, 160: Areas
[0027] 130: Accumulator Circuit
[0028] P21~P24, P31~P34, P41~P46, P51~P56: Stages
[0029] 610-640, 710-740: Steps Detailed Implementation
[0030] The technical terms used in this specification refer to those commonly used in the field. Where this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this specification. Each embodiment of this disclosure has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.
[0031] Figure 1 This diagram shows a circuit schematic of a memory device 100 according to an embodiment of the present invention. The memory device 100 is, for example, but not limited to, a three-dimensional (3D) memory device. Figure 1As shown, the memory device 100 includes multiple memory blocks B0 to BQ (Q is a positive integer), a page buffer circuit 120, a common source line CSL, multiple global source lines (also known as global signal lines) GSL0 to GSLQ, multiple string select lines SSL0 to SSLN (N is a positive integer), multiple word lines WL0 to WLM (M is a positive integer), and multiple bit lines BL0 to BLP (P is a positive integer).
[0032] Each of these memory blocks B0 to BQ includes multiple switches SW1, multiple switches SW2, and multiple memory strings SS. Each memory string SS includes multiple memory cells MC. These memory cells MC are located at the intersections of these word lines WL0 to WLM and these bit lines BL0 to BLP. Within the same memory block, these memory cells MC coupled to the same bit line form a memory string SS.
[0033] These switches SW1 are located at the intersections of the string selection lines SSL0 to SSLN and the bit lines BL0 to BLP. When an associated memory string SS is selected, the associated switch SW1 will be turned on.
[0034] These switches SW2 are located at the intersections of the overall source lines GSL0 to GSLQ and the bit lines BL0 to BLP. When an associated memory block is selected, the associated switch SW2 will be turned on.
[0035] The current Id of multiple cells flowing through these memory strings SS will flow through the common source line CSL to the relevant back-end circuitry (e.g., but not limited to, an accumulation circuit) to perform relevant operations (e.g., but not limited to, multiply-accumulate (MAC), data read, data write, etc.).
[0036] Page buffer circuit 120 includes multiple page buffers 121_0 to 121_P. Each page buffer 121_0 to 121_P is coupled to bit lines BL0 to BLP.
[0037] Figure 2 This diagram shows a schematic and waveform representation of a memory operation method according to an embodiment of the present invention. Figure 2 In the diagram, for ease of explanation, these memory cells MCs coupled to the same word line (such as WL0) are drawn to clearly show the operation when switching the serial select line. Furthermore, during serial select line switching, although... Figure 2Therefore, the switches are sequentially (SSL0→SSL1…), but it should be understood that the present invention is not limited to this, and the switching order of the string select line can be other orders, which are also within the spirit and scope of the present invention.
[0038] The following description uses memory block B0 (overall source line GSL0), string select lines SSL0 and SSL1, and word lines WL0 and WL1 as examples, but it should be understood that the present invention is not limited thereto. For ease of explanation, data originally accessed other memory blocks is accessed, but after address decoding, for example, it is found that the next piece of data is stored in the memory cell MC at the intersection of string select line SSL0 and word line WL0 in memory block B0 (that is, string select line SSL0 is the selected string select line, and word line WL0 is the selected word line).
[0039] Within stage P21, the overall source line GSL0 is selected by being pulled high from the first reference voltage to the second reference voltage; the string select line SSL0 is selected by being pulled high from the first reference voltage to the third reference voltage; other string select lines SSL1 to SSLN are unselected to remain at the first reference voltage; the word line WL0 is selected by being pulled high from the first reference voltage to the fourth reference voltage; other word lines WL1 to WLM are unselected to be pulled high from the first reference voltage to the fifth reference voltage (higher than the fourth reference voltage). In this way, these memory cells MC within region 150 (such as…) can be selected. Figure 1 and Figure 2 (As shown).
[0040] Then, sensing will be performed in phase P22.
[0041] After address decoding, for example, it is found that the next data is stored in the memory cell MC at the intersection of the string select line SSL1 and the word line WL0 in memory block B0 (that is, the string select line SSL1 is the selected string select line, and the word line WL0 is the selected word line). In other words, the selected string select line changes (from the string select line SSL0 to the string select line SSL1), but the selected word line does not change (it is still the word line WL0).
[0042] In stage P23, the selected source line GSL0 is maintained at the second reference voltage; the non-selected string select line SSL0 is pulled down from the third reference voltage to the first reference voltage; the other non-selected string select lines SSL2 to SSLN are maintained at the first reference voltage; the selected string select line SSL1 is pulled up from the first reference voltage to the third reference voltage; the selected word line WL0 is maintained at the fourth reference voltage; and the non-selected word lines WL1 to WLM are maintained at the fifth reference voltage. In this way, these memory cells MC within region 151 (such as…) can be selected. Figure 1 and Figure 2 (As shown).
[0043] Then, sensing takes place in phase P24.
[0044] Similarly, after address decoding, to access the next data, the selected string selection line needs to be changed (for example, from string selection line SSL1 to string selection line SSL2), but the selected word line remains unchanged. In the next stage, the selected overall source line GSL0 is maintained at the second reference voltage; the non-selected string selection line SSL1 is pulled down from the third reference voltage to the first reference voltage; the other non-selected string selection lines SSL0 and SSL3 to SSLN are maintained at the first reference voltage; the selected string selection line SSL2 is pulled up from the first reference voltage to the third reference voltage; the selected word line WL0 is maintained at the fourth reference voltage; and the other non-selected word lines WL1 to WLM are maintained at the fifth reference voltage.
[0045] Similarly, after address decoding, in order to access the next piece of data, if it is necessary to switch to a different memory block, an operation similar to stage P21 needs to be performed again.
[0046] like Figure 2 As shown, the memory device 100 further includes an accumulation circuit 130 coupled to a page buffer circuit 120.
[0047] The data read from these selected memory cells MC are first input into the page buffer circuit 120, and then transmitted to the accumulation circuit 130 (the present invention is not limited thereto) for MAC operation to obtain the output data.
[0048] That is, at Figure 2 In the operation method, after the initialization phase (P21), when reading data within the same memory block, if a string selection line switch is required, the overall source line level is maintained, the selected word line and the non-selected word line level are maintained, and the level of the next selected string selection line is switched with the level of the currently selected string selection line (as in phase P23). This approach can shorten the background setup time of memory device operation (phases P21 to P24 can be regarded as the multiplication bit line setup time and word line setup time in MAC operation).
[0049] Furthermore, in this invention Figure 2 In this embodiment, by switching memory blocks and serial select lines, word line setting time can be reduced compared to traditional techniques, thereby accelerating the operation.
[0050] Furthermore, in this invention Figure 2 In the embodiments, if the memory device has multiple memory planes and each memory plane has its own accumulation circuit, then the accumulation and output of MAC operations can be performed using a pipelined approach.
[0051] Figure 3 A schematic diagram and waveform diagram of a memory operation method according to another embodiment of the present invention are shown. Figure 3 In the diagram, for ease of explanation, these memory cells (MCs) coupled to the same select line (such as SSL0) are drawn to clearly show the operation during word line switching. Furthermore, during word line switching, although... Figure 3 Therefore, the switching is sequential (WL0→WL1…), but it should be understood that the present invention is not limited to this, and the switching order of the word lines can be other orders, which are also within the spirit and scope of the present invention.
[0052] The following description uses memory block B0 (overall source line GSL0), string select lines SSL0 and SSL1, and word lines WL0 and WL1 as examples, but it should be understood that the present invention is not limited thereto. For ease of explanation, data originally accessed other memory blocks is accessed, but after address decoding, for example, it is found that the next piece of data is stored in the memory cell MC at the intersection of string select line SSL0 and word line WL0 in memory block B0 (that is, string select line SSL0 is the selected string select line, and word line WL0 is the selected word line).
[0053] Within stage P31, the overall source line GSL0 is selected and pulled high from the first reference voltage to the second reference voltage; the string select line SSL0 is selected and pulled high from the first reference voltage to the third reference voltage; the other string select lines SSL1 to SSLN are not selected and are maintained at the first reference voltage; the word line WL0 is selected and pulled high from the first reference voltage to the fourth reference voltage; the remaining word lines WL1 to WLM are not selected and pulled high from the first reference voltage to the fifth reference voltage (higher than the fourth reference voltage). In this way, these memory cells MC within region 150 (such as…) can be selected. Figure 1 and Figure 3 (As shown).
[0054] Then, sensing is performed within stage P32.
[0055] After address decoding, for example, it is found that the next data is stored in the memory cell MC at the intersection of the string select line SSL0 and the word line WL1 in memory block B0 (that is, the string select line SSL0 is still the selected string select line, and the word line WL1 is the selected word line). In other words, the selected string select line does not change (it is still the string select line SSL0), but the selected word line changes (from word line WL0 to WL1).
[0056] In stage P33, the selected source line GSL0 is maintained at the second reference voltage; the selected string selection line SSL0 is maintained at the third reference voltage; the unselected string selection lines SSL1 to SSLN are maintained at the first reference voltage; the unselected word line WL0 is pulled high from the fourth reference voltage to the fifth reference voltage; the other unselected word lines WL2 to WLM are maintained at the fourth reference voltage; and the selected word line WL1 is pulled low from the fifth reference voltage to the fourth reference voltage. In this way, these memory cells MC within region 160 (such as…) can be selected. Figure 1 and Figure 3 (As shown).
[0057] Then, sensing is performed in phase P34.
[0058] Similarly, after address decoding, to access the next data, the selected word line needs to be changed (e.g., from word line WL1 to word line WL2), but the selected string selection line remains unchanged. In the next stage, the overall source line GSL0 of the selected string is maintained at the second reference voltage; the selected string selection line SSL0 is maintained at the third reference voltage; the non-selected string selection lines SSL1 to SSLN are maintained at the first reference voltage; the non-selected word line WL1 is pulled high from the fourth reference voltage to the fifth reference voltage; the other non-selected word lines WL0 and WL3 to WLM are maintained at the fifth reference voltage; and the selected word line WL2 is pulled low from the fifth reference voltage to the fourth reference voltage.
[0059] The data read from these selected memory cells MC are first input into the page buffer circuit 120, and then transmitted to the accumulation circuit 130 (the present invention is not limited thereto) for MAC operation to obtain the output data.
[0060] That is, at Figure 3 In the operation method, after the initialization phase (P31), when reading data within the same memory block, and when word line switching is required, the overall source line level is maintained, the selected string selection line and the non-selected string selection line level are maintained, and the level of the next selected word line is switched with the level of the currently selected word line (as in phase P33). This approach can shorten the background setup time of memory device operation (phases P31 to P34 can be regarded as the multiplication bit line setup time and word line setup time in MAC operation).
[0061] Furthermore, in this invention Figure 3 In this embodiment, by switching memory blocks, serial select lines, and word lines, word line setting time can be reduced compared to traditional techniques, thereby accelerating the operation.
[0062] Furthermore, in this invention Figure 3In the embodiments, if the memory device has multiple memory planes and each memory plane has its own accumulation circuit, then the accumulation and output of MAC operations can be performed using a pipelined approach.
[0063] Furthermore, in other possible embodiments of the present invention, Figure 2 and Figure 3 The operating methods can be combined arbitrarily, and all of them are within the spirit and scope of this invention. Figure 4 and Figure 5 This illustrates a method of operating a memory device according to yet another embodiment of the present invention.
[0064] At Figure 4 In the middle, stages P41-P44 are the same as or similar to Figure 2 Stages P21-P24 and stages P45-P46 are the same as or similar to Figure 3 The relevant sections are on pages 33-34, so details are omitted here.
[0065] That is, at Figure 4 First, the string selection line is switched (the selected string selection line is switched from string selection line SSL0 to string selection line SSL1, as shown in stage P43), and then the word line is switched (the selected word line is switched from word line WL0 to word line WL1, as shown in stage P45).
[0066] At Figure 5 In the middle, stages P51-P54 are the same as or similar to Figure 3 Stages P31-P34 and stages P55-P56 are the same as or similar to Figure 2 The details of the stages are omitted here, which are on pages 23-24.
[0067] That is, at Figure 5 First, the word line is switched (the selected word line is switched from word line WL0 to word line WL1, as shown in stage P53), and then the string selection line is switched (the selected string selection line is switched from string selection line SSL0 to string selection line SSL1, as shown in stage P55).
[0068] Figure 6This illustrates an operation method of a memory device according to another embodiment of the present invention. The operation method of the memory device includes: (610) in a first stage, selecting an integral signal line to pull the integral signal line high from a first reference voltage to a second reference voltage, selecting a first select line to pull the first select line high from the first reference voltage to a third reference voltage, not selecting a second select line to maintain it at the first reference voltage, selecting a first word line to pull the first word line high from the first reference voltage to a fourth reference voltage, and not selecting a second word line to pull the second word line high from the first reference voltage to a fifth reference voltage. Voltage; (620) sensing in a second stage; (630) in a third stage, maintaining the overall signal line at the second reference voltage, not selecting the first string of select lines and pulling the first string of select lines down from the third reference voltage to the first reference voltage, selecting the second string of select lines and pulling the second string of select lines up from the first reference voltage to the third reference voltage, maintaining the selected first word line at the fourth reference voltage, and maintaining the unselected second word line at the fifth reference voltage; and (640) sensing in a fourth stage.
[0069] Figure 7 This illustrates an operation method of a memory device according to another embodiment of the present invention. The operation method includes: (710) in a first stage, selecting an integral signal line to pull the integral signal line high from a first reference voltage to a second reference voltage, selecting a first select line to pull the first select line high from the first reference voltage to a third reference voltage, not selecting a second select line to maintain it at the first reference voltage, selecting a first word line to pull the first word line high from the first reference voltage to a fourth reference voltage, and not selecting a second word line to pull the second word line high from the first reference voltage to a third reference voltage. Five reference voltages; (720) sensing in a second stage; (730) in a third stage, maintaining the overall signal line at the second reference voltage, maintaining the selected first string of select lines at the third reference voltage, maintaining the unselected second string of select lines at the first reference voltage, unselecting the first word line so that the first word line is pulled up from the fourth reference voltage to the fifth reference voltage, and selecting the second word line so that the second word line is pulled down from the fifth reference voltage to the fourth reference voltage; and (740) sensing in a fourth stage.
[0070] As can be seen from the above, in the above embodiments of the present invention, a faster operation speed (e.g., but not limited to, a faster MAC operation speed, a faster data read / write speed, etc.) can be provided because the background setup time can be reduced before sensing (e.g., the multiplication bit line setup time and word line setup time in MAC operation can be reduced).
[0071] The above embodiments of the present invention can be applied to three-dimensional NAND flash memory, or memory devices sensitive to retention and thermal changes, such as, but not limited to, three-dimensional NOR flash memory, phase-change (PCM) flash memory, magnetic random access memory, or resistive RAM.
[0072] The above embodiments of the present invention can be applied to different artificial intelligence (AI) models that require the execution of multiple MAC operations, such as, but not limited to, fully connected layers, convolutional layers, multilayer perceptrons, support vector machines, etc.
[0073] The above embodiments of the present invention can be applied to accelerate MAC operations, read operations, write operations, etc.
[0074] The above embodiments of the present invention can be applied to computing use, as well as data searching, analysis, clustering analysis, etc.
[0075] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention should be determined by the appended claims.
Claims
1. A method of operating a memory device, the memory device comprising a plurality of memory cells, characterized in that, The operation method of the memory device includes: In a first stage, a whole signal line is selected to pull the whole signal line from a first reference voltage to a second reference voltage, a first string select line is selected to pull the first string select line from the first reference voltage to a third reference voltage, a second string select line is not selected to maintain at the first reference voltage, a first word line is selected to pull the first word line from the first reference voltage to a fourth reference voltage, and a second word line is not selected to pull the second word line from the first reference voltage to a fifth reference voltage; Sensing will be conducted within the second phase; In a third stage, the overall signal line is maintained at the second reference voltage, the first select line is not selected and pulled down from the third reference voltage to the first reference voltage, the second select line is selected and pulled up from the first reference voltage to the third reference voltage, the selected first word line is maintained at the fourth reference voltage, and the unselected second word line is maintained at the fifth reference voltage; and Sensing will be conducted within the fourth stage.
2. The method of operating the memory device according to claim 1, characterized in that, The memory device further includes a page buffer circuit and an accumulation circuit. Data read from at least one of the selected memory cells is input into the page buffer circuit and then transmitted to the accumulation circuit for multiplication and addition operations to obtain output data.
3. The method of operating the memory device according to claim 1, characterized in that, The memory device includes multiple memory planes, and each of these memory planes includes an accumulation circuit, so the accumulation and output of a multiply-accumulate-add operation is pipelined.
4. The method of operating the memory device according to claim 1, characterized in that, Also includes: In a fifth stage, the overall signal line is maintained at the second reference voltage, the selected second string of select lines is maintained at the third reference voltage, the unselected first string of select lines is maintained at the first reference voltage, the first word line is unselected so that the first word line is pulled up from the fourth reference voltage to the fifth reference voltage, and the second word line is selected so that the second word line is pulled down from the fifth reference voltage to the fourth reference voltage; as well as Sensing will be conducted within the sixth stage.
5. A method of operating a memory device, the memory device comprising a plurality of memory cells, characterized in that, The operation method of the memory device includes: In a first stage, a whole signal line is selected to pull the whole signal line from a first reference voltage to a second reference voltage, a first string select line is selected to pull the first string select line from the first reference voltage to a third reference voltage, a second string select line is not selected to maintain at the first reference voltage, a first word line is selected to pull the first word line from the first reference voltage to a fourth reference voltage, and a second word line is not selected to pull the second word line from the first reference voltage to a fifth reference voltage; Sensing will be conducted within the second phase; In a third stage, the overall signal line is maintained at the second reference voltage, the selected first select line is maintained at the third reference voltage, the unselected second select line is maintained at the first reference voltage, the unselected first word line is pulled high from the fourth reference voltage to the fifth reference voltage, and the selected second word line is pulled low from the fifth reference voltage to the fourth reference voltage; and Sensing will be conducted within the fourth stage.
6. The method of operating the memory device according to claim 5, characterized in that, The memory device also includes a page buffer circuit and an accumulation circuit. Data read from at least one of the selected memory cells is input into the page buffer circuit and then transmitted to the accumulation circuit for multiplication and addition operations to obtain output data.
7. The method of operating the memory device according to claim 5, characterized in that, The memory device includes multiple memory planes, and each of these memory planes includes an accumulation circuit, so the accumulation and output of a multiply-accumulate-add operation is pipelined.
8. The method of operating the memory device according to claim 5, characterized in that, Also includes: In a fifth stage, the overall signal line is maintained at the second reference voltage, the first select line is not selected and the first select line is pulled down from the third reference voltage to the first reference voltage, the second select line is selected and the second select line is pulled up from the first reference voltage to the third reference voltage, the selected second word line is maintained at the fourth reference voltage, and the unselected first word line is maintained at the fifth reference voltage; as well as Sensing will be conducted within the sixth stage.
9. A memory device, characterized in that, include: Multiple memory units; Multiple integrated signal lines; Multiple bit lines; Multiple string selection lines; Multiple word lines are coupled to these memory cells, which in turn are coupled to these bit lines; Multiple first switches are coupled to these serial select lines and these bit lines; as well as Multiple second switches are coupled to these overall signal lines and these bit lines; in, In a first stage, a first overall signal line of these overall signal lines is selected to pull the first overall signal line from a first reference voltage to a second reference voltage, a first string select line of these string select lines is selected to pull the first string select line from the first reference voltage to a third reference voltage, a second string select line of these string select lines is not selected to remain at the first reference voltage, a first word line of these word lines is selected to pull the first word line from the first reference voltage to a fourth reference voltage, and a second word line of these word lines is not selected to pull the second word line from the first reference voltage to a fifth reference voltage; Sensing will be conducted within the second phase; In a third stage, the first overall signal line is maintained at the second reference voltage, the first string select line is not selected and the first string select line is pulled down from the third reference voltage to the first reference voltage, the second string select line is selected and the second string select line is pulled up from the first reference voltage to the third reference voltage, the selected first word line is maintained at the fourth reference voltage, and the unselected second word line is maintained at the fifth reference voltage. as well as Sensing will be conducted within the fourth stage.
10. The memory device according to claim 9, characterized in that, In a fifth stage, the first overall signal line is maintained at the second reference voltage, the selected second string selection line is maintained at the third reference voltage, the unselected first string selection line is maintained at the first reference voltage, the first word line is unselected so that the first word line is pulled high from the fourth reference voltage to the fifth reference voltage, and the second word line is selected so that the second word line is pulled low from the fifth reference voltage to the fourth reference voltage; as well as Sensing will be conducted within the sixth stage.