Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a first dielectric material layer on the substrate surface, the first dielectric material layer being located on the first dummy gate structure and the second dummy gate structure sidewall; forming a second dielectric material layer on the first dielectric material layer, the second dielectric material layer thickness on the first region being less than the second dielectric material layer thickness on the second region; planarizing the first dielectric material layer and the second dielectric material layer until the first dummy gate and the second dummy gate are exposed, the first dielectric material layer forming a first transition dielectric layer; etching back the first transition dielectric layer to form a first initial dielectric layer, and the first initial dielectric layer thickness on the first region being lower than the first initial dielectric layer thickness on the second region; forming a protective layer on the first initial dielectric layer surface, improving the control window of the gate forming process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speeds, larger data storage capacity, and more functions, integrated circuit chips are moving towards higher device density and higher integration. As the feature size of devices continues to shrink to the nanometer scale, polysilicon gate technology can no longer meet the requirements of existing technologies. The semiconductor industry uses metal gates (MG) to replace polysilicon gate electrodes to solve problems such as threshold voltage drift, polysilicon gate depletion effect, excessively high gate resistance, and Fermi level pinning.

[0003] As device feature sizes continue to decrease, there is a need to reduce the metal gate height to obtain lower effective capacitance. However, in metal-substituted gate processes, it is difficult to achieve precise control over low-height metal gates due to factors such as wafer uniformity and loading effects during etching.

[0004] Therefore, the existing metal gate forming process needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region; forming a first dummy gate structure on the first region and a second dummy gate structure on the second region, the first dummy gate structure including a first dummy gate and the second dummy gate structure including a second dummy gate; forming a first dielectric material layer on the surface of the substrate, the first dielectric material layer being located on the sidewalls of the first dummy gate structure and the second dummy gate structure; forming a second dielectric material layer on the first dielectric material layer, the thickness of the second dielectric material layer on the first region being less than the thickness of the second dielectric material layer on the second region; planarizing the first dielectric material layer and the second dielectric material layer until the first dummy gate and the second dummy gate are exposed, thereby forming a first transition dielectric layer with the first dielectric material layer; etching back the first transition dielectric layer to form a first initial dielectric layer, wherein the thickness of the first initial dielectric layer on the first region is less than the thickness of the first initial dielectric layer on the second region; forming a protective layer on the surface of the first initial dielectric layer, the protective layer being located on the sidewalls of the first dummy gate and the second dummy gate and exposing the first dummy gate and the second dummy gate; forming a first gate to replace the first dummy gate and forming a second gate to replace the second dummy gate.

[0007] Optionally, the method for planarizing the first dielectric material layer and the second dielectric material layer includes: planarizing the second dielectric material layer using a first mechanochemical polishing process until the first dielectric material layer is exposed, wherein the polishing rate of the first mechanochemical polishing process on the second dielectric material layer is greater than the polishing rate on the first dielectric material layer; and after the first mechanochemical polishing process, planarizing the first dielectric material layer using a second mechanochemical polishing process until the first dummy gate and the second dummy gate are exposed.

[0008] Optionally, the material of the first dielectric material layer includes silicon oxide; the formation process of the first dielectric material layer includes fluid chemical vapor deposition; the material of the second dielectric material layer includes silicon oxide; the formation process of the second dielectric material layer includes plasma enhanced chemical vapor deposition.

[0009] Optionally, the process of etching back the first transition dielectric layer includes a dry etching process; the process parameters of the dry etching process include: the etching gas includes a combination of one or more gases selected from carbon tetrafluoride, hydrogen fluoride, nitrogen, argon, and trifluoromethane, the etching gas flow rate ranges from 5 sccm to 1000 sccm, and the etching power ranges from 50 watts to 1000 watts.

[0010] Optionally, the first dummy gate structure further includes a first dummy gate dielectric layer located between the first dummy gate and the substrate; the second dummy gate structure further includes a second dummy gate dielectric layer located between the second dummy gate and the substrate; the material of the protective layer is different from the materials of the first dummy gate dielectric layer and the second dummy gate dielectric layer.

[0011] Optionally, the method for the first gate and the second gate includes: removing the first dummy gate, the second dummy gate, the first dummy gate dielectric layer and the second dummy gate dielectric layer; forming a gate trench in the first initial dielectric layer and the protective layer; forming a gate material layer in the gate trench and on the surface of the protective layer; planarizing the gate material layer until the surface of the first initial dielectric layer on the first region is exposed; forming the first gate with the gate material layer on the first region; forming the second gate with the gate material layer on the second region; and forming the first dielectric layer with the first initial dielectric layer.

[0012] Optionally, the method for planarizing the gate material layer includes: planarizing the gate material layer using a third mechanical chemical polishing process until the surface of the protective layer is exposed to form an initial gate; etching the protective layer until the surface of the initial first dielectric layer is exposed; and planarizing the initial gate using a fourth mechanical chemical polishing process.

[0013] Optionally, the first region includes an isolation region, and the method further includes: after forming the first transition dielectric layer and before etching back the first transition dielectric layer, removing the first dummy gate on the isolation region, forming an isolation opening in the first transition dielectric layer and the first dummy gate, and forming an isolation structure in the isolation opening.

[0014] Optionally, the method for forming the isolation opening further includes: forming a first hard mask layer on the top surface of the first transition dielectric layer, the first dummy gate, and the second dummy gate, wherein the first hard mask layer exposes the first dummy gate on the isolation region; and etching the first dummy gate using the first hard mask layer as a mask.

[0015] Optionally, the method for forming the first hard mask layer includes: forming a hard mask material layer on the top surface of the first transition dielectric layer, the first dummy gate, and the second dummy gate; and patterning the hard mask material layer to form the first hard mask layer.

[0016] Optionally, the material of the first hard mask layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.

[0017] Optionally, the method of forming the isolation structure includes: forming an insulating material layer inside the isolation opening and on the surface of the first hard mask layer; planarizing the insulating material layer and the first hard mask layer until the surfaces of the first dummy gate and the second dummy gate are exposed.

[0018] Optionally, the method for forming the protective layer includes: forming a protective material layer on the surface of the first initial dielectric layer, the protective material layer also being located on the top surfaces of the first dummy gate and the second dummy gate; planarizing the protective material layer until the top surfaces of the first dummy gate and the second dummy gate are exposed.

[0019] Optionally, the process for forming the protective material layer includes atomic layer deposition.

[0020] Optionally, the method for planarizing the protective material layer further includes: forming a third dielectric material layer on the surface of the protective material layer, the material of the third dielectric material layer being different from the material of the protective material layer; planarizing the third dielectric material layer using a fifth mechanical-chemical polishing process until the surface of the protective material layer is exposed; and after the fifth mechanical-chemical polishing process, etching back the protective material layer until the top surfaces of the first dummy gate and the second dummy gate are exposed.

[0021] Optionally, the material of the third dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0022] Optionally, the material of the first dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride; the material of the second dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0023] Optionally, before forming the first dielectric material layer, an etch stop layer is also formed on the surfaces of the substrate, the first dummy gate structure, and the second dummy gate structure.

[0024] Optionally, the material of the protective layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

[0025] Optionally, the first initial dielectric layer on the first region has a first thickness value, and the first initial dielectric layer on the second region has a second thickness value, wherein the first thickness value is lower than the second thickness value by a range of 5 nanometers to 15 nanometers.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0027] In the semiconductor structure formation method provided by the present invention, on the one hand, a first dielectric material layer and a second dielectric material layer located on the surface of the first dielectric material layer are formed on the substrate surface. Since the device density in the first region is high, the thickness of the first dielectric material layer in the first region is greater than the thickness of the second dielectric material layer in the second region, and the thickness of the second dielectric material layer in the first region is less than the thickness of the second dielectric material layer in the second region. This makes the surface of the second dielectric material layer relatively flat, reducing surface non-uniformity caused by the different film thicknesses in subsequent planarization. On the other hand, by planarizing the first dielectric material layer and the second dielectric material layer, the first dummy gate and the second dummy gate are exposed. Then, by controlling the gate height by controlling the dummy gate height, the etching difference of the sidewall height caused by the difference in device density in different regions is avoided in the process of controlling the gate height by the sidewall. In addition, a protective layer is formed on the surface of the first initial dielectric layer. This protective layer plays a role in protecting the first initial dielectric layer during the mechanochemical polishing process of replacing the first dummy gate to form the first gate and replacing the second dummy gate to form the second gate. Furthermore, the thickness of the first initial dielectric layer on the first region is lower than the thickness of the first initial dielectric layer on the second region, which can reduce the occurrence of over-etching problems in the second region due to the low device density in the second region during the subsequent planarization of the gate material layer, and further improve the control window of the gate formation process.

[0028] Furthermore, during the planarization process using the first and second mechanochemical polishing processes to expose the first and second dummy gates, the surface flatness is increased by adjusting the polishing process. Specifically, since the device density in the first region is greater than that in the second region, after the first mechanochemical polishing process, there is a second dielectric material layer residue on the surface of the first dielectric material layer in the second region. In the second mechanochemical polishing process, a process with a similar polishing and etching ratio for the first and second dielectric material layers is selected, which can obtain a first transition dielectric layer with a relatively flat surface, which is beneficial for precise control of the formed gate height.

[0029] Furthermore, the material of the first dielectric material layer includes silicon oxide; the formation process of the first dielectric material layer includes fluid chemical vapor deposition (FCVD); the material of the second dielectric material layer includes silicon oxide; the formation process of the second dielectric material layer includes plasma-enhanced chemical vapor deposition (PECVD). The FCVD process facilitates the filling of the first dielectric material layer between adjacent first gate structures and adjacent second gate structures, reducing the generation of abnormalities such as voids and defects. The PCVD process facilitates the formation of a relatively flat surface of the second dielectric material layer, thereby improving the flatness of the substrate surface after subsequent planarization. The PCVD process facilitates the formation of a flat second dielectric material layer, which in turn facilitates the control of surface flatness in the subsequent planarization process, thereby improving the process window for gate height control.

[0030] Furthermore, the first pseudo-gate structure further includes a first pseudo-gate dielectric layer, and the second pseudo-gate structure further includes a second pseudo-gate dielectric layer. During the etching process of removing the first pseudo-gate dielectric layer and the second pseudo-gate dielectric layer, the protective layer plays a role in protecting the first initial dielectric layer, reducing over-etching of the first initial dielectric layer, and improving the flatness of the device surface. Attached Figure Description

[0031] Figures 1 to 7 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0032] Figures 8 to 28 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0033] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0034] As described in the background section, existing metal gate formation processes require further improvement. A method for forming a semiconductor structure will now be explained and analyzed.

[0035] Figures 1 to 7 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0036] Please refer to Figure 1A substrate 100 is provided, the substrate 100 including a first region I and a second region II; a first dummy gate structure and a second dummy gate structure are formed on the substrate 100, the first dummy gate structure being located on the first region I and the second dummy gate structure being located on the second region II. The first dummy gate structure includes a first initial dummy gate 101, a first hard mask layer located on the first initial dummy gate 101, and a first initial sidewall 102 located on the sidewalls of the first initial dummy gate 101 and the first hard mask layer. The first hard mask layer includes a first silicon nitride layer 103 and a first silicon oxide layer 104 located on the first silicon nitride layer 103. The second dummy gate structure includes a second initial dummy gate 201, a second hard mask layer located on the second initial dummy gate 201, and a second initial sidewall 202 located on the sidewalls of the second initial dummy gate 201 and the second hard mask layer. The second hard mask layer includes a second silicon oxide layer 203 and a second silicon oxide layer 204 located on the second silicon nitride layer 203. The distance between adjacent first dummy gate structures is smaller than the distance between adjacent second dummy gate structures. An etch stop layer 105 is formed on the substrate, the first dummy gate structure, and the second dummy gate structure. A spin-coated carbon material layer 106 is formed on the surface of the etch stop layer 105.

[0037] Please refer to Figure 2 A patterned layer (not shown in the figure) is formed on the surface of the spin-coated carbon material layer 106, and the surface of the patterned layer exposes the etch stop layer 105 on the top surface of the first dummy gate structure and the second dummy gate structure. The etch stop layer 105, the first initial sidewall 102 and the second initial sidewall 202 are etched to form a first transition sidewall 107 with the first initial sidewall 102 and a second sidewall 207 with the second initial sidewall 202. After forming the first transition sidewall 107 and the second sidewall 207, the spin-coated carbon material layer 106 is removed.

[0038] Please refer to Figure 3 After removing the spin-coated carbon material layer 106, a dielectric material layer 108 is formed on the surface of the substrate 100, and the dielectric material layer 108 exposes the first silicon nitride layer 103 and the second silicon nitride layer 203.

[0039] Please refer to Figure 4 After the dielectric material layer 108 is formed, the first silicon nitride layer 103 and the second silicon nitride layer 203 are removed by selective etching process, and the first transition sidewall 107 is etched to form the first intermediate sidewall 109.

[0040] Please refer to Figure 5The first intermediate sidewall 109, the first initial dummy gate 101, and the second initial dummy gate 201 are etched back, and the first sidewall 110 is formed with the first intermediate sidewall 109, the first dummy gate 111 is formed with the first initial dummy gate 101, and the second dummy gate 211 is formed with the second initial dummy gate 201.

[0041] Please refer to Figure 6 Remove the first dummy gate 111 and the second dummy gate 211, and form a gate groove (not shown in the figure) in the dielectric material layer 108; form a gate material layer 112 on the surface of the gate groove and the dielectric material layer 108.

[0042] Please refer to Figure 7 The gate material layer 112 and the dielectric material layer 108 are planarized until the first sidewall 110 and the second sidewall 207 are exposed. A dielectric layer 113 is formed with the dielectric material layer 108, a first gate 114 is formed with the gate material layer 112 on the first region I, and a second gate 214 is formed with the gate material layer 112 on the second region II.

[0043] The above method is used in the metal gate replacement process, where the heights of the first gate 114 and the second gate 214 are controlled by controlling the heights of the first sidewall 110 and the second sidewall 207. The first region I is used to form a short-channel device region, and the second region II is used to form a long-channel device region. During the etching of the first initial sidewall 102 and the second initial sidewall 202 using the spin-coated carbon material layer 106 as a protective layer, due to the different pattern densities of the first region I and the second region II, the thickness of the spin-coated carbon material layer 106 on the second region II is lower than that on the first region I. Furthermore, the spin-coated carbon material layer 106 on the second region II is more easily consumed during etching, resulting in the second sidewall 207 formed on the second region II being lower than the first transition sidewall 107 formed on the first region I. This height difference between the second sidewall 207 and the first transition sidewall 107 is detrimental to the precise control of the metal gate height and reduces the flatness of the device surface.

[0044] To address the aforementioned problems, this invention provides a method for forming a semiconductor structure. On one hand, a first dielectric material layer and a second dielectric material layer are formed on the surface of a substrate. The thickness of the first dielectric material layer in the first region is greater than the thickness of the second dielectric material layer in the second region, and the thickness of the second dielectric material layer in the first region is less than the thickness of the second dielectric material layer in the second region. This makes the surface of the second dielectric material layer relatively flat, reducing surface unevenness caused by the different film thicknesses during subsequent planarization. On the other hand, by planarizing the first and second dielectric material layers, the first and second dummy gates are exposed. The gate height is then controlled by controlling the height of the dummy gates, avoiding the etching differences in sidewall height caused by device density differences in different regions during the sidewall-controlled gate height process. In addition, a protective layer is formed on the surface of the first initial dielectric layer. This protective layer plays a role in protecting the first initial dielectric layer during the mechanochemical polishing process of replacing the first dummy gate to form the first gate and replacing the second dummy gate to form the second gate. Furthermore, the thickness of the first initial dielectric layer on the first region is lower than the thickness of the first initial dielectric layer on the second region, which can reduce the occurrence of over-etching problems in the second region due to the low device density in the second region during the subsequent planarization of the gate material layer, and further improve the control window of the gate formation process.

[0045] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Figures 8 to 28 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0047] Please refer to Figure 8 and Figure 9 , Figure 9 for Figure 8 A top-view structural diagram. Figure 8 yes Figure 9 A cross-sectional structural diagram along the EE1 direction is provided, and the substrate 301 includes a first region I and a second region II.

[0048] The substrate 301 can be monocrystalline silicon, polycrystalline silicon, or amorphous silicon, or it can be a semiconductor material such as germanium, silicon germanide, or gallium arsenide, or it can be a semiconductor-on-insulator structure.

[0049] The substrate 301 can be a planar structure or a non-planar structure, such as having fins formed within it. In this embodiment, the substrate 301 is single-crystal silicon and has a planar structure.

[0050] The first region I is used to form a short-channel device; the second region II is used to form a long-channel device. In this embodiment, the first region I further includes an isolation region A.

[0051] Please continue to refer to this. Figure 8 A first pseudo-gate structure is formed on the first region I, and a second pseudo-gate structure is formed on the second region II. The first pseudo-gate structure includes a first pseudo-gate 302, and the second pseudo-gate structure includes a second pseudo-gate 402.

[0052] In this embodiment, the first region I is used to form a short-channel device, and the second region II is used to form a long-channel device. Therefore, the distance between adjacent first pseudo-gate structures is smaller than the distance between adjacent second pseudo-gate structures.

[0053] The first dummy gate 302 is made of silicon; the second dummy gate 402 is also made of silicon. In this embodiment, both the first dummy gate 302 and the second dummy gate 402 are made of silicon. In other embodiments, the first dummy gate 302 may be made of polycrystalline silicon, amorphous carbon, etc.; and the second dummy gate 402 may be made of polycrystalline silicon, amorphous carbon, etc.

[0054] In this embodiment, the first pseudo gate structure further includes a first pseudo gate dielectric layer 303, which is located between the first pseudo gate 302 and the substrate 301; the second pseudo gate structure further includes a second pseudo gate dielectric layer 403, which is located between the second pseudo gate 402 and the substrate 301.

[0055] In this embodiment, the first dummy gate structure further includes a second hard mask layer 304 located on the first dummy gate 302; the second dummy gate structure further includes a third hard mask layer 404 located on the second dummy gate 402.

[0056] In this embodiment, the first dummy gate structure further includes a first sidewall 306 located on the sidewalls of the first dummy gate 302, the second hard mask layer 304, and the first dummy gate dielectric layer 303; the second dummy gate structure further includes a second sidewall 406 located on the sidewalls of the second dummy gate 402, the third hard mask layer 404, and the second dummy gate dielectric layer 403.

[0057] Subsequently, a first dielectric material layer is formed on the surface of the substrate 301.

[0058] In this embodiment, before forming the first dielectric material layer, an etch stop layer 305 is formed on the surfaces of the substrate 301, the first dummy gate structure, and the second dummy gate structure. In other embodiments, the etch stop layer 305 may not be formed.

[0059] It should be noted that, Figure 9 The etching stop layer 305 is omitted from the text.

[0060] Please refer to Figure 10 , Figure 10 The view direction is the same Figure 8 A first dielectric material layer 307 is formed on the surface of the substrate 301. The first dielectric material layer 307 is located on the sidewalls of the first dummy gate structure and the second dummy gate structure. The thickness of the first dielectric material layer 307 on the first region I is greater than the thickness of the first dielectric material layer 307 on the second region II. A second dielectric material layer 308 is formed on the first dielectric material layer 307. The thickness of the second dielectric material layer 308 on the first region I is less than the thickness of the second dielectric material layer 308 on the second region II.

[0061] Specifically, the surface of the first dielectric material layer 307 is higher than or flush with the top surface of the second dummy gate structure. In this embodiment, the surface of the first dielectric material layer 307 is higher than the top surface of the second dummy gate structure.

[0062] Because the device density in the first region I is high, the thickness of the first dielectric material layer 307 on the first region I is greater than the thickness of the second dielectric material layer 308 on the second region II. Forming the second dielectric material layer 308 on the first dielectric material layer 307, with a thickness less than that on the second region II, allows for a smoother surface of the second dielectric material layer 308, reducing surface unevenness caused by differences in film thickness during subsequent planarization.

[0063] The material of the first dielectric material layer 307 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride; the material of the second dielectric material layer 308 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbonitride.

[0064] In this embodiment, the material of the first dielectric material layer 307 includes silicon oxide; the formation process of the first dielectric material layer 307 includes a fluid chemical vapor deposition process; the material of the second dielectric material layer 308 includes silicon oxide; the formation process of the second dielectric material layer 308 includes a plasma enhanced chemical vapor deposition process.

[0065] The fluid chemical vapor deposition (FCVD) process facilitates filling between adjacent first gate structures and adjacent second gate structures, reducing the generation of void defects and other anomalies. Since the device density in the first region I is higher than that in the second region II, the thickness of the first dielectric material layer 307 on the first region I is greater than that on the second region II under the FCVD process. The plasma-enhanced chemical vapor deposition (PECVD) process facilitates the formation of a relatively flat surface for the second dielectric material layer 308, thereby improving the flatness of the device surface after subsequent planarization processing.

[0066] Subsequently, the first dielectric material layer 307 and the second dielectric material layer 308 are planarized until the first dummy gate and the second dummy gate are exposed, and the first dielectric material layer 307 is used to form the first transition dielectric layer.

[0067] For the method of planarizing the first dielectric material layer 307 and the second dielectric material layer 308, please refer to [reference needed]. Figures 11 to 12 .

[0068] Please refer to Figure 11 , Figure 11 The view direction is the same Figure 8 The second dielectric material layer 308 is planarized using a first mechanochemical polishing process until the first dielectric material layer 307 is exposed. The polishing rate of the first mechanochemical polishing process on the second dielectric material layer 308 is greater than the polishing rate on the first dielectric material layer 307.

[0069] In this embodiment, the first dielectric material layer 307 serves as the stop layer for planarization in the first mechanical-chemical polishing process. In other embodiments, the etching stop layer 305 can be used as the stop layer for planarization in the first mechanical-chemical polishing process.

[0070] Please refer to Figure 12 , Figure 12 The view direction is the same Figure 8 After the first mechanical chemical polishing process, a second mechanical chemical polishing process is used to planarize the first dielectric material layer 307 until the first dummy gate 302 and the second dummy gate 402 are exposed.

[0071] During the planarization process using a first and a second mechanochemical polishing process to expose the first dummy gate 302 and the second dummy gate 402, the surface smoothness is increased by adjusting the polishing process. Specifically, since the device density in the first region I is greater than that in the second region II, after the first mechanochemical polishing process, a second dielectric material layer 308 remains on the surface of the first dielectric material layer 307 in the second region II (e.g., ...). Figure 11As shown in the figure, the second mechanical chemical polishing process uses a process with a similar polishing and etching ratio for the first dielectric material layer 307 and the second dielectric material layer 308, which can obtain a first transition dielectric layer 309 with a relatively flat surface, which is beneficial for precise control of the formed gate height.

[0072] By planarizing the first dielectric material layer 307 and the second dielectric material layer 308, the first dummy gate 302 and the second dummy gate 402 are exposed. Then, by controlling the gate height by controlling the dummy gate height, the etching difference of the sidewall height caused by the difference in device density in different regions is avoided in the process of controlling the gate height by the sidewall.

[0073] In this embodiment, after forming the first transition dielectric layer 309 and before etching back the first transition dielectric layer 309, an isolation structure is formed in the isolation region A. The method is described in reference [reference needed]. Figures 13 to 17 .

[0074] Please refer to Figure 13 and Figure 14 , Figure 13 yes Figure 14 A schematic diagram of the cross-sectional structure along EE1. Figure 14 yes Figure 13 The top view of the structure shows that after the first transition dielectric layer 309 is formed and before the first transition dielectric layer 309 is etched back, the first dummy gate 302 on the isolation region A is removed, and an isolation opening 311 is formed in the first transition dielectric layer 309 and the first dummy gate 302.

[0075] The method for forming the isolation opening 311 further includes: forming a first hard mask layer 310 on the top surface of the first transition dielectric layer 309, the first dummy gate 302 and the second dummy gate 402, wherein the first hard mask layer 310 exposes the first dummy gate 302 on the isolation region A; and etching the first dummy gate 302 using the first hard mask layer 310 as a mask.

[0076] In this embodiment, the first pseudo-gate dielectric layer 303 on the isolation region A is also removed, and the first transition dielectric layer 309, the etch stop layer 305 and the first sidewall 306 are partially etched away to form the isolation opening 311.

[0077] The method for forming the first hard mask layer 310 includes: forming a hard mask material layer (not shown in the figure) on the top surface of the first transition dielectric layer 309, the first dummy gate 302 and the second dummy gate 402; and patterning the hard mask material layer to form the first hard mask layer 310.

[0078] In this embodiment, the first hard mask layer 310 has a three-layer structure. The hard mask material layer consists of three layers: a silicon oxide material layer, a silicon nitride material layer on the silicon oxide material layer, and a silicon oxide layer on the silicon nitride material layer. The hard mask material layer is formed using plasma-enhanced chemical vapor deposition (PECVD).

[0079] The first hard mask layer 310 serves as a mask to form an isolation opening 311 within the first dummy gate 302. The material of the first hard mask layer 310 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.

[0080] Subsequently, an isolation structure is formed within the isolation opening 311. For the method of forming the isolation structure, please refer to [reference needed]. Figures 15 to 17 .

[0081] Please refer to Figure 15 , Figure 15 The view direction is the same Figure 8 An insulating material layer 312 is formed inside the isolation opening 311 and on the surface of the first hard mask layer 310.

[0082] The insulating material layer 312 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the insulating material layer 312 is made of silicon nitride.

[0083] Please refer to Figure 16 and Figure 17 , Figure 16 yes Figure 17 A schematic diagram of the cross-sectional structure along the EE1 method. Figure 17 yes Figure 16 The top view of the structure shows that the insulating material layer 312 and the first hard mask layer 310 are planarized until the surfaces of the first dummy gate 302 and the second dummy gate 402 are exposed.

[0084] The isolation structure 314 is used to cut one of the first dummy gates 302 into two dummy gates that are electrically insulated.

[0085] Please refer to Figure 18 , Figure 18 The view direction is the same Figure 8 The first transition dielectric layer 309 is etched back to form a first initial dielectric layer 315, and the thickness m of the first initial dielectric layer 315 on the first region I is lower than the thickness n of the first initial dielectric layer 315 on the second region II.

[0086] The thickness m of the first initial dielectric layer 315 on the first region I is lower than the thickness n of the first initial dielectric layer 315 on the second region II. This can reduce the problem of over-etching in the second region II due to the low device density in the second region II during the subsequent planarization of the gate material layer, and further improve the control window of the gate formation process.

[0087] The first initial dielectric layer 315 on the first region I has a first thickness value, and the first initial dielectric layer 315 on the second region II has a second thickness value. The first thickness value is lower than the second thickness value by a range of 5 nanometers to 15 nanometers. The thickness refers to the dimension along the normal direction of the surface of the substrate 301.

[0088] The process of etching back the first transition dielectric layer 309 includes a dry etching process; the process parameters of the dry etching process include: the etching gas includes a combination of one or more gases selected from carbon tetrafluoride, hydrogen fluoride, nitrogen, argon, and trifluoromethane, the etching gas flow rate ranges from 5 sccm to 1000 sccm, and the etching power ranges from 50 watts to 1000 watts.

[0089] Subsequently, a protective layer is formed on the surface of the first initial dielectric layer 315. This protective layer is located on the sidewalls of the first dummy gate 302 and the second dummy gate 402, and exposes the first dummy gate 302 and the second dummy gate 402. For the method of forming the protective layer, please refer to [reference needed]. Figures 19 to 21 .

[0090] Please refer to Figure 19 , Figure 19 The view direction is the same Figure 8 A protective material layer 316 is formed on the surface of the first initial dielectric layer 315, and the protective material layer 316 is also located on the top surface of the first dummy gate 302 and the second dummy gate 402.

[0091] The protective material layer 316 is formed using an atomic layer deposition (ALD) process. In this embodiment, the protective material layer 316 is formed using an ALD process. The ALD process helps improve the quality of the protective material layer 316 and reduces the generation of defects.

[0092] The protective material layer 316 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the protective material layer 316 is made of silicon nitride.

[0093] The material of the protective material layer 316 is different from the materials of the first pseudo-gate dielectric layer 303 and the second pseudo-gate dielectric layer 403.

[0094] Subsequently, the protective material layer 316 is planarized until the top surfaces of the first dummy gate 302 and the second dummy gate 402 are exposed. For the method of planarizing the protective material layer 316, please refer to [reference needed]. Figures 19 to 21 .

[0095] Please continue to refer to this. Figure 19 A third dielectric material layer 317 is formed on the surface of the protective material layer 316, and the material of the third dielectric material layer 317 is different from the material of the protective material layer 316.

[0096] The material of the third dielectric material layer 317 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the material of the third dielectric material layer 317 is silicon oxide.

[0097] In this embodiment, the third dielectric material layer 317 is formed using plasma-enhanced chemical vapor deposition (PECVD). PECVD is beneficial for improving the surface smoothness of the formed film.

[0098] Please refer to Figure 20 , Figure 20 The view direction is the same Figure 8 The third medium material 317 is planarized using a fifth mechanical chemical polishing process until the surface of the protective material layer 316 is exposed.

[0099] Because the surface of the protective material layer 316 is uneven, after the fifth mechanical and chemical polishing process, some of the third medium material layer 316 remains on the surface of the protective material layer 316.

[0100] Please refer to Figure 21 , Figure 21 The view direction is the same Figure 8 After the fifth mechanical-chemical polishing process, the protective material layer 316 is etched back until the top surfaces of the first dummy gate 302 and the second dummy gate 402 are exposed.

[0101] The process of etching back the protective material layer 316 includes a non-selective dry etching process. The non-selective dry etching process has a similar etching rate for the protective material layer 316 and the third dielectric material 317, which can obtain a protective layer 318 with a relatively flat surface, so as to facilitate subsequent precise control of the gate height.

[0102] The protective layer 318 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the protective layer 318 is made of silicon nitride.

[0103] The material of the protective layer 318 is different from the materials of the first pseudo-gate dielectric layer 303 and the second pseudo-gate dielectric layer 403.

[0104] Subsequently, after the protective layer 318 is formed, a first gate is formed to replace the first dummy gate 302, and a second gate is formed to replace the second dummy gate 402.

[0105] For the methods of the first gate and the second gate, please refer to [reference needed]. Figures 22 to 28 .

[0106] Please refer to Figure 22 , Figure 22 for Figure 23 A schematic diagram of the cross-sectional structure along the EE1 direction. Figure 23 for Figure 22 The top view of the structure shows that the first dummy gate 302, the second dummy gate 402, the first dummy gate dielectric layer 303 and the second dummy gate dielectric layer 403 are removed, and a gate trench 319 is formed in the first initial dielectric layer 315 and the protective layer 318.

[0107] During the etching process of removing the first dummy gate dielectric layer 303 and the second dummy gate dielectric layer 403, the protective layer 318 serves to protect the first initial dielectric layer 315, reduce over-etching of the first initial dielectric layer 315, and improve the flatness of the device surface.

[0108] Please refer to Figure 24 , Figure 24 The view direction is the same Figure 8 A gate material layer 320 is formed in the gate trench 319 and on the surface of the protective layer 318.

[0109] The gate material layer 320 is made of metal.

[0110] In this embodiment, before forming the gate material layer 320, a gate dielectric layer 407 is also formed at the bottom of the gate trench 319.

[0111] Subsequently, the gate material layer 320 is planarized until the surface of the first initial dielectric layer 315 on the first region I is exposed. The first gate is formed with the gate material layer 320 on the first region I, the second gate is formed with the gate material layer 320 on the second region II, and the first dielectric layer is formed with the first initial dielectric layer 315. For the method of planarizing the gate material layer 320, please refer to [reference needed]. Figures 25 to 28 .

[0112] Please refer to Figure 25 , Figure 25 The view direction is the same Figure 8The gate material layer 320 is planarized using a third mechanical chemical polishing process until the surface of the protective layer 318 is exposed, forming the initial gate 321.

[0113] In the third mechanical-chemical polishing process, the protective layer 318 serves to protect the first initial dielectric layer 315, thereby improving the process window.

[0114] Please refer to Figure 26 , Figure 26 The view direction is the same Figure 8 The protective layer 318 is etched until the surface of the initial first dielectric layer 315 is exposed.

[0115] Etching the protective layer 318 includes one or a combination of dry etching and wet etching processes. In this embodiment, the etching process for the protective layer 318 is a dry etching process.

[0116] In this embodiment, the purpose of etching the protective layer 318 to remove the protective layer 318 after the third mechanochemical polishing process and before the fourth mechanochemical polishing process is to reduce the impact of the protective layer 318 on the polishing process in the fourth mechanochemical polishing process.

[0117] Please refer to Figure 27 , Figure 27 The view direction is the same Figure 8 The initial gate 321 is planarized using a fourth mechanical chemical polishing process.

[0118] The first gate 322 is formed with the gate material layer 320 on the first region I, the second gate 422 is formed with the gate material layer 320 on the second region II, and the first dielectric layer 323 is formed with the first initial dielectric layer 315.

[0119] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A first pseudo-gate structure is formed on the first region, and a second pseudo-gate structure is formed on the second region. The first pseudo-gate structure includes a first pseudo-gate, and the second pseudo-gate structure includes a second pseudo-gate. A first dielectric material layer is formed on the surface of the substrate, and the first dielectric material layer is located on the sidewalls of the first dummy gate structure and the second dummy gate structure. A second dielectric material layer is formed on the first dielectric material layer, wherein the thickness of the second dielectric material layer on the first region is less than the thickness of the second dielectric material layer on the second region. Planarize the first dielectric material layer and the second dielectric material layer until the first dummy gate and the second dummy gate are exposed, and form a first transition dielectric layer with the first dielectric material layer; The first transition dielectric layer is etched back to form a first initial dielectric layer, and the thickness of the first initial dielectric layer on the first region is lower than the thickness of the first initial dielectric layer on the second region. A protective layer is formed on the surface of the first initial dielectric layer, the protective layer being located on the sidewalls of the first dummy gate and the second dummy gate, and exposing the first dummy gate and the second dummy gate; A first gate is formed to replace the first dummy gate, and a second gate is formed to replace the second dummy gate.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for planarizing the first dielectric material layer and the second dielectric material layer includes: planarizing the second dielectric material layer using a first mechanochemical polishing process until the first dielectric material layer is exposed, wherein the polishing rate of the first mechanochemical polishing process on the second dielectric material layer is greater than the polishing rate on the first dielectric material layer; and after the first mechanochemical polishing process, planarizing the first dielectric material layer using a second mechanochemical polishing process until the first dummy gate and the second dummy gate are exposed.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric material layer includes silicon oxide; the formation process of the first dielectric material layer includes fluid chemical vapor deposition; the material of the second dielectric material layer includes silicon oxide; the formation process of the second dielectric material layer includes plasma enhanced chemical vapor deposition.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of etching back the first transition dielectric layer includes a dry etching process; the process parameters of the dry etching process include: the etching gas includes a combination of one or more gases selected from carbon tetrafluoride, hydrogen fluoride, nitrogen, argon, and trifluoromethane, the etching gas flow rate ranges from 5 sccm to 1000 sccm, and the etching power ranges from 50 watts to 1000 watts.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first dummy gate structure further includes a first dummy gate dielectric layer, which is located between the first dummy gate and the substrate; the second dummy gate structure further includes a second dummy gate dielectric layer, which is located between the second dummy gate and the substrate; the material of the protective layer is different from the materials of the first dummy gate dielectric layer and the second dummy gate dielectric layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method for the first gate and the second gate includes: removing the first dummy gate, the second dummy gate, the first dummy gate dielectric layer and the second dummy gate dielectric layer; forming a gate trench in the first initial dielectric layer and the protective layer; forming a gate material layer in the gate trench and on the surface of the protective layer; planarizing the gate material layer until the surface of the first initial dielectric layer on the first region is exposed; forming the first gate with the gate material layer on the first region; forming the second gate with the gate material layer on the second region; and forming the first dielectric layer with the first initial dielectric layer.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for planarizing the gate material layer includes: planarizing the gate material layer using a third mechanochemical polishing process until the surface of the protective layer is exposed to form an initial gate; etching the protective layer until the surface of the initial first dielectric layer is exposed; and planarizing the initial gate using a fourth mechanochemical polishing process.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first region includes an isolation region, and the method further includes: after forming the first transition dielectric layer and before etching back the first transition dielectric layer, removing the first dummy gate on the isolation region, forming an isolation opening in the first transition dielectric layer and the first dummy gate, and forming an isolation structure in the isolation opening.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the isolation opening further includes: forming a first hard mask layer on the top surfaces of the first transition dielectric layer, the first dummy gate, and the second dummy gate, wherein the first hard mask layer exposes the first dummy gate on the isolation region; and etching the first dummy gate using the first hard mask layer as a mask.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the first hard mask layer includes: forming a hard mask material layer on the top surface of the first transition dielectric layer, the first dummy gate, and the second dummy gate; and patterning the hard mask material layer to form the first hard mask layer.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the first hard mask layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the isolation structure includes: forming an insulating material layer inside the isolation opening and on the surface of the first hard mask layer; planarizing the insulating material layer and the first hard mask layer until the surfaces of the first dummy gate and the second dummy gate are exposed.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the protective layer includes: forming a protective material layer on the surface of the first initial dielectric layer, the protective material layer also being located on the top surfaces of the first dummy gate and the second dummy gate; planarizing the protective material layer until the top surfaces of the first dummy gate and the second dummy gate are exposed.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process for forming the protective material layer includes atomic layer deposition.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method for planarizing the protective material layer further includes: forming a third dielectric material layer on the surface of the protective material layer, the material of the third dielectric material layer being different from the material of the protective material layer; planarizing the third dielectric material layer using a fifth mechanochemical polishing process until the surface of the protective material layer is exposed; and after the fifth mechanochemical polishing process, etching back the protective material layer until the top surfaces of the first dummy gate and the second dummy gate are exposed.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The material of the third dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride; the material of the second dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the first dielectric material layer, an etch stop layer is also formed on the surface of the substrate, the first dummy gate structure, and the second dummy gate structure.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the protective layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

20. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first initial dielectric layer on the first region has a first thickness value, and the first initial dielectric layer on the second region has a second thickness value, wherein the first thickness value is lower than the second thickness value by a range of 5 nanometers to 15 nanometers.

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