Clamping circuit and electronic device

Abstract

This disclosure provides a clamping circuit and an electronic device. The clamping circuit generates a supply voltage for a load module based on the positive and negative power supply voltages applied to a power transistor. The clamping circuit adjusts the potential of the output node in its conduction path under the control of a first control voltage according to the input current, thereby clamping the output range of the supply voltage within the operating range of the load module. This simple circuit design maintains the low-voltage potential of the supply voltage above the substrate bias potential of the power transistor in the low-voltage range of the negative power supply voltage, thus avoiding negative voltage. This effectively saves costs while meeting application requirements and prevents chip damage caused by an excessively large operating range of the supply voltage.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to a clamping circuit and an electronic device. Background Technology

[0002] In the prior art, some devices can utilize a clamping circuit to "clamp" the power supply voltage in response to the power supply voltage exceeding a trigger voltage level, thereby maintaining the power supply voltage within a specific operating range. For example, such as Figure 1 The circuit diagram shown is used to provide the power supply voltage for the load module. VDD and VEE are the positive and negative power supply voltages of the system, respectively. When VDD = 3V and VEE = -4V, VDD - VEE = 7V, meaning there is a 7V voltage difference between the positive and negative power supplies. In some applications, for low-voltage devices in the load module, the voltage difference between the positive and negative power supplies should be less than 5V. Therefore, an internal power supply voltage SUB_VDD needs to be generated to ensure that its voltage difference with VEE is less than 5V, in order to power the load module connected to VEE. Figure 1 The circuit shown operates under the following principle: the supply voltage is:

[0003] VSUB_VDD=VEE+VR1-VGS=VEE+IB*R1-VGS=VS-VGS (1)

[0004] Where VR1 is the voltage drop across resistor R1, VGS is the gate-source voltage of power MOSFET MN1, IB is the current supplied by current source Ib, and VS is the potential of node S. The curve showing the change of the supply voltage SUB_VDD with VEE is as follows. Figure 2 As shown. If IB*R1 is set to 5V and VGS to 0.8V, when VEE is low, for example -5V, then VSUB_VDD = -5 + 5 - 0.8 = -0.8V < 0. Since SUB_VDD is the power supply for the load module, it must be connected to the N-type injected active region, such as the N-well layer, of the power MOSFET MN1. And the chip ( Figure 1 The circuit shown below has a P-type substrate with a potential of 0V. The difference between the substrate bias potential VPSUB and the N-well layer potential VNWELL is greater than 0. At this time, the parasitic diode PN is turned on, which causes the parasitic NPN transistor inside the chip to have a latch-up effect, resulting in the chip burning out.

[0005] Existing solutions to the above problems include: one is to limit the minimum voltage range of VEE, but this directly limits the application range of the circuit; the other is to replace the load module connected to VEE with a high-voltage device, but the cost of using high-voltage devices is high, and the isolation ring of high-voltage devices increases the design complexity and reduces the reliability of the system. Summary of the Invention

[0006] To address the aforementioned technical problems, this disclosure provides a clamping circuit and an electronic device.

[0007] On one hand, this disclosure provides a clamping circuit for generating a supply voltage for a load module based on a power transistor connected to a positive or negative power supply voltage. The clamping circuit has a first input terminal for receiving an input current and a second input terminal for receiving a first control voltage, as well as an output node for providing the drive voltage for the power transistor.

[0008] The clamping circuit is used to adjust the potential of the output node in its conduction path under the control of the first control voltage according to the aforementioned input current, so as to clamp the output range of the power supply voltage within the working range of the load module.

[0009] Preferably, the aforementioned clamping circuit includes:

[0010] A first current source, a first transistor, and a first resistor are provided. The first current source is used to provide the aforementioned input current. The first current source is connected in series with the first transistor and the first resistor to the negative power supply terminal. The connection node between the first current source and the first transistor serves as the aforementioned output node to provide the driving voltage.

[0011] Preferably, the control terminal of the aforementioned power transistor is connected to the output node, the first terminal of the power transistor is connected to the positive power supply terminal and connected to the positive power supply voltage, the second terminal is connected to the first terminal of the load module to provide the aforementioned power supply voltage, and the second terminal of the load module is connected to the negative power supply terminal and connected to the negative power supply voltage.

[0012] Preferably, the aforementioned power transistor is an N-channel metal-oxide-semiconductor field-effect transistor, and the aforementioned first transistor is a P-channel metal-oxide-semiconductor field-effect transistor.

[0013] Preferably, the aforementioned first control voltage controls the first transistor to be in the on state, the clamping circuit forms a first connection path from the first current source to the load module, and the supply voltage is:

[0014] VSUB_VDD=VEE+IB*R1+VDS1-VGS2 (2)

[0015] Wherein, VSUB_VDD represents the supply voltage, VEE is the negative supply voltage, IB represents the input current, R1 represents the first resistor, VDS1 represents the source-drain voltage of the first transistor, and VGS2 represents the gate-source voltage of the power transistor.

[0016] Preferably, the aforementioned first control voltage controls the first transistor to be in the on state, the clamping circuit forms a second connection path from the first resistor to the load module, and the supply voltage is:

[0017] VSUB_VDD=VG+VGS1-VGS2=VS-VGS2 (3)

[0018] Wherein, VSUB_VDD represents the supply voltage, VG represents the first control voltage, VGS1 represents the gate-source voltage of the first transistor, VS represents the potential of the aforementioned output node, i.e., the aforementioned driving voltage, and VGS2 represents the gate-source voltage of the power transistor.

[0019] Preferably, the aforementioned clamping circuit clamps and controls the low-voltage potential of the power supply voltage above the substrate bias potential of the power transistor in the low-voltage range of the negative power supply voltage, so as to maintain the power supply voltage as constant positive throughout the entire operating phase.

[0020] On the other hand, this disclosure also provides an electronic device, which includes:

[0021] The clamping circuit described above has a first input terminal for receiving input current and a second input terminal for receiving a first control voltage, as well as an output node for providing drive voltage.

[0022] A power transistor and a load module are connected in series between the positive and negative power supply terminals, and the control terminal of the power transistor is connected to the aforementioned output node.

[0023] The clamping circuit is used to adjust the potential of the output node in its conduction path under the control of the first control voltage according to the input current, so as to clamp the output range of the power supply voltage within the working range of the load module.

[0024] The beneficial effects of this disclosure are as follows: This disclosure provides a clamping circuit and electronic device. The clamping circuit generates a supply voltage for a load module based on the positive and negative power supply voltages of the power transistor. The clamping circuit adjusts the potential of the output node in its conduction path under the control of a first control voltage according to the input current, thereby clamping the output range of the supply voltage within the operating range of the load module. Through simple circuit design, the low-voltage potential of the supply voltage is maintained above the substrate bias potential of the power transistor in the low-voltage range of the negative power supply voltage, thus avoiding negative voltage. This effectively saves costs while meeting application requirements and prevents chip damage caused by an excessively large operating range of the supply voltage. Attached Figure Description

[0025] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings.

[0026] Figure 1 This diagram illustrates a prior art circuit for providing power supply voltage to a load module.

[0027] Figure 2 Show Figure 1 A schematic diagram of the waveform of the supply voltage changing with the negative power supply voltage in the circuit shown.

[0028] Figure 3 This diagram illustrates the structure of a clamping circuit for providing power supply voltage to a load module, as provided in an embodiment of this disclosure.

[0029] Figure 4 Show Figure 3 The diagram shows the waveform of the supply voltage changing with the negative power supply voltage in the clamping circuit. Detailed Implementation

[0030] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the contents of this disclosure.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0032] The present disclosure will now be described in detail with reference to the accompanying drawings.

[0033] Figure 3 This diagram illustrates the structure of a clamping circuit for providing power supply voltage to a load module, as provided in an embodiment of this disclosure. Figure 4 Show Figure 3 The diagram shows the waveform of the supply voltage changing with the negative power supply voltage in the clamping circuit.

[0034] refer to Figure 3 On one hand, this disclosure provides a clamping circuit 100, which is used to generate the internal supply voltage VSUB_VDD of the load module 110 based on the positive and negative power supply voltages (VDD & VEE) connected to the power transistor MN1. The clamping circuit 100 has a first input terminal connected to the input current IB and a second input terminal connected to the first control voltage VG, as well as an output node S providing the drive voltage VS for the power transistor MN1.

[0035] The clamping circuit 100 is used to adjust the potential VS of the output node S in its conduction path under the control of the first control voltage VG according to the aforementioned input current IB, so as to clamp the output range of the power supply voltage VSUB_VDD within the working range of the load module 110.

[0036] Furthermore, in this embodiment, reference is made to... Figure 3 The aforementioned clamping circuit 100 includes:

[0037] The first current source Ib, the first transistor MP1, and the first resistor R1 are used to provide the aforementioned input current IB. The first current source Ib is connected in series with the first transistor MP1 and the first resistor R1 to the negative power supply terminal. The connection node between the first current source Ib and the first transistor MP1 serves as the aforementioned output node S, which is used to provide the driving voltage VS (which is also the potential of the output node S in the following text).

[0038] Furthermore, in this embodiment, the control terminal of the aforementioned power transistor MN1 is connected to the aforementioned output node S. The first terminal of the power transistor MN1 is connected to the positive power supply terminal and connected to the positive power supply voltage VDD. The second terminal is connected to the first terminal of the load module 110 to provide the aforementioned power supply voltage VSUB_VDD. The second terminal of the load module 110 is connected to the negative power supply terminal and connected to the negative power supply voltage VEE.

[0039] Furthermore, in this embodiment, the aforementioned power transistor MN1 is an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as MOS transistor), and the aforementioned first transistor MP1 is a P-channel MOS transistor.

[0040] Furthermore, in this embodiment, the supply voltage VSUB_VDD is determined by two branches. Specifically, the aforementioned first control voltage VG controls the first transistor MP1 to be in the on state, and the clamping circuit 100 forms a first connection path from the first current source Ib to the load module 110, such as... Figure 3 As shown, the supply voltage VSUB_VDD is:

[0041] VSUB_VDD=VEE+IB*R1+VDS1-VGS2 (2)

[0042] Wherein, VSUB_VDD represents the supply voltage, VEE is the negative supply voltage, IB represents the input current, R1 represents the first resistor, VDS1 represents the source-drain voltage of the first transistor MP1, and VGS2 represents the gate-source voltage of the power transistor MN1.

[0043] The aforementioned first control voltage VG controls the first transistor MP1 to be in the on state, the clamping circuit 100 forms a second connection path from the first resistor R1 to the load module 110, and the supply voltage VSUB_VDD is:

[0044] VSUB_VDD=VG+VGS1-VGS2=VS-VGS2 (3)

[0045] Wherein, VSUB_VDD represents the supply voltage, VG represents the first control voltage, VGS1 represents the gate-source voltage of the first transistor MP1, VS represents the potential of the aforementioned output node S, i.e. the aforementioned driving voltage, and VGS2 represents the gate-source voltage of the power transistor MN1.

[0046] In this embodiment, the voltage drop VR1 across the first resistor R1 is set to be IB*R1 = 5V, and VGS2 = 0.8V. The gate-source voltage VGS1 and source-drain voltage VDS1 of the first transistor MP1 will adaptively adjust according to the negative power supply voltage VEE and the first control voltage VG. Furthermore, by designing the width-to-length ratio (W / L) of the first transistor MP1 and the power transistor MN1, even when the negative power supply voltage VEE is low and the gate-source voltage VGS1 of the first transistor MP1 is at its minimum, VGS1 still > VGS2. The curve of the supply voltage VSUB_VDD changing with the negative power supply voltage VEE is shown below. Figure 4 As shown.

[0047] The following example uses specific data to illustrate this:

[0048] 1) When the negative power supply voltage VEE is high, for example, -2V,

[0049] According to formula (2), VSUB_VDD=-2+5+0.2-0.8=2.4V.

[0050] At this point, for formula (3), VSUB_VDD = 0 + 3.2 - 0.8 = 2.4V, where VGS1 = 3.2V.

[0051] 2) When the negative power supply voltage VEE is low, for example -5V,

[0052] According to formula (3), VSUB_VDD=0+1-0.8=0.2V.

[0053] At this point, for formula (2), VSUB_VDD=-5+5+1-0.8=0.2V>0V, where VGS1=1V.

[0054] According to the above analysis, when the negative power supply voltage VEE is high, the supply voltage VSUB_VDD is also high and far from 0V; when the negative power supply voltage VEE gradually decreases, the supply voltage VSUB_VDD also decreases accordingly, but is not limited by formula (3); when the negative power supply voltage VEE is low to a certain extent, even if the driving voltage VS is close to the minimum value of the gate-source voltage VGS1 of the first transistor MP1, and the supply voltage VSUB_VDD is close to 0V, the potential of the supply voltage VSUB_VDD is maintained at a positive voltage through the second connection path corresponding to formula (3), thereby avoiding the negative voltage of the supply voltage VSUB_VDD during its entire working stage.

[0055] Furthermore, in this embodiment, the aforementioned clamping circuit clamps and controls the low-voltage potential of the power supply voltage above the substrate bias potential of the power transistor in the low-voltage range of the negative power supply voltage, so as to maintain the power supply voltage as constant positive throughout the entire operation phase. Specifically, in this embodiment, by designing the parameters of the clamping circuit 100, the VGS of the first transistor MP1 is greater than the VGS of the power transistor MN1, i.e., VGS1>VGS2, and the first transistor applies a bias voltage GND (i.e., 0V) to the control terminal of MP1, so that the power supply voltage VSUB_VDD>0=VPSUB (substrate bias potential of power transistor MN1), thereby avoiding the conduction of the parasitic diode PN of the system (power transistor MN1), avoiding the occurrence of latch-up effect, effectively saving costs while meeting the application requirements of the load module 110, and at the same time avoiding damage to the chip (the integrated circuit of the load module 110) due to the excessively large operating range of the power supply voltage VSUB_VDD.

[0056] On the other hand, this disclosure also provides an electronic device 200, such as Figure 3 As shown, it includes:

[0057] The clamping circuit 100 described above has a first input terminal connected to the input current IB and a second input terminal connected to the first control voltage VG, as well as an output node S that provides the drive voltage VS.

[0058] The power transistor MN1 and the load module 110 are connected in series between the positive and negative power supply terminals, and the control terminal of the power transistor MN1 is connected to the aforementioned output node S.

[0059] The clamping circuit 100 is used to adjust the potential VS of the output node S in its conduction path under the control of the first control voltage VG according to the input current IB, so as to clamp the output range of the power supply voltage VSUB_VDD within the working range of the load module 110.

[0060] In summary, the clamping circuit 100 and electronic device 200 provided in this disclosure generate a supply voltage VSUB_VDD within the load module 110 based on the positive and negative power supply voltages (VDD & VEE) of the power transistor MN1. The clamping circuit 110 adjusts the potential VS of the output node S in its conduction path under the control of the first control voltage VG according to the input current IB, thereby clamping the output range of the supply voltage VSUB_VDD within the operating range of the low-voltage devices in the load module 100. This simple circuit design maintains the low-voltage potential of the supply voltage VSUB_VDD above the substrate bias potential VPSUB of the power transistor MN1 within the low-voltage range of the negative power supply voltage VEE, thus preventing negative voltage VSUB_VDD. This effectively saves costs while meeting application requirements and avoids chip damage caused by an excessively large operating range of the supply voltage VSUB_VDD.

[0061] In the above embodiments, the power transistor MN1 and the transistor MP1 are, for example, MOS transistors. In this embodiment, the "control terminal", "first terminal", and "second terminal" are, for example, the "gate", "source", and "drain" of a field-effect transistor.

[0062] It should be understood that the transistors in the above embodiments are implemented using field-effect transistors, but this invention is not limited thereto. In other embodiments of this invention, the transistors in the above embodiments can be implemented using bipolar transistors, where the "control terminal," "first terminal," and "second terminal" in the embodiments are respectively the "base," "emitter," and "collector" of the bipolar transistor.

[0063] It should be noted that, in the description of this disclosure, the terms "upper," "lower," "inner," etc., which indicate orientation or positional relationship, are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0064] Furthermore, throughout this document, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0065] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this disclosure and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of this disclosure.

Claims

1. A clamping circuit for generating a supply voltage for a load module based on a power transistor connected to a positive or negative power supply voltage, characterized in that, The clamping circuit has a first input terminal for receiving the input current and a second input terminal for receiving the first control voltage, as well as an output node for providing the drive voltage for the power transistor. The clamping circuit is used to adjust the potential of the output node in its conduction path under the control of the first control voltage according to the input current, so as to clamp the output range of the power supply voltage within the working range of the load module. The control terminal of the power transistor is connected to the output node. The first terminal of the power transistor is connected to the positive power supply terminal and is connected to the positive power supply voltage. The second terminal is connected to the first terminal of the load module to provide the power supply voltage. The second terminal of the load module is connected to the negative power supply terminal and is connected to the negative power supply voltage. The clamping circuit includes: A first current source, a first transistor, and a first resistor are provided. The first current source is used to provide the input current, and the first current source is connected in series with the first transistor and the first resistor to the negative power supply terminal. The connection node between the first current source and the first transistor serves as the output node to provide the driving voltage.

2. The clamp circuit of claim 1, wherein, The power transistor is an N-channel metal-oxide-semiconductor field-effect transistor, and the first transistor is a P-channel metal-oxide-semiconductor field-effect transistor.

3. The clamp circuit of claim 1, wherein, The first control voltage controls the first transistor to be in the on state, the clamping circuit forms a first connection path from the first current source to the load module, and the supply voltage is: VSUB_VDD=VEE+IB*R1+VDS1-VGS2 (2) Wherein, VSUB_VDD represents the power supply voltage, VEE is the negative power supply voltage, IB represents the input current, R1 represents the first resistor, VDS1 represents the source-drain voltage of the first transistor, and VGS2 represents the gate-source voltage of the power transistor.

4. The clamp circuit of claim 3, wherein, The first control voltage controls the first transistor to be in the on state, the clamping circuit forms a second connection path from the first resistor to the load module, and the supply voltage is: VSUB_VDD=VG+VGS1-VGS2=VS-VGS2 (3) Wherein, VSUB_VDD represents the power supply voltage, VG represents the first control voltage, VGS1 represents the gate-source voltage of the first transistor, VS represents the potential of the output node, and VGS2 represents the gate-source voltage of the power transistor.

5. The clamping circuit according to claim 4, characterized in that, The clamping circuit clamps and controls the low-voltage potential of the power supply voltage above the substrate bias potential of the power transistor in the low-voltage range of the negative power supply voltage, so as to maintain the power supply voltage as constant positive throughout the entire operation phase.

6. An electronic device, comprising: include: The clamping circuit as described in any one of claims 1 to 5, the clamping circuit having a first input terminal for receiving input current and a second input terminal for receiving a first control voltage, and an output node for providing a drive voltage; A power transistor and a load module are connected in series between the positive and negative power supply terminals, and the control terminal of the power transistor is connected to the output node. The clamping circuit is used to adjust the potential of the output node in its conduction path under the control of the first control voltage according to the input current, so as to clamp the output range of the power supply voltage within the working range of the load module.

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