A frequency detection method and system

Abstract

The present disclosure relates to the technical field of frequency detection, and proposes a frequency detection method and system. The method comprises: converting an acquired to-be-detected signal into a pulse form of a detected signal; acquiring a plurality of high-frequency clock signals with a set phase difference; performing frequency division processing on the high-frequency clock signals to convert them into a reference clock signal; using a serial-parallel conversion method to detect the time instants of two rising edges or falling edges of adjacent periods of the detected signal and output corresponding multi-bit parallel detection values; merging the multi-bit parallel detection values output after detection using the serial-parallel conversion method of the plurality of high-frequency clock signals according to phase relationships to obtain combined parallel detection values, and calculating the frequency value of the detected signal. The present disclosure uses a serial-parallel conversion method to fuse phase-shift detection, and realizes more accurate identification of the position of a rising edge in the case that the to-be-detected signal and the reference signal are not aligned, thereby improving the detection accuracy of the frequency.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of frequency detection, and in particular, to a frequency detection method and system. BACKGROUND

[0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute the prior art.

[0003] Frequency is an important physical quantity that needs to be detected in engineering practice. With the increasing complexity and precision requirements of control systems, higher precision requirements are also put forward for frequency measurement. There are two commonly used frequency measurement methods, M method and T method. The M method specifies a reference clock for generating a given time interval, measures the number of pulses of the to-be-measured signal in the given time, and obtains the frequency of the measured signal by the quotient of the number of pulses and the given time. The T method also specifies a reference clock, measures the period of the pulse signal using the reference clock, and then calculates the reciprocal of the period to obtain the frequency of the measured signal.

[0004] The inventors found in the research that the M method and the T method have inherent problems. When the frequency of the to-be-measured signal is not an integer multiple of the reference clock, or when the rising edge of the to-be-measured signal is not aligned with the rising edge of the reference clock, the frequency measurement accuracy of the to-be-measured signal cannot meet the requirements.

[0005] With the development of measurement technology and digital signal processing theory, FFT frequency measurement method, vernier method, analog interpolation method, etc. have appeared. FFT calculation can realize the conversion of the measured signal from time domain to frequency domain, thereby obtaining frequency, phase and other information. However, the FFT frequency measurement method has the disadvantages of complex algorithm and large amount of calculation; the vernier method and the analog interpolation method improve the measurement accuracy at the starting sampling point and the ending sampling point, thereby improving the frequency measurement accuracy. However, the instruments implementing these two methods are expensive and have low cost performance. SUMMARY

[0006] In order to solve the above problems, the present disclosure provides a frequency detection method and system, which greatly improves the detection accuracy of the to-be-measured signal based on phase shift detection and serial-parallel conversion for the case that the to-be-measured signal and the reference signal are not aligned.

[0007] In order to achieve the above purpose, the present disclosure adopts the following technical solutions:

[0008] One or more embodiments provide a frequency detection method, comprising the following steps:

[0009] Converting the obtained to-be-measured signal into a pulse form of the measured signal;

[0010] Obtaining a plurality of high-frequency clock signals with a set phase difference;

[0011] The high-frequency clock signal is frequency-division processed to be converted into a reference clock signal;

[0012] The adjacent period two rising edge moments or falling edge moments of the measured signal are detected by using a serial-parallel conversion method, and corresponding multi-bit parallel detection values are outputted;

[0013] The multi-bit parallel detection values outputted after detection by using the serial-parallel conversion method of the multi-path high-frequency clock signal are merged according to phase relations to obtain combined parallel detection values, and the frequency value of the measured signal is calculated.

[0014] One or more embodiments provide a frequency detection system, comprising a signal collector and a processor;

[0015] The signal collector is used for collecting a measured signal;

[0016] The processor is configured to execute the above frequency detection method.

[0017] One or more embodiments provide a frequency detection system, comprising:

[0018] A high-speed comparison unit configured to convert the acquired measured signal into a pulse form;

[0019] A PLL module configured to acquire a multi-path high-frequency clock signal with a set phase difference;

[0020] A frequency-division module configured to frequency-division process the high-frequency clock signal to be converted into a reference clock signal;

[0021] A serial-parallel conversion module configured to detect the adjacent period two rising edge moments or falling edge moments of the measured signal by using a serial-parallel conversion method, and output corresponding multi-bit parallel detection values;

[0022] A phase shift data merging module configured to merge the multi-bit parallel detection values outputted after detection by using the serial-parallel conversion method of the multi-path high-frequency clock signal according to phase relations to obtain combined parallel detection values;

[0023] A calculation unit configured to calculate the frequency value of the measured signal according to the combined parallel detection values.

[0024] An electronic device comprising a memory and a processor, and computer instructions stored in the memory and running on the processor, when the computer instructions are run by the processor, the steps of the above method are completed.

[0025] A computer readable storage medium for storing computer instructions, when the computer instructions are executed by a processor, the steps of the above method are completed.

[0026] Compared with the prior art, the present disclosure has the following advantages:

[0027] The present disclosure converts the detection of frequency into a digital signal by using a serial-parallel conversion method, and the frequency of the measured signal can be recognized by counting the digital signal, thereby improving the detection accuracy. Meanwhile, for the case that the rising edge of the measured signal is not aligned with the reference signal, the rising edge position can be more accurately recognized by using a high-frequency clock signal with multiple phase shift angles, thereby improving the detection accuracy of the frequency.

[0028] Compared with the traditional M method or T method for measuring frequency, the frequency of the measured signal can be improved by at least 16 times in accuracy by using the phase shift serial-parallel conversion idea for measuring the frequency of the signal; compared with the FFT frequency measurement method, the algorithm complexity is reduced, which is conducive to software programming implementation and engineering application; compared with the vernier method and the interpolation method, the complexity of the device is greatly reduced, and the cost is reduced.

[0029] The advantages of the present disclosure and the advantages of additional aspects will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0030] The drawings accompanying the specification of the present disclosure serve to provide a further understanding of the present disclosure, and the illustrative embodiments of the present disclosure and their descriptions serve to explain the present disclosure, and do not constitute a limitation of the present disclosure.

[0031] Figure 1 Schematic diagram of M method for measuring frequency in ideal case;

[0032] Figure 2 Schematic diagram of T method for measuring frequency in ideal case;

[0033] Figure 3 Schematic diagram of M method for measuring frequency in actual case;

[0034] Figure 4 Schematic diagram of T method for measuring frequency in actual case;

[0035] Figure 5 Schematic diagram of serial-parallel conversion module of embodiment 1 of the present disclosure;

[0036] Figure 6 Schematic diagram of serial-parallel conversion method of embodiment 1 of the present disclosure;

[0037] Figure 7 Schematic diagram of frequency measurement by using serial-parallel conversion method of embodiment 1 of the present disclosure;

[0038] Figure 8 Schematic diagram of frequency measurement by using serial-parallel conversion method of embodiment 1 of the present disclosure when the measured signal is not aligned with the high-speed clock signal;

[0039] Figure 9Figure 1 is a schematic diagram of a phase-shifted serial-parallel conversion method using multiple high-speed clock signals for the embodiment 1 of the present disclosure.

[0040] Figure 10 Figure 2 is a schematic diagram of a data merging method for the phase-shifted serial-parallel conversion for the embodiment 1 of the present disclosure.

[0041] Figure 11 Figure 3 is a system block diagram for measuring the frequency of the phase-shifted serial-parallel conversion method for the embodiment 2 of the present disclosure. DETAILED DESCRIPTION

[0042] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0043] It should be noted that the following detailed description is exemplary in nature and is intended to provide further description of the present disclosure. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0044] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. It will be noted that various embodiments and implementations of the present disclosure can be combined with each other, provided there is no conflict. The embodiments will be described in detail below with reference to the accompanying drawings.

[0045] As described in the background section, the M method and the T method cannot meet the demand of the frequency measurement accuracy of the to-be-measured signal in some application scenarios.

[0046] Figure 1 Figure 4 is a schematic diagram of detecting the frequency of the to-be-measured signal using the M method. The period of the reference clock is T SCLK , which is used as a reference clock to calculate a given time value, such as a given time T C . The reference clock is M C =M*T SCLK . The number of pulse changes of the to-be-measured signal is counted within the given time, and it is assumed that the number of pulse changes is N. According to the above information, the frequency f of the to-be-measured signal can be calculated as f=N / T C =N / (M*T SCLK ).

[0047] Figure 2 Figure 5 is a schematic diagram of detecting the frequency of the to-be-measured signal using the T method. The period of the reference clock is T SCLK , which is used as a reference clock to measure the period value T P, for example, the period of the signal to be measured is M times the reference clock, T P =M*T SCLK . According to the relationship between the frequency and the period, the frequency f of the signal to be measured can be calculated, f = 1 / T P =1 / (M*T SCLK ).

[0048] However, the above measurement methods are all for detecting the frequency of the signal to be measured under ideal conditions. The ideal conditions refer to that the frequency of the signal to be measured is an integer multiple of the reference clock, and the rising edge of the signal to be measured is aligned with the rising edge of the reference clock. However, in actual conditions, the signal to be measured is difficult to meet the above requirements.

[0049] Figure 3 FIG. 1 is a schematic diagram of the M method for detecting the frequency of the signal to be measured under actual conditions. At the start time and the end time of the given time, the rising edge of the signal to be measured is not aligned with the rising edge of the reference clock. Within the given time, the time interval between the start time and the first rising edge of the signal to be measured is defined as t1, and the time interval between the end time and the last rising edge of the signal to be measured is defined as t2. Therefore, within the given time, the actual time T C_r of the signal to be measured can be represented as T C_r =N*T P +t1-t2, and the period measurement error Ess = |t1-t2| / T P . The measurement accuracy is related to the frequency of the signal to be measured. The higher the frequency, the higher the accuracy of the signal to be measured. When the frequency of the signal to be measured is much smaller than the reference clock, the measurement error of the M method is large.

[0050] Figure 4 FIG. 2 is a schematic diagram of the T method for detecting the frequency of the signal to be measured under actual conditions. The rising edges of the adjacent two periods of the signal to be measured are not aligned with the rising edge of the reference clock. The time interval between the rising edge of the first period of the signal to be measured and the rising edge of the reference clock is defined as t3, and the time interval between the rising edge of the second period of the signal to be measured and the rising edge of the reference clock is defined as t4. Therefore, the actual time T P_r of one period of the signal to be measured can be represented as T P_r =TP+t3-t4, and the frequency measurement error ESS = |t3-t4| / T SCLK ≤ 1.

[0051] In this embodiment, for the case that the rising edge of the signal to be measured is not aligned with the reference clock, the frequency detection of the signal to be measured is performed by using the serial-parallel conversion method, which can improve the frequency measurement accuracy of the signal to be measured by at least 16 times. The following specific embodiments are described.

[0052] Embodiment 1

[0053] In one or more embodiments of the technical solutions disclosed, for example, Figures 1 to 10As shown, a frequency detection method comprises the following steps:

[0054] Step 1, converting the acquired to-be-detected signal into a pulse form of the measured signal;

[0055] Step 2, acquiring a plurality of high-frequency clock signals with a set phase difference;

[0056] Optionally, the product of the phase shift angle of the plurality of high-frequency clock signals and the number of high-frequency clock signals is equal to 360°.

[0057] Step 3, performing frequency division processing on the high-frequency clock signals to convert them into reference clock signals;

[0058] Step 4, detecting the time instants of the adjacent rising edges or falling edges of the measured signal by using a serial-parallel conversion method and outputting corresponding multi-bit parallel detection values;

[0059] Step 5, merging the multi-bit parallel detection values output by the serial-parallel conversion method using the plurality of high-frequency clock signals according to the phase relationship to obtain combined parallel detection values, and calculating the frequency value of the measured signal according to the obtained parallel detection values.

[0060] In this embodiment, the serial-parallel conversion method is used to convert the detection of the frequency into a digital signal, and the frequency of the measured signal can be recognized by counting the digital signal, thereby improving the detection accuracy. Meanwhile, for the case that the rising edge of the measured signal is not aligned with the reference signal, the rising edge position can be more accurately recognized by using the plurality of high-frequency clock signals with a set phase shift angle, thereby improving the detection accuracy of the frequency.

[0061] In Step 1, the to-be-detected signal is converted into a pulse form by comparing the to-be-detected signal with a set signal, in which a value greater than a set value is a high level and a value less than the set value is a low level.

[0062] In Step 3, the frequency division number can be self-set, such as two frequency division, four frequency division, eight frequency division, and theoretically can be any frequency division number. In this embodiment, four frequency division is preferably used for illustration.

[0063] After frequency division, the period of the reference clock signal is an integer multiple of the period of the high-speed clock signal. In one reference clock, the measured signal is processed by the high-speed clock signal to obtain a group of parallel output values with corresponding bit numbers. Meanwhile, the reference clock can be used to quickly measure the number of reference clocks in a single period of the measured signal, thereby realizing fast counting.

[0064] In Step 4, the serial-parallel conversion can be realized by using a general IP core in the FPGA or a dedicated serial-parallel conversion chip. According to the detection accuracy and cost control requirements, different speed grades of FPGA or conversion chips are selected to meet the actual engineering requirements.

[0065] As Figure 5 As shown, the serial-parallel conversion can be implemented by a serial-parallel conversion module, D represents the signal to be measured, SCLK represents a reference clock, ECLK represents a high-speed clock, and Q1 to Q8 represent parallel output results. To implement the serial-parallel conversion idea, a special chip can be used, or an IP core in an FPGA can be borrowed.

[0066] In some embodiments, the serial-parallel conversion method specifically comprises: aligning a reference clock signal with a high-frequency clock signal, detecting the signal to be measured using the high-frequency clock signal, the rising edge or the falling edge of the high-frequency clock signal corresponding to the high level of the signal to be measured outputting a value A, and the low level outputting a value B; detecting the signal to be measured for one or more periods, and outputting corresponding multi-bit parallel detection values.

[0067] Optionally, the rising edge or the falling edge of the signal to be measured can be positionally detected using the high-speed clock signal, and the value output at the rising edge or the falling edge jumps;

[0068] Specifically, the high level output value A corresponds to the low level output value B, wherein the values of A and B can be self-set, preferably, the high level output value A = 1, and the low level output value B = 0. The rising edge of the signal to be measured can be detected by the high-speed clock signal, and can change from 0 to 1; similarly, the falling edge, the output value can change from 1 to 0.

[0069] As Figure 6 As shown, it is a schematic diagram of the serial-parallel conversion method, the rising edge and the falling edge of the high-speed clock ECLK are sampled on the signal to be measured, after 8 times of sampling in one reference clock period, the sampling results are output from the output pins (Q1 to Q8). When all the 8-bit output results are 0, it indicates that the signal to be measured is in a low level state; when all the 8-bit output results are 1, it indicates that the signal to be measured is in a high level state; when the 8-bit output results change from 0 to 1, it indicates that the signal to be measured changes from a low level to a high level; when the 8-bit output results change from 1 to 0, it indicates that the signal to be measured changes from a high level to a low level.

[0070] Step 4, according to the number of reference clocks between the two rising edges or the two falling edges of the signal to be measured and the number of high-speed clock signals, the frequency of the signal to be measured is calculated. That is, after obtaining the multi-bit parallel detection values containing 0 and 1 in this embodiment, the frequency of the signal to be measured is calculated by counting the number of 0 and 1.

[0071] As Figure 7This diagram illustrates frequency measurement using the serial-to-parallel conversion method, taking the detection of two rising edges of the signal under test as one signal period as an example. At time A, the output of the serial-to-parallel conversion module (SERDES module) changes from 0 to 1, indicating that a rising edge event occurred in the signal under test within the previous reference period TSCLK. The output is recorded, and the number of 1s is counted as n1. Simultaneously, the reference clock count begins. At time B, the output of the SERDES module changes from 0 to 1, indicating that a second rising edge event occurred in the signal under test within the previous reference period TSCLK. The output of the SERDES module is recorded, and the number of 0s is counted as n2. The reference clock count stops, and the current count value is recorded as m. Based on this information, the period T of the signal under test is calculated. P The value is T P =(n1+n2)*T ECLK +(m-2)*T SCLK .

[0072] Figure 7 When the rising edge of the signal under test is aligned with the rising edge of the high-speed clock signal, the same principle applies. However, when the rising edge of the high-speed clock signal is not aligned with the signal under test, there will still be a frequency detection error even with a high-speed clock signal and a reference clock signal.

[0073] like Figure 8 The diagram illustrates a real-world frequency measurement method using serial-to-parallel conversion. The rising edges of two adjacent cycles of the signal under test are not aligned with either the rising or falling edge of the high-speed clock ECLK. The time interval between the first rising edge of the signal under test and the edge of the high-speed clock is defined as t5, and the time interval between the second rising edge of the signal under test and the edge of the high-speed clock is defined as t6. Therefore, the actual time T of one cycle of the signal under test is... P_r It can be represented as T P_r =T P +t5-t6, Frequency measurement error ESS=|t5-t6| / T SCLK ≤ 1 / 8. Even though high-speed clock signals are high-frequency signals, there is still a certain degree of error.

[0074] A further technical solution involves using multiple high-frequency clock signals for detection, and finally splicing the detection results based on the phase relationship of the high-frequency clock signals, thereby further reducing the frequency detection error of the signal under test.

[0075] To further improve the accuracy of frequency measurement, a phase-shifting series-parallel conversion method is proposed based on the series-parallel conversion method for frequency measurement. A specific example is shown below. Figures 9 to 10 As shown.

[0076] Optionally, the method for data merging of the output results of the multi-path serial-parallel conversion module: taking the rising edge position time or the falling edge position time as the reference time, aligning the output results of the serial-parallel conversion corresponding to the multi-path high-speed clock signals, and combining the aligned output results according to the high and low bits of the data.

[0077] In the combination according to the high and low bits of the data, the output results are combined according to the time sequence of the detection sampling of the multi-path high-speed clock signals. For example, Figure 10 In the combination according to the high and low bits of the data, the output results are combined according to the time sequence of the detection sampling of the multi-path high-speed clock signals. For example,

[0078] In this embodiment, specifically: in the multi-path high-speed clock signals with a set phase difference, taking the output result of the serial-parallel conversion corresponding to the high-speed clock with the last phase as the reference, the output results corresponding to the remaining high-speed clocks are shifted and adjusted, so that all the output results are aligned according to the rising edge position time or the falling edge position time as the reference time; the aligned and adjusted results are combined according to the high and low bits of the data to obtain the combined parallel detection values.

[0079] In some embodiments, in step 2, the PLL module in the FPGA is used to generate multi-path high-speed clock signals with a fixed phase difference, such as ECLK1, ECLK2, ECLK3, …, ECLKn, etc.

[0080] In step 3, the frequency division module can be used to divide the high-speed clock signals to obtain corresponding reference clock signals SCLK1, SCLK2, SCLK3, …, SCLKn, etc.

[0081] Figure 9 In the combination according to the high and low bits of the data, the output results are combined according to the time sequence of the detection sampling of the multi-path high-speed clock signals. For example, Figure 9 For the case of a phase difference of 120°, the phase- shifted serial-parallel conversion method is shown in the figure, that is, ECLK2 lags ECLK1 by 120°, and ECLK3 lags ECLK2 by 120°.

[0082] Figure 9 In the combination according to the high and low bits of the data, the output results are combined according to the time sequence of the detection sampling of the multi-path high-speed clock signals. For example, Figure 10As shown, it is a schematic diagram of the phase-shifted serial-parallel conversion result data merging method. Since ECLK3 lags behind ECLK1 and ECLK2, the parallel output result corresponding to ECLK3 is used as the data reference for data merging. When it is detected that the parallel data output by the serial-parallel conversion module 3 changes from 0 to 1, the results of parallel data 1 and parallel data 2 at this moment are recorded, and the output result 1 and the output result 2 are translated based on this time as the reference, so that all the output results are aligned based on this time as the reference; specifically, the low 2 bits of parallel data 1, i.e., the output result 1, are used as the high 2 bits of the converted data to obtain the output result 1 conversion; the low 5 bits of parallel data 2, i.e., the output result 2, are used as the high 5 bits of the converted data to obtain the output result 1 conversion, and the conversion result is as shown in Figure 10 The converted data and the output data of the serial-parallel conversion module 3 are merged according to the high and low bits to obtain 24-bit parallel data, which is equivalent to sampling the to-be-detected signal after the high-speed clock signal is tripled, and the detection accuracy can be improved by 3 times compared with the serial-parallel conversion method.

[0083] The multi-bit parallel detection values after the serial-parallel conversion are merged according to the phase relationship to obtain the combined parallel data, which is equivalent to frequency doubling the high-frequency clock again, and the smaller the phase shift angle is, the higher the detection accuracy is.

[0084] According to the combined parallel detection values, the detection interval time of the adjacent bits of the parallel detection values, and the value of the reference clock counter, the period value of the to-be-detected signal is calculated, and the frequency value of the to-be-detected signal is obtained according to the relationship between the period and the frequency.

[0085] Embodiment 2

[0086] Based on embodiment 1, a frequency detection system is provided in this embodiment, which includes a signal collector and a processor.

[0087] The signal collector is used for collecting the to-be-detected signal. The to-be-detected signal can be analog data.

[0088] The processor is configured to perform the frequency detection method described in embodiment 1 to detect the frequency of the to-be-detected signal.

[0089] Further, a communication unit and an upper computer are further included, and the processor is used for sending the frequency detection result to the upper computer through the communication unit.

[0090] Embodiment 3

[0091] Based on embodiment 1, a frequency detection system is provided in this embodiment, as shown in Figure 11 , which includes:

[0092] The high-speed comparison unit is configured to convert the acquired to-be-detected signal into a pulse form of the to-be-detected signal.

[0093] PLL module: configured to obtain a plurality of high-frequency clock signals with a set phase difference;

[0094] frequency division module: configured to divide the high-frequency clock signal to convert it into a reference clock signal;

[0095] serial-parallel conversion module: configured to detect the time of two rising edges or falling edges of adjacent cycles of the measured signal using a serial-parallel conversion method, and output corresponding multi-bit parallel detection values;

[0096] phase-shifted data merging module: configured to merge the multi-bit parallel detection values output by the serial-parallel conversion module using a plurality of high-frequency clock signals according to the phase relationship to obtain combined parallel detection values.

[0097] a calculation unit configured to calculate the frequency value of the measured signal according to the combined parallel detection values.

[0098] The analog channel data passes through a high-speed comparison circuit to obtain the pulse form of the measured signal. The measured signal is taken as an input signal and connected to the multi-channel serial-parallel conversion module. The phase-different multi-bit data output by the serial-parallel conversion module is merged by the phase-shifted data merging module, and the frequency is calculated according to the parallel data output by the module and the reference clock count value. Special cases that occur during the calculation process require separate frequency calculation. Finally, the frequency calculation result is sent to the host computer for recording through communication. The accuracy of the serial-parallel conversion module in measuring the frequency of the measured signal is affected by the high-frequency clock and the phase shift angle. The high-frequency clock frequency output by different devices is also different, and the device selection can be performed according to the actual engineering requirements.

[0099] It should be noted that each module in the embodiment corresponds to each step in Embodiment 1 one by one, and the specific implementation process is the same, which will not be repeated here.

[0100] Embodiment 4

[0101] The embodiment provides an electronic device, which includes a memory and a processor, and computer instructions stored in the memory and running on the processor. When the computer instructions are run by the processor, the steps of the method of Embodiment 1 are completed.

[0102] Embodiment 5

[0103] The embodiment provides a computer-readable storage medium for storing computer instructions. When the computer instructions are executed by a processor, the steps of the method of Embodiment 1 are completed.

[0104] The above merely describes preferred embodiments of the present disclosure and is not intended to limit the present disclosure. The present disclosure can have various modifications and changes for those skilled in the art. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

[0105] Although the specific embodiments of the present disclosure are described above with reference to the accompanying drawings, the present disclosure is not limited thereto, and those skilled in the art should understand that various modifications or changes made on the basis of the technical solutions of the present disclosure without creative labor are still within the protection scope of the present disclosure.

Claims

1. A frequency detection method, characterized by, It comprises the following steps: The acquired to-be-detected signal is converted into a pulse form of the detected signal; A plurality of high-frequency clock signals with a set phase difference are acquired; The high-frequency clock signals are frequency-divided to convert them into reference clock signals; A serial-parallel conversion method is used to detect the time of two rising edges or the time of two falling edges of adjacent periods of the detected signal, and output corresponding multi-bit parallel detection values; The multi-bit parallel detection values output after detection by the serial-parallel conversion method using the plurality of high-frequency clock signals are merged according to phase relationships to obtain combined parallel detection values, and the frequency value of the detected signal is calculated; The serial-parallel conversion method specifically comprises the following steps: the reference clock signals are aligned with the high-frequency clock signals, the detected signal is detected using the high-frequency clock signals, the rising edge or the falling edge of the high-frequency clock signal corresponds to output of a value A when the detected signal is at a high level, and output of a value B when the detected signal is at a low level; after sampling for one reference clock period, the sampling results are output in parallel from output pins; one or more periods of the detected signal are detected, and corresponding multi-bit parallel detection values are output; The merging according to phase relationships specifically comprises the following steps: the output results of the serial-parallel conversion of the plurality of high-frequency clock signals are aligned with the rising edge position time or the falling edge position time as a reference time, and the aligned output results are combined according to the high and low bits of the data.

2. A frequency detection method as claimed in claim 1, characterized in that: The product of the phase shift angle of the plurality of high-frequency clock signals and the number of high-frequency clock paths is equal to 360°.

3. The frequency detection method of claim 1, wherein: The value A output when the rising edge or the falling edge of the high-frequency clock signal corresponds to the detected signal being at a high level is 1, and the value B output when the rising edge or the falling edge of the high-frequency clock signal corresponds to the detected signal being at a low level is 0.

4. The frequency detection method of claim 1, wherein: According to the combined parallel detection values, the detection interval time of adjacent bits of the parallel detection values, and the value of the reference clock counter, the period value of the to-be-detected signal is calculated, and the frequency value of the to-be-detected signal is obtained according to the relationship between the period and the frequency.

5. A frequency detection system characterized by: It comprises a signal collector and a processor. The signal collector is configured to collect the detected signal. The processor is configured to perform the frequency detection method of any one of claims 1-4.

6. A frequency detection system characterized by, It comprises: A high-speed comparison unit configured to convert the acquired to-be-detected signal into a pulse form of the detected signal; A PLL module configured to acquire a plurality of high-frequency clock signals with a set phase difference; A frequency division module configured to frequency-divide the high-frequency clock signals to convert them into reference clock signals; A serial-parallel conversion module configured to use a serial-parallel conversion method to detect the time of two rising edges or the time of two falling edges of adjacent periods of the detected signal, and output corresponding multi-bit parallel detection values; A phase shift data merging module configured to merge the multi-bit parallel detection values output after detection by the serial-parallel conversion method using the plurality of high-frequency clock signals according to phase relationships to obtain combined parallel detection values; A calculation unit configured to calculate the frequency value of the detected signal according to the combined parallel detection values. The series-parallel conversion method is specifically: the reference clock signal is aligned with the high-frequency clock signal, the high-frequency clock signal is used to detect the measured signal, the rising edge or the falling edge of the high-frequency clock signal corresponds to the output value A when the measured signal is high, and the output value B is output when the measured signal is low; after sampling for one reference clock period, the sampling result is output in parallel from the output pin; the measured signal is detected for one or more periods, and corresponding multi-bit parallel detection values are output; The merging according to the phase relationship is specifically: taking the rising edge position moment or the falling edge position moment as a reference moment, the output results of the series-parallel conversion of the multiple high-speed clock signals are aligned, and the aligned output results are combined according to the high and low bits of the data.

7. An electronic device, comprising: The computer program product comprises a memory and a processor, and computer instructions stored in the memory and running on the processor, and when the computer instructions are run by the processor, the steps of the method in any one of claims 1-4 are completed.

8. A computer-readable storage medium, characterized in that, The computer program product is used for storing computer instructions, and when the computer instructions are executed by the processor, the steps of the method in any one of claims 1-4 are completed.

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