Display Panel

Abstract

The display panel includes: a first substrate having a top surface and a side surface, the top surface including a display area and a non-display area surrounding the display area; a second substrate facing the first substrate; a first insulating structure arranged between the second substrate and the first substrate, the first insulating structure overlapping the non-display area but not overlapping the display area; an organic light emitting diode between the first substrate and the second substrate and overlapping the display area; a thin film encapsulation layer on the organic light emitting diode; a signal line having a side surface aligned with the side surface of the first substrate, the signal line being arranged on the first substrate; a second insulating structure overlapping the signal line and arranged between the first substrate and the first insulating structure, the second insulating structure having a side surface aligned with the side surface of the first substrate; and a connecting pad in contact with the side surface of the signal line, wherein the second insulating structure includes an organic pattern overlapping the signal line and the non-display area but not overlapping the display area.

Description

[0001] This application is a divisional application of Chinese patent application No. 201811066081.X, entitled “Display Panel”, filed on September 13, 2018. Technical Field

[0002] Exemplary embodiments of the present invention relate generally to display panels, and more particularly, to a display panel having a strong structure and a large viewing area. Background Art

[0003] Generally, after manufacturing the display panel, a printed circuit board (PCB) is connected to the display panel. For example, in a tape automated bonding (TAB) mounting method, the PCB is bonded to the display panel using an anisotropic conductive film (ACF). Generally, the PCB has a planar shape extending from the display panel in a direction generally parallel to the display panel after connection, which increases the overall size of the display panel.

[0004] Recently, display panel design methods for reducing a bezel area (or a non-display area) have been studied in various ways.

[0005] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0006] A display panel constructed according to an exemplary embodiment of the present invention has a PCB connected to a side surface of the display panel, which can improve structural integrity and provide a more compact configuration, thereby reducing a non-display area and / or improving electrical connection between the PCB and signal lines, and preventing the signal lines from being damaged and / or deformed during a manufacturing process such as a grinding process.

[0007] According to one or more exemplary embodiments of the present invention, a display panel includes: a first substrate having a top surface and a side surface extending in a direction intersecting the top surface; a second substrate facing the first substrate; an insulating layer disposed between the first substrate and the second substrate; a first insulating structure disposed between the insulating layer and the first substrate; a pixel disposed between the first substrate and the second substrate; a signal line having a side surface substantially aligned with a side surface of the first substrate; a second insulating structure overlapping the signal line and contacting the first insulating structure; and a connection pad in contact with a side surface of the first substrate, a side surface of the signal line, and a side surface of the second insulating structure. The first insulating structure is in contact with the insulating layer, the signal line is disposed on the first substrate, and the second insulating structure has a side surface substantially aligned with a side surface of the first substrate.

[0008] The second insulating structure may include an organic layer overlapping the signal line and an inorganic layer disposed on the organic layer.

[0009] The pixel may include a first electrode, a second electrode insulated from the first electrode, a thin film transistor electrically connected to the first electrode, and a liquid crystal layer controlled by an electric field formed between the first electrode and the second electrode.

[0010] The display panel may further include a spacer overlapping the thin film transistor. The first electrode and the second electrode may overlap each other and may be spaced apart from each other in a thickness direction of the first substrate, the inorganic layer may extend to overlap the thin film transistor, the second electrode may overlap the thin film transistor, and the spacer may be disposed between a portion of the inorganic layer overlapping the thin film transistor and a portion of the second electrode overlapping the thin film transistor.

[0011] The first insulating structure and the spacer may include substantially the same material.

[0012] The display panel may further include a color filter disposed between the first substrate and the first electrode and overlapping the first electrode.

[0013] The inorganic layer may extend to overlap with and contact the color filter.

[0014] The organic layer and the color filter may include substantially the same material.

[0015] The signal line may be provided on substantially the same layer as the control electrode of the thin film transistor.

[0016] The display panel may further include a sealing member spaced apart from the organic layer of the second insulating structure. The sealing member may surround the liquid crystal layer.

[0017] The display may further include a floating electrode overlapping the signal line and the second insulating structure. The floating electrode may be disposed between the signal line and the organic layer of the second insulating structure.

[0018] The floating electrode may be disposed on substantially the same layer as an input electrode or an output electrode of the thin film transistor.

[0019] The display panel may further include a circuit substrate electrically connected to the connection pad.

[0020] The pixel may include a first electrode, a second electrode insulated from the first electrode, a thin film transistor electrically connected to the first electrode, and a light emitting layer disposed between the first electrode and the second electrode.

[0021] The signal lines may include copper, and the connection pads may include silver paste.

[0022] According to one or more exemplary embodiments of the present invention, a display panel includes: a first substrate having a top surface and a side surface extending in a direction intersecting the top surface; a second substrate facing the first substrate; an electrode disposed between the first substrate and the second substrate; a liquid crystal layer disposed between the first substrate and the second substrate; a sealing structure disposed between the first substrate and the second substrate and configured to surround the liquid crystal layer; an insulating structure disposed between the first substrate and the second substrate and disposed outside the sealing structure; a signal line having a side surface substantially aligned with a side surface of the first substrate; and a connecting pad contacting a side surface of the first substrate, a side surface of the signal line, and a side surface of the insulating structure. The insulating structure has a side surface substantially aligned with a side surface of the first substrate and includes a layer different from a layer of the sealing structure. The signal line is disposed on the first substrate and overlaps with the insulating structure.

[0023] The insulating structure may surround the sealing structure.

[0024] The sealing structure may have a single-layer structure, and the insulating structure may include at least two stacked organic layers.

[0025] The insulating structure may further include an inorganic layer disposed between the two organic layers.

[0026] The electrode may include a first electrode and a second electrode spaced apart from each other, the liquid crystal layer may be disposed between the first electrode and the second electrode, the sealing structure may contact one of the first electrode and the second electrode, and the insulating structure may be spaced apart from the first electrode and the second electrode.

[0027] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0028] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings illustrate exemplary embodiments of the present invention and together with the description serve to explain the inventive concept, wherein the accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification.

[0030] Figure 1 is a schematic perspective view of an exemplary embodiment of a display device constructed according to the principles of the present invention.

[0031] Figure 2 yes Figure 1 A schematic plan view of a display device.

[0032] Figure 3 yes Figure 1 A schematic partial stereoscopic view of a display area of ​​a display panel of a display device.

[0033] Figure 4 yes Figure 1 A schematic partial stereoscopic view of a non-display area of ​​a display panel of a display device.

[0034] Figure 5 yes Figure 2 An equivalent circuit diagram of a pixel of a display panel of a display device.

[0035] FIG. 6A to FIG. 6C is a schematic cross-sectional view of a display area of ​​a display panel constructed according to some embodiments of the present invention.

[0036] Figure 7 is a schematic cross-sectional view of a non-display area of ​​a display panel constructed according to an embodiment of the present invention.

[0037] Figure 8 is a cross-sectional image of a non-display region of a display panel constructed according to an embodiment of the present invention.

[0038] Fig.9A is a schematic perspective view of a working panel used in an exemplary method of manufacturing a display panel according to an embodiment of the present invention.

[0039] Fig. 9B yes Fig.9A Schematic cross-sectional view of a working panel.

[0040] Fig. 9C is from Fig.9A A schematic cross-sectional view of the initial display panel cut of the working panel.

[0041] Fig.9D is a cross-sectional image of a display panel as a comparative example.

[0042] Fig.10 is a schematic cross-sectional view of a non-display area of ​​a display panel constructed according to an embodiment of the present invention.

[0043] Fig.11 is an equivalent circuit diagram of a pixel applicable in any of the display panels constructed according to the embodiments of the present invention.

[0044] Fig.12 is a schematic cross-sectional view of a display area of ​​a display panel constructed according to an embodiment of the present invention.

[0045] Fig.13 is a schematic cross-sectional view of a non-display area of ​​a display panel constructed according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of each exemplary embodiment or embodiment of the present invention. As used herein, "embodiment" and "embodiment" are interchangeable words, which are non-limiting examples of one or more devices or methods to which the inventive concepts disclosed herein are applied. However, it is apparent that each exemplary embodiment can be implemented without these specific details or by one or more equivalent arrangements. In other cases, in order to avoid unnecessary confusion of each exemplary embodiment, known structures and devices are shown in block diagram form. In addition, each exemplary embodiment may be different, but does not have to be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0047] Unless otherwise noted, the exemplary embodiments shown should be understood as providing exemplary features of different details that can actually implement some ways of inventive concepts. Therefore, unless otherwise noted, the features, components, modules, layers, films, panels, regions and / or aspects of each embodiment (hereinafter individually referred to as or collectively referred to as "elements") may be combined, separated, exchanged and / or rearranged without departing from the inventive concept.

[0048] The use of hatching and / or shading in the drawings is generally used to make the boundaries between adjacent elements clear. Thus, unless otherwise indicated, the presence or absence of hatching or shading does not convey or indicate any preference or need for a particular material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments may be performed differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0049] When an element such as a layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, connected to or coupled to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may represent a physical connection, an electrical connection, and / or a fluid connection with or without an intervening element. In addition, the D1 axis, the D2 axis, and the D3 axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, the y-axis, and the z-axis), and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0051] Spatially relative terms, such as "beneath", "below", "under", "lower", "above", "upper", "over", "higher", "side" (e.g., as in "sidewall"), etc., may be used herein for descriptive purposes, and thus may be used to describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, elements described as being "below" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both the above orientation and the below orientation. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and thus, the spatially relative descriptors used herein should be interpreted accordingly.

[0052] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "one", "an" and "said" are intended to also include plural forms. In addition, the terms "comprises", "comprising", "includes" and / or "including" when used in this specification specify the presence of the features, wholes, steps, operations, elements, components and / or combinations thereof described, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. It should also be noted that the terms "substantially", "about" and other similar terms as used herein are used as approximate terms rather than as terms of degree, and thus, are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that would be recognized by a person of ordinary skill in the art.

[0053] The exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, deviations from the shapes of the accompanying drawings due to, for example, manufacturing techniques and / or tolerances should be contemplated. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but should include shape deviations due to, for example, manufacturing. In this manner, the regions shown in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus, are not necessarily intended to be limiting.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. Terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0055] Figure 1 is a schematic perspective view of an exemplary embodiment of a display device constructed according to the principles of the present invention. Figure 2 yes Figure 1 A schematic plan view of a display device. Figure 3 yes Figure 1 A schematic partial stereoscopic view of a display area of ​​a display panel of a display device. Figure 4 yes Figure 1 A schematic partial stereoscopic view of a non-display area of ​​a display panel of a display device.

[0056] refer to Figure 1 and Figure 2The display device DD includes a display panel DP, a gate driving unit GDC, a data driving unit DDC, a main circuit substrate PB, and a signal controller SC. The display device DD may further include a base member or a molding member, and may further include a backlight unit according to the type of the applied display panel DP.

[0057] The display panel DP may be formed as a liquid crystal display panel, a plasma display panel, an electrophoretic display panel, a micro-electromechanical system (MEMS) display panel, an electrowetting display panel, or other types of display panels known in the art.

[0058] The display panel DP may include a first display substrate 100 and a second display substrate 200 disposed on the first display substrate 100. Figure 1 Although not visible in the figure, a gap may be formed between the first display substrate 100 and the second display substrate 200.

[0059] like Figure 1 As shown in , the display panel DP may display an image through a display surface DP-IS. The display surface DP-IS is parallel to a plane defined by a first direction axis DR1 and a second direction axis DR2. The display surface DP-IS may include a display area DA and a non-display area NDA. The non-display area NDA may be defined along an edge of the display surface DP-IS and may surround the display area DA.

[0060] The normal direction of the display surface DP-IS (i.e., the thickness direction of the display panel DP) is indicated by the third directional axis DR3. Hereinafter, the front surface (or top surface) and the rear surface (or bottom surface) of each of the layers or units may have a thickness defined on the third directional axis DR3. However, the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 shown in the illustrated embodiment are examples of the present invention, and the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 may be relative concepts and may be changed to other directions. Hereinafter, the first direction, the second direction, and the third direction are directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3, respectively, and are indicated by the same reference numerals as the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3.

[0061] In the illustrated embodiment, a display panel DP having a flat display surface is shown. However, the inventive concept is not limited thereto. In some embodiments, the display panel DP may include a curved display surface or a three-dimensional (3D) display surface. The 3D display surface may include a plurality of display areas indicated by different directions.

[0062] The gate driving unit GDC and the data driving unit DDC may include circuit substrates GCB and DCB and driving chips GC and DC, respectively, wherein the circuit substrates GCB and DCB may be formed as a printed circuit board (PCB). Each of the circuit substrates GCB and DCB has a structure in which an insulating layer and a conductive layer are stacked. The conductive layer may include a plurality of signal lines. The gate driving unit GDC and the data driving unit DDC may be coupled to the side surface of the display panel DP to be electrically connected to the signal lines of the display panel DP, and may have a plane shape defined by the second direction DR2 (or the first direction DR1) and the third direction DR3, extending substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 of the display panel DP. Because the gate driving unit GDC and the data driving unit DDC are coupled to the side surface of the display panel DP in this manner, the non-display area NDA may be reduced compared to a typical configuration in a plane shape defined by a circuit substrate extending substantially parallel to the plane of the display surface DP-IS.

[0063] In the illustrated embodiment, the gate driving unit GDC and the data driving unit DDC are coupled to different side surfaces of the display panel DP. However, the inventive concept is not limited thereto. In another embodiment, one of the gate driving unit GDC and the data driving unit DDC may be omitted. In other embodiments, the gate driving unit GDC and the data driving unit DDC may be coupled to substantially the same side surface of the display panel DP, or the gate driving unit GDC may be integrated on the display panel DP by an oxide silicon gate driver circuit (OSG) process or an amorphous silicon gate driver circuit (ASG) process.

[0064] The main circuit substrate PB may be connected to the circuit substrate DCB of the data driving unit DDC. The main circuit substrate PB may be electrically connected to the circuit substrate DCB of the data driving unit DDC through an anisotropic conductive film (ACF) or a solder ball. The signal controller SC may be mounted on the main circuit substrate PB. The signal controller SC receives image data and control signals from an external graphic controller. The signal controller SC may provide control signals to the gate driving unit GDC and the data driving unit DDC.

[0065] In an embodiment of the present invention, the display device DD may further include a main circuit substrate connected to the circuit substrate GCB of the gate driving unit GDC. In an embodiment of the present invention, the driving chip DC of the data driving unit DDC may be mounted on the main circuit substrate PB.

[0066] Figure 21 shows a planar arrangement of signal lines GL1 to GLn, DL1 to DLm, PL-G and PL-D and pixels PX11 to PXnm in the display panel DP. The signal lines GL1 to GLn, DL1 to DLm, PL-G and PL-D may include a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and first and second auxiliary signal lines PL-G and PL-D.

[0067] The gate lines GL1 to GLn extend in the first direction DR1 and are arranged in the second direction DR2 , and the data lines DL1 to DLm are insulated from the gate lines GL1 to GLn and cross the gate lines GL1 to GLn.

[0068] The gate lines GL1 to GLn and the data lines DL1 to DLm overlap each other and are disposed in the display area DA. The first and second auxiliary signal lines PL-G and PL-D are disposed in the non-display area NDA and are connected to the gate lines GL1 to GLn and the data lines DL1 to DLm.

[0069] The first auxiliary signal lines PL-G connected to the gate lines GL1 to GLn may be disposed on substantially the same layer as the gate lines GL1 to GLn and may constitute a single body with the gate lines GL1 to GLn. The second auxiliary signal lines PL-D connected to the data lines DL1 to DLm may be disposed on a layer different from a layer on which the data lines DL1 to DLm are disposed. Each of the data lines DL1 to DLm may be electrically connected to a corresponding one of the second auxiliary signal lines PL-D through a contact hole CH penetrating at least one insulating layer disposed between the second auxiliary signal lines PL-D and the data lines DL1 to DLm.

[0070] In an embodiment of the present invention, the contact hole CH may be omitted, and the data lines DL1 to DLm and the second auxiliary signal line PL-D may be disposed on substantially the same layer. In the illustrated embodiment, the gate lines GL1 to GLn and the first auxiliary signal line PL-G are distinguished from each other. However, in another embodiment, the gate line and the first auxiliary signal line connected to each other may be defined as one signal line. In this case, the gate line and the first auxiliary signal line connected to each other may be defined as different parts of one signal line.

[0071] The signal lines GL1 to GLn, DL1 to DLm, PL-G, and PL-D may further include other signal lines such as signal lines for electrically connecting the gate driving unit GDC to each other and signal lines for electrically connecting the gate driving unit GDC to the main circuit substrate PB.

[0072] Each of the pixels PX11 to PXnm is connected to a corresponding one of the gate lines GL1 to GLn and a corresponding one of the data lines DL1 to DLm. Each of the pixels PX11 to PXnm may include a pixel driving circuit and a display element.

[0073] Figure 2 2 shows as an example that the pixels PX11 to PXnm are arranged in a matrix shape. However, the inventive concept is not limited thereto. In another embodiment, the pixels PX11 to PXnm may be arranged in a pentile shape.

[0074] Figure 3 The central portion of the display area DA is shown. The display area DA may include a pixel area PXA and a peripheral area NPXA. The peripheral area NPXA may surround each of the pixel areas PXA and may correspond to a boundary area between the pixel areas PXA. The pixel areas PXA may be arranged in substantially the same shape as the pixels PX11 to PXnm.

[0075] The pixel area PXA may substantially correspond to an area displaying a color. In a transmissive display panel, the pixel area PXA may correspond to a transmissive area, or in an emissive display panel, the pixel area PXA may correspond to an emissive area. The pixel area PXA may be divided into a plurality of groups based on the color displayed by the pixel area PXA. In other words, each of the pixel areas PXA may display one of the primary colors. The primary colors may include red, green, blue, and white.

[0076] A gap GP is defined between the first display substrate 100 and the second display substrate 200. Figure 2 The described signal lines GL1 to GLn, DL1 to DLm, PL-G, and PL-D may be included in one of the first display substrate 100 and the second display substrate 200. The pixels PX11 to PXnm may be included in one of the first display substrate 100 and the second display substrate 200. Alternatively, some components of the pixels PX11 to PXnm may be included in the first display substrate 100, and other components of the pixels PX11 to PXnm may be included in the second display substrate 200. The pixels PX11 to PXnm may be disposed between a base substrate of the first display substrate 100 and a base substrate of the second display substrate 200.

[0077] Figure 4 A portion of the non-display area NDA that may be connected to the gate driving unit GDC and the data driving unit DDC is shown. Figure 4 A portion where the second auxiliary signal line PL-D is provided is shown.

[0078] The insulating structure IS, which has a side surface substantially aligned with the side surface of the display panel DP, may overlap the second auxiliary signal line PL-D. The insulating structure IS may have a multi-layered structure. Figure 4 2 shows an insulating structure IS having a two-layer structure as an example. One of the first insulating structure IS1 and the second insulating structure IS2 of the insulating structure IS may correspond to a portion of one of the first display substrate 100 and the second display substrate 200.

[0079] Although Figure 4 , a portion of the insulating structure IS is shown in FIG. 1 , but the insulating structure IS may extend along the edge of the display panel DP in a plan view and may have a closed loop shape in a plan view.

[0080] A sealing structure SS may be further provided between the first display substrate 100 and the second display substrate 200. The sealing structure SS may be provided inside the insulating structure IS. In other words, the sealing structure SS may be closer to the display area DA than the insulating structure IS. In other words, the sealing structure SS may be provided between the insulating structure IS and the display area DA. The sealing structure SS may surround the gap GP. In other words, the first display substrate 100, the second display substrate 200, and the sealing structure SS may define a sealed space.

[0081] The sealing structure SS may have a structure different from that of the insulating structure IS. The sealing structure SS may have a single-layer structure. The sealing structure SS may include a photocurable organic material, a thermosetting organic material, or a glass frit sealant.

[0082] Figure 5 yes Figure 2 An equivalent circuit diagram of a pixel of a display panel of a display device. FIG. 6A to FIG. 6C is a schematic cross-sectional view of a display area of ​​a display panel constructed according to some embodiments of the present invention. Figure 7 is a schematic cross-sectional view of a non-display area of ​​a display panel constructed according to an embodiment of the present invention. Figure 8 is a cross-sectional image of a non-display region of a display panel constructed according to an embodiment of the present invention.

[0083] Figures 5 to 8 A liquid crystal display panel is shown as an example of the display panel DP. Figure 5 4 shows a pixel PXij connected to an i-th gate line GLi and a j-th data line DLj as an example.

[0084] The pixel PXij may include a thin film transistor TR (hereinafter, referred to as a "transistor"), a liquid crystal capacitor Clc, and a storage capacitor Cst. The liquid crystal capacitor Clc may correspond to a display element, and the transistor TR and the storage capacitor Cst may constitute a pixel driving circuit. The number of transistors TR and storage capacitors Cst may vary according to an operation mode of the liquid crystal display panel.

[0085] The liquid crystal capacitor Clc may store a pixel voltage output from the transistor TR. The arrangement of the liquid crystal directors included in the liquid crystal layer LCL may be changed according to the amount of charge stored in the liquid crystal capacitor Clc. In other words, the liquid crystal directors may be controlled by an electric field formed between two electrodes of the liquid crystal capacitor Clc. Light incident to the liquid crystal layer LCL may be transmitted or blocked according to the arrangement of the liquid crystal directors.

[0086] The storage capacitor Cst is connected to the liquid crystal capacitor Clc in parallel. The storage capacitor Cst maintains the alignment of the liquid crystal directors for a certain period.

[0087] The transistor TR includes a control electrode GE connected to the i-th gate line GLi, an active component AL overlapping the control electrode GE, an input electrode SE connected to the j-th data line DLj, and an output electrode DE spaced apart from the input electrode SE.

[0088] The liquid crystal capacitor Clc includes a pixel electrode PE and a common electrode CE. The storage capacitor Cst includes the pixel electrode PE and a portion of the storage line STL overlapping the pixel electrode PE.

[0089] The i-th gate line GLi and the storage line STL are disposed on one surface of the first base substrate BS1 of the first display substrate 100. The control electrode GE branches from the i-th gate line GLi. The i-th gate line GLi and the storage line STL may include a metal (e.g., aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti)) or any alloy thereof. In an embodiment, the i-th gate line GLi and the storage line STL may have a multi-layer structure (e.g., a titanium layer and a copper layer).

[0090] The first base substrate BS1 may be a glass substrate or a plastic substrate. The first insulating layer 10 may be disposed on one surface of the first base substrate BS1 and may cover the control electrode GE and the storage line STL. The first insulating layer 10 may include at least one of an inorganic material and an organic material. For example, the first insulating layer 10 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. In an embodiment, the first insulating layer 10 may include a multilayer structure (e.g., a silicon nitride layer and a silicon oxide layer).

[0091] The active part AL overlapping the control electrode GE is disposed on the first insulating layer 10. The active part AL may include a semiconductor layer SCL and an ohmic contact layer OCL. The semiconductor layer SCL is disposed on the first insulating layer 10, and the ohmic contact layer OCL is disposed on the semiconductor layer SCL.

[0092] The semiconductor layer SCL may include amorphous silicon or polycrystalline silicon. Alternatively, the semiconductor layer SCL may include a metal oxide semiconductor. The ohmic contact layer OCL may be doped with a dopant. The concentration of the dopant in the ohmic contact layer OCL may be higher than the concentration of the dopant in the semiconductor layer SCL. The ohmic contact layer OCL may include two parts spaced apart from each other. In an embodiment of the present invention, the ohmic contact layer OCL may have a single body.

[0093] The output electrode DE and the input electrode SE are disposed on the active part AL. The output electrode DE and the input electrode SE are spaced apart from each other. Each of the output electrode DE and the input electrode SE partially overlaps the control electrode GE.

[0094] The second insulating layer 20 is disposed on the first insulating layer 10 and covers the active component AL, the output electrode DE, and the input electrode SE. The second insulating layer 20 may include at least one of an inorganic material and an organic material. For example, the second insulating layer 20 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. In an embodiment, the second insulating layer 20 may include a multilayer structure (e.g., a silicon nitride layer and a silicon oxide layer).

[0095] Fig. 6A 2 shows a transistor TR having a staggered structure as an example. However, the structure of the transistor TR is not limited thereto. In another embodiment, the transistor TR may have a planar structure.

[0096] The third insulating layer 30 is disposed on the second insulating layer 20. The third insulating layer 30 may be a single organic layer that provides a flat surface. In the illustrated embodiment, the third insulating layer 30 may include a plurality of color filters. The color filters may at least completely cover the second insulating layer 20. Figure 3 In the peripheral area NPXA, color filters of adjacent pixels may partially overlap each other.

[0097] The fourth insulating layer 40 is disposed on the third insulating layer 30. The fourth insulating layer 40 may be an inorganic layer covering the color filter. For example, the fourth insulating layer 40 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. In an embodiment, the fourth insulating layer 40 may include a multilayer structure (e.g., a silicon nitride layer and a silicon oxide layer).

[0098] The pixel electrode PE is disposed on the fourth insulating layer 40. The pixel electrode PE is connected to the output electrode DE through a contact hole CH10 penetrating the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. An alignment layer covering the pixel electrode PE may be disposed on the fourth insulating layer 40.

[0099] The second base substrate BS2 of the second display substrate 200 may be a glass substrate or a plastic substrate. The black matrix layer BM is disposed on the bottom surface of the second base substrate BS2. The black matrix layer BM may have a Figure 3 In other words, an opening corresponding to the pixel area PXA may be defined in the black matrix layer BM.

[0100] At least one insulating layer covering the black matrix layer BM is disposed on the bottom surface of the second base substrate BS2. Fig. 6A , the fifth insulating layer 50 providing a substantially flat surface is illustrated as an example of providing an insulating layer on the bottom surface of the second base substrate BS2. The fifth insulating layer 50 may include an organic material.

[0101] The common electrode CE is disposed on the bottom surface of the second base substrate BS2. A common voltage is applied to the common electrode CE. The value of the common voltage is different from the value of the pixel voltage. However, Fig. 6A A cross section of a pixel PXij is shown as an example of the present invention. In another embodiment, the first display substrate 100 and the second display substrate 200 may be reversed.

[0102] In the illustrated embodiment, a liquid crystal display panel in a vertical alignment (VA) mode is described as an example. However, the inventive concept is not limited thereto. The embodiments of the present invention may be applied to a liquid crystal display panel in an in-plane switching (IPS) mode, a fringe field switching (FFS) mode, a plane line switching (PLS) mode, a super vertical alignment (SVA) mode, or a surface stabilized vertical alignment (SS-VA) mode, or other modes known in the art.

[0103] Figure 6B An in-plane switching (IPS) mode liquid crystal display panel is shown, and Figure 6C , a liquid crystal display panel in a plane-line switching (PLS) mode is shown. In a liquid crystal display panel in an in-plane switching (IPS) mode, a pixel electrode PE and a common electrode CE may be disposed on substantially the same layer. Each of the pixel electrode PE and the common electrode CE may include a plurality of branch portions. The branch portions of the pixel electrode PE and the branch portions of the common electrode CE may be arranged alternately. The common electrode CE may be connected to a signal line (e.g., a storage line STL) receiving a common voltage through a contact hole CH20.

[0104] In a plane-to-line switching (PLS) mode liquid crystal display panel, the pixel electrode PE and the common electrode CE may be disposed on the fourth insulating layer 40 with the sixth insulating layer 45 interposed therebetween. The pixel electrode PE may include a plurality of branch portions or may include a plurality of slits.

[0105] The spacer CS may be disposed between the first display substrate 100 and the second display substrate 200. The spacer CS maintains Figure 3 The spacer CS may include a photosensitive organic material. The spacer CS overlaps the peripheral area NPXA. The spacer CS may overlap the transistor TR.

[0106] like Figure 7 As shown in , the side surface PL-DS of the second auxiliary signal line PL-D is substantially aligned with the side surface BS1-S of the first base substrate BS1. The side surface of the insulating structure IS is substantially aligned with the side surface BS1-S of the first base substrate BS1. The insulating structure IS includes a first insulating structure IS1 in contact with the fifth insulating layer 50 of the second display substrate 200. The first insulating structure IS1 is disposed between the fifth insulating layer 50 and the first base substrate BS1. In the case where the alignment layer is disposed below the fifth insulating layer 50, the first insulating structure IS1 may be in contact with the alignment layer. The alignment layer may be defined as another insulating layer.

[0107] The first insulating structure IS1 may include Figures 6A to 6C The spacer CS shown in FIG. is made of substantially the same material. 9A to 9C When describing the second working substrate 200 -W, the first insulating structure IS1 and the spacer CS may be formed by substantially the same process.

[0108] The insulating structure IS includes a second insulating structure IS2 corresponding to a portion of the first display substrate 100. A side surface of the second insulating structure IS2 is substantially aligned with the side surface BS1-S of the first base substrate BS1. The second insulating structure IS2 may have a two-layer structure. The first layer IS2-1 of the second insulating structure IS2 may include an organic material. The first layer IS2-1 may include an organic material such as Figures 6A to 6C The first layer IS2-1 may include substantially the same material as the color filter. The second layer IS2-2 of the second insulating structure IS2 may include an inorganic material. The second layer IS2-2 may be a part of the fourth insulating layer 40. In an embodiment of the present invention, the second layer IS2-2 may be omitted.

[0109] The connection pad CP is disposed on the side surface of the display panel DP. The connection pad CP may be provided in plurality, and the connection pad CP may be in contact with the side surface PL-DS of the second auxiliary signal line PL-D, respectively. The connection pad CP may be in contact with the side surface BS1-S of the first base substrate BS1, the side surface PL-DS of the second auxiliary signal line PL-D, and the side surface of the insulating structure IS. In one embodiment of the present invention, the connection pad CP may be in contact with the side surface BS1-S of the first base substrate BS1, the side surface of the insulating structure IS, and the side surface of the second base substrate BS2. Figure 7 2 shows as an example a connection pad CP in contact with the side surface IS2-S of the second insulating structure IS2. The connection pad CP may include a metal paste. The metal paste includes a mixture of a metal and an insulating material. The connection pad CP may include a silver paste.

[0110] The connection pad CP may be electrically connected to the pad DCB-P of the circuit substrate DCB through an anisotropic conductive film (ACF). The size of the pad DCB-P of the circuit substrate DCB and the size of the anisotropic conductive film (ACF) may be set to correspond to the size of the connection pad CP. The anisotropic conductive film (ACF) may be replaced with solder paste, and the connection pad CP may be directly connected to the pad DCB-P of the circuit substrate DCB.

[0111] The sealing structure SS may be disposed inside the insulating structure IS and may be disposed between the common electrode CE and the fourth insulating layer 40. In the case where an alignment layer is disposed, the sealing structure SS is disposed between the alignment layers. A black matrix layer BM is also disposed in the non-display area NDA.

[0112] Figure 8 The second auxiliary signal line PL-D overlapping the insulating structure IS and the connection pad CP connected to the second auxiliary signal line PL-D are shown. The insulating structure IS may be provided to eliminate a gap between the first display substrate 100 and the second display substrate 200 near the side surface of the display panel DP. Therefore, the end of the second auxiliary signal line PL-D may be prevented from being damaged in a manufacturing process to be described later.

[0113] Fig.9A is a schematic perspective view of a working panel used in an exemplary method of manufacturing a display panel according to an embodiment of the present invention. Fig. 9B yes Fig.9A Schematic cross-sectional view of a working panel. Fig. 9C is from Fig.9A A schematic cross-sectional view of the initial display panel cut of the working panel. Fig.9D is a cross-sectional image of a display panel as a comparative example.

[0114] like Fig.9AAs shown in FIG. 1 , substantially the same process may be performed on the cell areas DP-C defined in the work panel WP to form a plurality of cell areas DP-C as shown in FIG. 1 . Figures 5 to 7 More specifically, the first working substrate 100-W and the second working substrate 200-W may be coupled to each other to form the working panel WP. In each of the cell areas DP-C, the first working substrate 100-W may have a Figures 5 to 7 The first display substrate 100 described above has substantially the same structure, and in each of the unit cell areas DP-C, the second working substrate 200-W may have the same structure as the reference Figures 5 to 7 The second display substrate 200 is described to have substantially the same structure.

[0115] like Fig. 9B As shown in FIG. 1 , the structure extending from the structure of the cell area DP-C may be arranged in the border area BA of the working panel WP. Fig. 9B The cutting line CL shown in FIG. 1 cuts the work panel WP, and thus, the Fig. 9C The initial display panel DP-P.

[0116] and Figure 7 Compared with the side surface of the display panel DP, Fig. 9C The side surface of the initial display panel DP-P is in a non-uniform state. The side surface of the initial display panel DP-P is ground using a grinding machine GM, which is called a grinding process. The grinding process can be used to make the side surface of the insulating structure IS, the side surface of the second auxiliary signal line PL-D, the side surface of the first base substrate BS1, and the side surface of the second base substrate BS2 basically aligned with each other. The cross-sectional shape of the second auxiliary signal line PL-D may be different depending on the grinding method (for example, the rotation direction of the grinding machine GM). However, regardless of the grinding method, the side surface of the second auxiliary signal line PL-D and the side surface of the first base substrate BS1 can be basically aligned with each other. Figure 8 The side surface of the second auxiliary signal line PL-D is Fig. 9C The rotation direction of the grinding wheel machine GM is formed.

[0117] As used herein, the term "substantially aligned" may include a case where the insulating structure IS, the second auxiliary signal line PL-D, and the side surfaces of the first base substrate BS1 and the second base substrate BS2 constitute one surface, and the term "substantially aligned" may also include deviations due to manufacturing technology and / or process tolerances. For example, the side surface of the second auxiliary signal line PL-D may have a fine curved surface formed by a grinder GM. The corners defining the curved side surface of the second auxiliary signal line PL-D may be aligned with the corners defining the side surface of the insulating structure IS.

[0118] During the grinding process, the end of the second auxiliary signal line PL-D can be prevented from being damaged / deformed. This may be because the insulating structure IS supports the first display substrate 100 and the second display substrate 200, thereby preventing the side surface of the display panel DP from being damaged / deformed due to friction of the grinder GM.

[0119] Fig.9D A cross section of a display panel DP-S as a comparative example is shown. Fig.9D Shown with Figure 8 However, because Fig.9D In the embodiment, the insulating structure IS is not provided in the region GP-E corresponding to the insulating structure IS, so the region GP-E is filled with residues generated during the grinding process. In addition, the residues of the first base substrate BS1 cover the side surface of the second auxiliary signal line PL-D, and therefore, the second auxiliary signal line PL-D is not completely connected to the connection pad CP. In other words, the contact resistance between the second auxiliary signal line PL-D and the connection pad CP increases.

[0120] Fig.10 is a schematic cross-sectional view of a non-display area of ​​a display panel constructed according to an embodiment of the present invention. Fig.10 Shown with Figure 7 In the following, in order to avoid redundancy, the Figures 1 to 9D Description of components that are the same or substantially the same as those in the embodiments of the present invention.

[0121] With reference Figures 1 to 7 Compared with the display panel DP described above, the display panel DP according to the illustrated embodiment further includes a floating electrode FE. The floating electrode FE overlaps the second auxiliary signal line PL-D and the first layer IS2-1 of the second insulating structure IS2. The floating electrode FE is disposed between the second auxiliary signal line PL-D and the first layer IS2-1 of the second insulating structure IS2. The floating electrode FE may be disposed on substantially the same layer as the input electrode SE of the transistor TR.

[0122] A side surface of the floating electrode FE may be substantially aligned with the side surface BS1 -S of the first base substrate BS1 The connection pad CP may be in contact with the side surface of the floating electrode FE.

[0123] Figure 8 The floating electrode FE is shown in FIG. The floating electrode FE may be disposed on the second auxiliary signal line PL-D to resist stress applied to the second auxiliary signal line PL-D during grinding, and thus may prevent damage / deformation of the second auxiliary signal line PL-D.

[0124] Fig.11 is an equivalent circuit diagram of a pixel applicable in any of the display panels constructed according to the embodiments of the present invention. Fig.12 is a schematic cross-sectional view of a display area of ​​a display panel constructed according to an embodiment of the present invention. Fig.13 is a schematic cross-sectional view of a non-display area of ​​a display panel constructed according to an embodiment of the present invention.

[0125] Already used as an example reference Figures 5 to 8 A liquid crystal display panel is described. However, the principles of the present invention may also be applied to other types of displays, such as Figures 11 to 13 Hereinafter, in order to avoid redundancy, the difference between the liquid crystal display panel and the organic light emitting display panel will be mainly described.

[0126] like Fig.11 As shown in , the pixel PXij connected to the i-th gate line GLi and the j-th data line DLj may include an organic light emitting diode OLED and a pixel driving circuit. The organic light emitting diode OLED may be a front surface type light emitting diode or a rear surface type light emitting diode. The pixel driving circuit may include a first thin film transistor (or switching transistor) TR1, a second thin film transistor (or driving transistor) TR2 and a capacitor Cst. The first power supply voltage ELVDD is provided to the second thin film transistor TR2, and the second power supply voltage ELVSS is provided to the organic light emitting diode OLED. The second power supply voltage ELVSS may be lower than the first power supply voltage ELVDD. However, the pixel driving circuit may not be limited thereto, but may be variously changed. The pixel driving circuit may also include a plurality of transistors and / or may include two or more capacitors. In another embodiment, the organic light emitting diode OLED may be connected between the power line PL and the second thin film transistor TR2.

[0127] like Fig.12 As shown in , the circuit element layer DP-CL, the display element layer DP-OLED and the thin film encapsulation layer TFE are sequentially stacked on the first base substrate BS1. In the illustrated embodiment, the circuit element layer DP-CL may include a buffer layer BFL, a first insulating layer 10, a second insulating layer 20 and a third insulating layer 30, wherein the buffer layer BFL corresponds to an inorganic layer. The first insulating layer 10 and the second insulating layer 20 may be inorganic layers, and the third insulating layer 30 may be an organic layer. The materials of the inorganic layer and the organic layer are not limited to specific materials, and the buffer layer BFL may be provided or omitted in some embodiments of the present invention.

[0128] The semiconductor pattern OSP1 of the first thin film transistor TR1 (hereinafter, referred to as a "first semiconductor pattern") and the semiconductor pattern OSP2 of the second thin film transistor TR2 (hereinafter, referred to as a "second semiconductor pattern") are disposed on the buffer layer BFL. Each of the first semiconductor pattern OSP1 and the second semiconductor pattern OSP2 may be at least one material selected from the group consisting of amorphous silicon, polycrystalline silicon, and a metal oxide semiconductor.

[0129] The first insulating layer 10 is disposed on the first semiconductor pattern OSP1 and the second semiconductor pattern OSP2. The control electrode GE1 of the first thin film transistor TR1 (hereinafter, referred to as the "first control electrode") and the control electrode GE2 of the second thin film transistor TR2 (hereinafter, referred to as the "second control electrode") are disposed on the first insulating layer 10. The first control electrode GE1 and the second control electrode GE2 may be connected to the reference electrode GE1. Fig.11 The gate lines GLi are formed by substantially the same photolithography process.

[0130] The second insulating layer 20 is disposed on the first insulating layer 10 and covers the first control electrode GE1 and the second control electrode GE2. The input electrode DE1 (hereinafter, the first input electrode) and the output electrode SE1 (hereinafter, the first output electrode) of the first thin film transistor TR1 and the input electrode DE2 (hereinafter, the second input electrode) and the output electrode SE2 (hereinafter, the second output electrode) of the second thin film transistor TR2 are disposed on the second insulating layer 20.

[0131] The first input electrode DE1 and the first output electrode SE1 are connected to a portion of the first semiconductor pattern OSP1 via first and second through holes CH1 and CH2, respectively, which penetrate the first and second insulating layers 10 and 20. The second input electrode DE2 and the second output electrode SE2 are connected to a portion of the second semiconductor pattern OSP2 via third and fourth through holes CH3 and CH4, respectively, which penetrate the first and second insulating layers 10 and 20. On the other hand, in other embodiments, at least one of the first thin film transistor TR1 and the second thin film transistor TR2 may have a bottom gate structure.

[0132] The third insulating layer 30 is disposed on the second insulating layer 20 and covers the first input electrode DE1, the second input electrode DE2, the first output electrode SE1, and the second output electrode SE2. The third insulating layer 30 may provide a flat surface.

[0133] The display element layer DP-OLED is disposed on the third insulating layer 30. The display element layer DP-OLED may include a pixel defining layer PDL and an organic light emitting diode OLED. The pixel defining layer PDL may include an organic material. The first electrode AE ​​is disposed on the third insulating layer 30. The first electrode AE ​​is connected to the second output electrode SE2 via a fifth through hole CH5 penetrating the third insulating layer 30. An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a portion of the first electrode AE. In an embodiment of the present invention, the pixel defining layer PDL may be omitted.

[0134] The display area DA may include a pixel area (or light emitting area) PXA and a peripheral area (or non-light emitting area) NPXA adjacent to the pixel area PXA. The peripheral area NPXA may surround the pixel area PXA. In the illustrated embodiment, the pixel area PXA is defined to correspond to a partial area of ​​the first electrode AE ​​exposed by the opening OP.

[0135] In an embodiment of the present invention, the pixel area PXA may also overlap at least one of the first thin film transistor TR1 and the second thin film transistor TR2. The opening OP may be wider, and the first electrode AE ​​and the light emitting layer EML to be described later may also be wider.

[0136] The hole control layer HCL may be commonly disposed in the pixel region PXA and the peripheral region NPXA. Although not shown in the drawings, a common layer such as the hole control layer HCL may be commonly formed in the pixel region PXA and the peripheral region NPXA. Figure 3 In the pixel area PXA shown in .

[0137] The light emitting layer EML is disposed on the hole control layer HCL. The light emitting layer EML may be disposed in a region corresponding to the opening OP. In other words, the light emitting layers EML of the pixel regions PXA may be separated from each other. The light emitting layer EML may include an organic material and / or an inorganic material. The light emitting layer EML may generate light having a predetermined color.

[0138] In the illustrated embodiment, a patterned light emitting layer EML is shown as an example. However, in another embodiment, the light emitting layer EML may be disposed together as shown in FIG. Figure 3 In the pixel area PXA shown in FIG. 1 , the light emitting layer EML may generate white light. In addition, the light emitting layer EML may have a multi-layer structure called a “tandem”.

[0139] The electron control layer ECL is disposed on the light emitting layer EML. Although not shown in the drawings, the electron control layer ECL may be formed together with the light emitting layer EML. Figure 3 In the pixel area PXA shown in FIG. 1 , the second electrode NE is disposed on the electronic control layer ECL. The second electrode NE is disposed together as shown in FIG. Figure 3In the pixel area PXA shown in .

[0140] The thin film encapsulation layer TFE is disposed on the second electrode NE. The thin film encapsulation layer TFE is disposed on Figure 3 In the pixel area PXA shown in . In the embodiment shown, the thin film encapsulation layer TFE directly covers the second electrode NE. In the embodiment of the present invention, the capping layer covering the second electrode NE may be further disposed between the thin film encapsulation layer TFE and the second electrode NE. In this case, the thin film encapsulation layer TFE may directly cover the capping layer.

[0141] In an embodiment of the present invention, the organic light emitting diode OLED may further include a resonance structure for controlling the resonance distance of light generated from the light emitting layer EML. The resonance structure may be disposed between the first electrode AE ​​and the second electrode NE, and the thickness of the resonance structure may be determined according to the wavelength of light generated from the light emitting layer EML.

[0142] The second base substrate BS2 is spaced apart from the thin film encapsulation layer TFE. The second base substrate BS2 may include a glass substrate or a plastic substrate. In the illustrated embodiment, the second base substrate BS2 corresponds to the second display substrate 200. However, in another embodiment, each functional layer may be disposed on the top surface or the bottom surface of the second base substrate BS2.

[0143] like Fig.13 As shown in the figure, the thin film encapsulation layer TFE, the electron control layer ECL and the hole control layer HCL extend into the non-display area NDA. The insulating structure IS is disposed between the second base substrate BS2 and the first base substrate BS1. The side surface of the insulating structure IS is substantially aligned with the side surface BS1-S of the first base substrate BS1. In the illustrated embodiment, the insulating structure IS having a two-layer structure is shown as an example. However, the inventive concept is not limited thereto.

[0144] The first insulating structure IS1 and the second insulating structure IS2 of the insulating structure IS may be connected to the reference Figure 7 The first and second insulating structures IS1 and IS2 are described to be substantially the same. However, the inventive concept is not limited thereto. In other embodiments, each of the first and second insulating structures IS1 and IS2 may include an organic layer and may be variously modified.

[0145] The insulating structure IS is disposed between the uppermost surface of the first display substrate 100 and the lowermost surface of the second display substrate 200. In the illustrated embodiment, the uppermost surface of the first display substrate 100 corresponds to the top surface of the thin film encapsulation layer TFE, and the lowermost surface of the second display substrate 200 corresponds to the bottom surface of the second base substrate BS2. However, the inventive concept is not limited thereto. In another embodiment, the thin film encapsulation layer TFE, the electron control layer ECL, and the hole control layer HCL may not be disposed in the non-display area NDA, and the top surface of the pixel defining layer PDL may correspond to the uppermost surface of the first display substrate 100. The connection pad CP may be electrically connected to the pad DCB-P of the circuit substrate DCB through an anisotropic conductive film (ACF).

[0146] According to the above description, the connection pad can be provided on the side surface of the display panel, and thus, the circuit substrate can be connected to the side surface of the display panel. Because the connection area of ​​the circuit substrate and the display panel is defined on the side surface of the display panel, the non-display area can be reduced and the structural integrity can be improved.

[0147] Since the side surface of the insulating structure is substantially aligned with the side surface of the display panel and the side surface of the signal line, the signal line can be prevented from being damaged and / or deformed during a manufacturing process such as a grinding process. A contact area defined on the side surface of the signal line can be ensured, thereby reducing contact resistance between the circuit substrate and the display panel.

[0148] Although certain exemplary embodiments and examples have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those of ordinary skill in the art.

Claims

1. Display panel, including: A first substrate having a top surface and a side surface, wherein the top surface includes a display area and a non-display area surrounding the display area; a second substrate, facing the first substrate; a first insulating structure, disposed between the second substrate and the first substrate, wherein the first insulating structure overlaps the non-display area but does not overlap the display area; an organic light emitting diode, between the first substrate and the second substrate and overlapping the display area; A thin film encapsulation layer on the organic light emitting diode; a signal line having a side surface aligned with the side surface of the first substrate, wherein the signal line is disposed on the first substrate; a second insulating structure overlapping the signal line and disposed between the first substrate and the first insulating structure, wherein the second insulating structure has a side surface aligned with the side surface of the first substrate; a connection pad in contact with the side surface of the signal line; and a floating electrode overlapping the signal line and the second insulating structure, The second insulating structure includes an organic pattern that overlaps the signal line and the non-display area but does not overlap the display area.

2. The display panel according to claim 1, wherein: The first insulating structure and the second insulating structure are disposed on the thin film encapsulation layer.

3. The display panel according to claim 1, wherein: The second substrate is spaced apart from the thin film encapsulation layer.

4. The display panel according to claim 1, further comprising: a pixel defining layer on the first substrate, and Wherein, the first insulating structure and the second insulating structure are arranged on the pixel defining layer.

5. The display panel according to claim 1, further comprising: a thin film transistor electrically connected to the organic light emitting diode, and The signal line is arranged on the same layer as the control electrode of the thin film transistor.

6. The display panel according to claim 1, further comprising: A sealing member is disposed between the first substrate and the second substrate and is spaced apart from the organic pattern of the second insulating structure.

7. The display panel according to claim 1, in, The floating electrode is disposed between the signal line and the organic pattern of the second insulating structure.

8. The display panel according to claim 7, wherein: The floating electrode contacts the connection pad.

9. The display panel according to claim 7, further comprising: a thin film transistor electrically connected to the organic light emitting diode, and The floating electrode is arranged on the same layer as the input electrode or the output electrode of the thin film transistor.

10. The display panel according to claim 1, further comprising: A circuit substrate is electrically connected to the connection pads.

11. The display panel according to claim 1, wherein: The signal line includes copper, and the connection pad includes silver paste.

12. The display panel according to claim 1, wherein: The second insulating structure contacts the first insulating structure.

13. The display panel according to claim 1, wherein: The connection pad contacts the side surface of the first substrate and the side surface of the second insulating structure.

14. Display panel, comprising: A first substrate having a top surface and a side surface, wherein the top surface includes a display area and a non-display area outside the display area; A display element, disposed on the display area; a signal line having a side surface aligned with the side surface of the first substrate; an insulating layer, on the first substrate and overlapping the signal line; as well as an electrode having a side surface aligned with the side surface of the first substrate, The electrode is disposed on the insulating layer and overlaps with the signal line, and the electrode is floating.

15. The display panel according to claim 14, further comprising: A connection pad is in contact with the side surface of the signal line.

16. The display panel according to claim 15, wherein: The connection pad is in contact with the side surface of the electrode.

17. The display panel according to claim 15, further comprising: A circuit substrate is electrically connected to the connection pads.

18. The display panel according to claim 15, wherein: The signal line includes copper, and the connection pad includes silver paste.

19. The display panel according to claim 14, further comprising: a second substrate, facing the first substrate; A first insulating structure is provided between the second substrate and the first substrate; as well as The second insulating structure overlaps the signal line and is disposed between the first substrate and the first insulating structure.

20. The display panel according to claim 19, wherein: The first insulating structure overlaps the non-display area but does not overlap the display area.

21. The display panel according to claim 19, wherein: The second insulating structure has a side surface aligned with the side surface of the first substrate.

22. The display panel according to claim 21, wherein: The second insulating structure includes an organic pattern overlapping the non-display area but not overlapping the display area.

23. The display panel according to claim 22, wherein: The second insulating structure further includes an inorganic layer disposed on the organic pattern and overlapping the display area and the non-display area.

24. The display panel according to claim 19, further comprising: a sealing structure disposed between the first substrate and the second substrate, and Wherein, in a plan view, the sealing structure is arranged inside the second insulating structure.

25. The display panel according to claim 24, wherein: The sealing structure includes a layer different from a layer of the second insulating structure.

26. The display panel according to claim 19, further comprising: a connection pad in contact with the side surface of the signal line, and The connection pad is in contact with the side surface of the first substrate and the side surface of the second insulating structure.

27. The display panel according to claim 14, further comprising: A thin film transistor is electrically connected to the display element.

28. The display panel according to claim 27, wherein: The signal line is provided on the same layer as the control electrode of the thin film transistor.

29. The display panel according to claim 14, wherein: The display element includes an organic light emitting diode.

30. Display panel, comprising: a first substrate having a top surface and a side surface; a second substrate, facing the first substrate; A display element, between the first substrate and the second substrate; A sealing structure, disposed between the first substrate and the second substrate; an insulating structure disposed between the first substrate and the second substrate, wherein the insulating structure has a side surface aligned with the side surface of the first substrate and includes a layer different from a layer of the sealing structure; a signal line having a side surface aligned with the side surface of the first substrate, wherein the signal line is disposed on the first substrate and overlaps the insulating structure; an electrode having a side surface aligned with the side surface of the first substrate, The electrode is disposed on a layer different from the signal line and overlaps the signal line, and the electrode is floating.

31. The display panel according to claim 30, further comprising: A connection pad is in contact with the side surface of the signal line.

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