A narrow pulse detection and counting circuit

Abstract

The present invention relates to a narrow pulse detection and counting circuit, belonging to the field of integrated circuits. The present invention combines the methods of analog circuit design and digital circuit design. First, the analog circuit is used to filter out the narrow pulse signal, and then the signal before filtering out the narrow pulse is used to perform double-edge sampling on the signal after filtering out the narrow pulse. In essence, it is the input signal sampled at both edges after a delay. Then, an exclusive NOR operation is performed according to the sampling results. If the same signal is sampled at both edges, it indicates that a narrow pulse is detected, and a high level is output; on the contrary, if the double-edge detection results are different signals, it indicates that the detected signal is not a narrow pulse, and a low level is output. This method does not require a high-frequency sampling clock, and the detection delay is only the time of one narrow pulse. The detection output can be cascaded to realize the detection of multiple consecutive narrow pulses. The circuit implementation is simple and highly scalable. It can be freely cascaded to realize the customized detection and counting of consecutive narrow pulses.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits and relates to a narrow pulse detection and counting circuit. Background Art

[0002] In analog integrated circuits, the high and low levels of logic signals can represent different states, and the pulse width can be used to represent different information. In an on-off keying (OOK) modulation system, different pulse widths are used to represent different information to achieve the encoded transmission of different signals.

[0003] In a capacitive isolation type digital isolation chip, for a signal transmission system using OOK modulation and demodulation, it is necessary to be able to identify signals with different pulse widths, so as to decode different information. It is required to be able to detect and count the start and end times of narrow pulses with low latency, as well as the number of consecutive narrow pulses. The transmitted information is decoded by counting the number of narrow pulses.

[0004] Traditional pulse width detection and counting circuits require a high-frequency sampling clock. The frequency of this clock must be greater than at least twice the frequency of the sampled signal in order to identify and detect the signal with the minimum pulse width being transmitted. This not only increases the complexity of circuit design, but also has certain requirements for the frequency. Usually, within the time of one level state of the sampled signal, the periods of the sampling clock are counted. If the period is greater than the designed threshold, it is considered that the detected pulse width is a wide pulse; conversely, if the counted period is less than the threshold, it is considered that a narrow pulse is detected. If continuous narrow pulses are to be detected, a detection result register circuit is also required. This method uses the logic implementation of a pure digital circuit and requires a threshold counter and a high-frequency clock, and the circuit implementation is complex. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a narrow pulse detection and counting circuit.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A narrow pulse detection and counting circuit, the circuit comprising:

[0008] An input signal PWM_input, the input signal PWM_input containing narrow pulse and wide pulse information;

[0009] EN is the enable signal of the narrow pulse detection circuit. When EN is at a high level, the detection circuit enables to work. When EN is at a low level, the circuit does not work and the counter output is cleared;

[0010] PWM_Filt_OUT is the output signal of the filter circuit;

[0011] Unit narrow pulse detection circuit. A dashed box represents a detection unit that checks and counts the state of a narrow pulse.

[0012] Narrow pulse detection output 1 and narrow pulse detection output 2 indicate the state of the detected narrow pulse. When a narrow pulse is detected, a high level is output; otherwise, a low level is output.

[0013] Schmitt triggers ST1 and ST2 are used to reduce the power consumption of the intermediate state generated by the filtering of capacitor C and resistor R.

[0014] When the initial state of the input PWM_input is low, MN2 is turned on, the R terminal of the RS flip-flop is at a high level, and the output state is determined by the S terminal. At the same time, MN1 is turned off, and INV6 charges capacitor C1 through resistor R1. When the voltage of capacitor C1 is higher than the threshold voltage of the Schmitt trigger, the voltage at point S turns low and the PWM_Filt_OUT output turns low. Therefore, the low level of the output PWM_Filt_OUT is the delay of the low level of the input PWM_input, and the delay time is the time for resistor R1 and capacitor C1 to charge to the flip-flop threshold of Schmitt trigger ST1.

[0015] When the input PWM_input turns high, MN1 is turned on, the S terminal is at a high level, and the output state of the RS flip-flop is determined by the R terminal. At the same time, MN2 is turned off, and INV5 charges capacitor C2 through resistor R2. When the voltage of capacitor C2 is higher than the threshold voltage of the Schmitt trigger, the voltage at point R turns low and the PWM_Filt_OUT output turns high. Therefore, the high level of the output PWM_Filt_OUT is the delay of the high level of the input PWM_input, and the delay time is the time for resistor R2 and capacitor C2 to charge to the flip-flop threshold of Schmitt trigger ST2.

[0016] When the low - level time of the pulse of the input PWM_input is greater than the delay generated by the resistor R1 and the capacitor C1, and the high - level time of the pulse of the input PWM_input is greater than the delay generated by the resistor R2 and the capacitor C2, the output PWM_Filt_OUT is the delayed signal of the input PWM_input. If the delays of the high voltage and the low level are the same, then the pulse widths of PWM_Filt_OUT and PWM_input will be exactly the same, only the delays are different, and their edges are staggered; the rising edge of PWM_input will correspond to the low level of PWM_Filt_OUT, and the falling edge of PWM_input will correspond to the high level of PWM_Filt_OUT; using PWM_input as the clock signal, the rising edge samples PWM_Filt_OUT through the D - flip - flop DFF1, and the output is the low level; after passing through the inverter INV8, the falling edge of PWM_input will sample PWM_Filt_OUT through the D - flip - flop DFF2, and the output is the high level; the state of the low - level output of DFF1 remains unchanged, so the inputs of the XNOR gate XNOR1 are different values, and the output is the low level, indicating that no narrow pulse is detected;

[0017] When the low - level time of the pulse of the input PWM_input is less than the delay generated by the resistor R1 and the capacitor C1, and the high - level time of the pulse of the input PWM_input is less than the delay generated by the resistor R2 and the capacitor C2, the output PWM_Filt_OUT is the signal of the input PWM_input after filtering out the narrow pulse. The narrow - pulse time is not enough to cause the Schmitt triggers ST1 and ST2 to flip, and the state of the RS - flip - flop will maintain the original value and will not change; during the input of the narrow pulse of PWM_input, the output PWM_Filt_OUT will remain unchanged;

[0018] When the narrow - pulse detection output 1 turns high and is input to the EN terminal of the subsequent - stage single - unit narrow - pulse detection circuit, the enable is effective, and the second narrow pulse of PWM_input will be detected by the second detection unit, and the narrow - pulse detection output 2 turns high; two consecutive narrow pulses are detected and counted in sequence;

[0019] When a wider pulse is transmitted after the narrow pulse of PWM_input ends, the first single - unit narrow - pulse detection circuit will output a low level and simultaneously clear the subsequent cascaded single - unit narrow - pulse detection circuits.

[0020] Optionally, when PWM_Filt_OUT remains low, the rising edge of PWM_input will correspond to the low level of PWM_Filt_OUT, and the falling edge of PWM_input will also correspond to the low level of PWM_Filt_OUT; using PWM_input as the clock signal, the rising edge samples PWM_Filt_OUT through D flip-flop DFF1, and the output is low level; after passing through inverter INV8, the falling edge of PWM_input will sample PWM_Filt_OUT through D flip-flop DFF2, and the output is also low level; the inputs of exclusive-NOR gate XNOR1 are the same values, and the output is high level, indicating that a narrow pulse is detected. The narrow pulse detection output 1 is high level, and the detection delay is the time of one narrow pulse width; the detection result is output as soon as the narrow pulse ends.

[0021] The beneficial effects of the present invention are as follows: The present invention combines the methods of analog circuit design and digital circuit design. First, the analog circuit is used to filter out the narrow pulse signal, and then the signal before filtering out the narrow pulse is used to perform double-edge sampling on the signal after filtering out the narrow pulse. Essentially, it is the input signal sampled at both edges after a delay. Then, an exclusive-NOR operation is performed according to the sampling results. If the same signal is sampled at both edges, it indicates that a narrow pulse is detected and a high level is output; on the contrary, if the double-edge detection results are different signals, it indicates that the detected signal is not a narrow pulse and a low level is output. This method does not require a high-frequency sampling clock, the detection delay is only the time of one narrow pulse, the detection output can be cascaded to realize the detection of multiple consecutive narrow pulses, the circuit implementation is simple, and the scalability is extremely strong. It can be freely cascaded to realize custom continuous narrow pulse detection and counting.

[0022] Other advantages, objectives and features of the present invention will be described to some extent in the subsequent specification, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following specification. Brief Description of the Drawings

[0023] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be described in detail preferably with reference to the accompanying drawings, where:

[0024] Figure 1 It is the schematic diagram of the narrow pulse detection and counting circuit of the present invention;

[0025] Figure 2 It is the basic timing logic diagram in the present invention. Detailed Embodiments

[0026] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0027] Among them, the drawings are only for illustrative purposes, showing only schematic diagrams, not physical diagrams, and should not be construed as a limitation to the present invention; in order to better illustrate the embodiments of the present invention, some components in the drawings will be omitted, enlarged or reduced, which does not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0028] In the drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, they are based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the drawings are only for illustrative purposes and should not be construed as a limitation to the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0029] By filtering the input signal PWM_input for high and low levels to filter out the narrow pulse information carried by it, the filter circuit is implemented by R1 and C1 and R2 and C2, and then the PWM_Filt_OUT signal is output through the RS flip-flop circuit. The key narrow pulse detection and counting circuit is as Figure 1As shown by the dashed box, the implementation principle is to use the input PWM_input signal as the bilateral edge sampling clock. The sampling circuit is implemented by D flip-flops DFF1 and DFF2. Among them, DFF1 is used as the rising edge sampling circuit, and DFF2 is used as the falling edge sampling circuit, and simultaneously samples the PWM_Filt_OUT signal output by the filtering circuit. Then the sampling output passes through an exclusive-NOR gate to realize the output of the detection state. When a narrow pulse is detected, a high level is output, otherwise a low level is output. At the same time, the signal of narrow pulse detection output 1 can be used as the status signal output of detecting a narrow pulse, or can be used as the enable signal EN of the second narrow pulse detection unit. This realizes cascade expansion, which means that the output of the previous unit narrow pulse detection circuit can be used as the enable of the next unit narrow pulse detection circuit. In this way, when a narrow pulse is detected, then continue to detect the next narrow pulse to achieve continuous detection and counting. The unit narrow pulse detection circuit can be infinitely expanded to achieve infinite continuous narrow pulse detection and counting. At the same time, as long as the first narrow pulse detection unit does not detect the continuous state of the narrow pulse, a chain reaction will be triggered to clear all the cascaded detection units to achieve the purpose of synchronous clearing of the counter. In addition, the exclusive-NOR gate here requires different output signals to be low level. Therefore, when no narrow pulse is detected in the initial state, the initial states of the two edge sampling D flip-flops need to be different, that is, the initial state output of one D flip-flop is high level, and the initial state output of the other is low level. Only in this way can the initial state output be correct.

[0030] The specific narrow pulse detection and counting circuit is as Figure 1 shown, including: MN1, MN2, INV1~9, R1, R2, C1, C2, ST1, ST2, NAND1, NAND2, DFF1~DFF4, XNOR1, XNOR2.

[0031] As Figure 1 shown, the PWM_input in the circuit is the input signal, which contains narrow pulse and wide pulse information, and specific examples are as Figure 2 shown. Figure 1 The EN in it is the enable signal of the narrow pulse detection circuit. When EN is high level, the detection circuit enables to work. When EN is low level, the circuit does not work and the counter output is cleared. Figure 1 The PWM_Filt_OUT in it is the output signal of the filtering circuit, and specific examples are as Figure 2 shown. Figure 1 The circuit within the dashed box in it represents the unit narrow pulse detection circuit. One dashed box represents one detection unit, which can detect and count the status of one narrow pulse. This example only shows two detection units, and the actual cascade number can be customized according to needs. The narrow pulse detection output 1 and the narrow pulse detection output 2 represent the status of detecting a narrow pulse. When a narrow pulse is detected, a high level is output, otherwise a low level is output. Figure 1ST1 and ST2 in it are Schmitt triggers, whose function is to reduce the power consumption of the intermediate state generated by the filtering of capacitor C and resistor R.

[0032] When the initial state of the input PWM_input is low level, MN2 is turned on, the R terminal of the RS flip-flop is high level, the output state is determined by the S terminal. At the same time, MN1 is turned off, and INV6 charges the capacitor C1 through the resistor R1. When the voltage of the capacitor C1 is higher than the threshold voltage of the Schmitt trigger, the voltage at point S flips low and the PWM_Filt_OUT output flips low. Therefore, the low level of the output PWM_Filt_OUT is the delay of the low level of the input PWM_input, and the delay time is the time for the resistor R1 and the capacitor C1 to charge to the flip-flop threshold of the Schmitt trigger ST1.

[0033] When the input PWM_input flips high, MN1 is turned on, the S terminal is high level, the output state of the RS flip-flop is determined by the R terminal. At the same time, MN2 is turned off, and INV5 charges the capacitor C2 through the resistor R2. When the voltage of the capacitor C2 is higher than the threshold voltage of the Schmitt trigger, the voltage at point R flips low and the PWM_Filt_OUT output flips high. Therefore, the high level of the output PWM_Filt_OUT is the delay of the high level of the input PWM_input, and the delay time is the time for the resistor R2 and the capacitor C2 to charge to the flip-flop threshold of the Schmitt trigger ST2.

[0034] When the pulse low level time of the input PWM_input is greater than the delay generated by the resistor R1 and the capacitor C1, and the pulse high level time of the input PWM_input is greater than the delay generated by the resistor R2 and the capacitor C2, the output PWM_Filt_OUT is the delay signal of the input PWM_input. If the delays of the high voltage and the low level are the same, then the pulse widths of PWM_Filt_OUT and PWM_input will be exactly the same, only the delays are different, and their edges are staggered. The rising edge of PWM_input will correspond to the low level of PWM_Filt_OUT, and the falling edge of PWM_input will correspond to the high level of PWM_Filt_OUT. Therefore, using PWM_input as the clock signal, the rising edge samples PWM_Filt_OUT through the D flip-flop DFF1, and the output is low level. After passing through the inverter INV8, the falling edge of PWM_input will sample PWM_Filt_OUT through the D flip-flop DFF2, and the output is high level. And the state of the low level output by DFF1 remains unchanged. Therefore, the inputs of the XNOR gate XNOR1 are different values, and the output is low level. It also means that no narrow pulse is detected.

[0035] When the low - level time of the pulse of PWM_input is less than the delay generated by resistor R1 and capacitor C1, and the high - level time of the pulse of PWM_input is less than the delay generated by resistor R2 and capacitor C2, the output PWM_Filt_OUT is the signal after filtering out the narrow pulses of PWM_input. Because the narrow - pulse time is not long enough to cause the Schmitt triggers ST1 and ST2 to flip, the state of the RS flip - flop will remain the original value and will not change. Thus, during the input of narrow pulses of PWM_input, the output PWM_Filt_OUT will remain unchanged. Taking the case where PWM_Filt_OUT remains low (since the case of remaining high is the same), the rising edge of PWM_input will correspond to the low level of PWM_Filt_OUT, and the falling edge of PWM_input will also correspond to the low level of PWM_Filt_OUT. Thus, using PWM_input as the clock signal, the rising edge samples PWM_Filt_OUT through D - flip - flop DFF1, and the output is low level. After passing through inverter INV8, the falling edge of PWM_input will sample PWM_Filt_OUT through D - flip - flop DFF2, and the output is also low level. Thus, the inputs of exclusive - NOR gate XNOR1 are the same value, and the output is high level. That is to say, a narrow pulse is detected, the narrow - pulse detection output 1 is high level, and the detection delay is the time of one narrow - pulse width. Therefore, the detection delay is extremely low, and the detection result can be output immediately after the narrow pulse ends.

[0036] When the narrow - pulse detection output 1 turns high and is input to the EN terminal of the next - stage single - unit narrow - pulse detection circuit to enable it effectively, the second narrow pulse of PWM_input will be detected by the second detection unit, and the narrow - pulse detection output 2 turns high. So two consecutive narrow pulses can be detected and counted in sequence.

[0037] When a relatively wide pulse is transmitted after the narrow pulse of PWM_input ends, the first single - unit narrow - pulse detection circuit will output a low level and simultaneously clear the subsequent cascaded single - unit narrow - pulse detection circuits.

[0038] Through the analysis of the narrow - pulse detection and counting circuit, it can be seen that the narrow - pulse detection circuit proposed by the present invention has a simple implementation principle, an extremely short detection delay, strong scalability, can realize the detection and counting of continuous narrow pulses, and the function of automatic synchronous clearing.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the present technical solution, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A narrow pulse detection and counting circuit, characterized in that: The circuit includes: An input signal PWM_input, where the input signal PWM_input contains narrow pulse and wide pulse information; EN is the enable signal of the narrow pulse detection circuit. When EN is at a high level, the detection circuit enables operation. When EN is at a low level, the circuit does not work and the counter output is cleared; PWM_Filt_OUT is the output signal of the filter circuit; A unit narrow pulse detection circuit. A dashed box represents a detection unit that checks and counts the state of a narrow pulse; Narrow pulse detection output 1 and narrow pulse detection output 2 represent the state of the detected narrow pulse. When a narrow pulse is detected, a high level is output, otherwise a low level is output; Schmitt triggers ST1 and ST2, whose function is to reduce the power consumption of the intermediate state generated by the filtering of capacitor C and resistor R; When the initial state of the input PWM_input is low, MN2 is turned on, the R terminal of the RS flip-flop is at a high level, and the output state is determined by the S terminal. At the same time, MN1 is turned off, and INV6 charges capacitor C1 through resistor R1. When the voltage of capacitor C1 is higher than the threshold voltage of the Schmitt trigger, the voltage at point S turns low and the PWM_Filt_OUT output turns low. Therefore, the low level of the output PWM_Filt_OUT is the delay of the low level of the input PWM_input, and the delay time is the time for resistor R1 and capacitor C1 to charge to the inversion threshold of the Schmitt trigger ST1; When the input PWM_input turns high, MN1 is turned on, the S terminal is at a high level, and the output state of the RS flip-flop is determined by the R terminal. At the same time, MN2 is turned off, and INV5 charges capacitor C2 through resistor R2. When the voltage of capacitor C2 is higher than the threshold voltage of the Schmitt trigger, the voltage at point R turns low and the PWM_Filt_OUT output turns high. Therefore, the high level of the output PWM_Filt_OUT is the delay of the high level of the input PWM_input, and the delay time is the time for resistor R2 and capacitor C2 to charge to the inversion threshold of the Schmitt trigger ST2; When the low - level time of the pulse of the input PWM_input is greater than the delay generated by the resistor R1 and the capacitor C1, and the high - level time of the pulse of the input PWM_input is greater than the delay generated by the resistor R2 and the capacitor C2, the output PWM_Filt_OUT is the delayed signal of the input PWM_input. If the delays of the high voltage and the low level are the same, then the pulse widths of PWM_Filt_OUT and PWM_input will be exactly the same, only the delays are different, and their edges are staggered; the rising edge of PWM_input will correspond to the low level of PWM_Filt_OUT, and the falling edge of PWM_input will correspond to the high level of PWM_Filt_OUT; using PWM_input as the clock signal, the rising edge samples PWM_Filt_OUT through the D - flip - flop DFF1, and the output is low level; after passing through the inverter INV8, the falling edge of PWM_input will sample PWM_Filt_OUT through the D - flip - flop DFF2, and the output is high level; the state of the low - level output of DFF1 remains unchanged, so the inputs of the XNOR gate XNOR1 are different values, and the output is low level, indicating that no narrow pulse is detected; When the low - level time of the pulse of the input PWM_input is less than the delay generated by the resistor R1 and the capacitor C1, and the high - level time of the pulse of the input PWM_input is less than the delay generated by the resistor R2 and the capacitor C2, the output PWM_Filt_OUT is the signal of the input PWM_input after filtering out the narrow pulse. The narrow - pulse time is not sufficient to cause the Schmitt triggers ST1 and ST2 to flip, and the state of the RS - flip - flop will remain the original value and will not change; during the input of the narrow pulse of PWM_input, the output PWM_Filt_OUT will remain unchanged; When the narrow - pulse detection output 1 turns high and is input to the EN terminal of the next - stage single - unit narrow - pulse detection circuit, enabling is effective, and the second narrow pulse of PWM_input will be detected by the second detection unit, and the narrow - pulse detection output 2 turns high; two consecutive narrow pulses are detected and counted in sequence; When a wider pulse is transmitted after the narrow pulse of PWM_input ends, the first single - unit narrow - pulse detection circuit will output a low level and simultaneously clear the subsequent cascaded single - unit narrow - pulse detection circuits.

2. The narrow pulse detection and counting circuit according to claim 1, characterized in that: When the PWM_Filt_OUT remains low, the rising edge of PWM_input will correspond to the low level of PWM_Filt_OUT, and the falling edge of PWM_input also corresponds to the low level of PWM_Filt_OUT; using PWM_input as the clock signal, the rising edge samples PWM_Filt_OUT through the D flip-flop DFF1, and the output is low level; after passing through the inverter INV8, the falling edge of PWM_input will sample PWM_Filt_OUT through the D flip-flop DFF2, and the output is also low level; the inputs of the XNOR gate XNOR1 are the same values, and the output is high level, indicating that a narrow pulse is detected. The narrow pulse detection output 1 is high level, and the detection delay is the time of one narrow pulse width; the detection result is output as soon as the narrow pulse ends.

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