A gate drive circuit, a pixel circuit, and an active light-emitting type active display

Abstract

The application discloses a kind of gate drive circuit, pixel circuit and active light-emitting active display, wherein gate drive circuit includes cascaded shift register module and the drive module connected with shift register module, wherein drive module includes scan signal generation module and light-emitting control signal generation module;Shift register module is used to generate stage signal under the control of clock signal, and the level of stage signal output control end and the level of programming signal control end are programmed control;Scan signal generation module is used to output scan signal under the control of the level of stage signal output control end and the level of programming signal control end;Light-emitting control signal generation module is used to output light-emitting control signal under the control of the level of stage signal output control end.The gate drive circuit provided by the application can output programmable scan signal and light-emitting control signal simultaneously in a level gate drive circuit, which is matched with pixel circuit to realize digital PWM subframe light-emitting.

Description

Technical Field

[0001] This invention relates to the field of display device technology, and in particular to a gate driving circuit, a pixel circuit, and an active-matrix display. Background Technology

[0002] Miniature LED displays possess advantages such as self-illumination, ultra-high brightness, long lifespan, low power consumption, and thin and light size, and are considered to have the potential to surpass traditional displays and become a disruptive future display technology. The field of miniature LED displays is currently expanding into various wearable, IoT, and biomedical applications, such as virtual reality (VR), smartwatches, and medical sensors. Miniature LED displays (MLED) are further divided into Mini-LED and Micro-LED displays. In Mini-LEDs, the LED chip size is approximately 50-100 μm, while in Micro-LEDs, the LED chip size is approximately 1-50 μm. Although both miniature LEDs and organic light-emitting diodes (OLEDs) are current-driven devices, miniature LED displays have distinct characteristics: the IV characteristic of miniature LEDs is very steep, their luminous efficiency is only high at appropriate current densities, and the wavelength of the emitted light varies with current density. If traditional pulse amplitude modulation (PAM) dimming is used, which converts the voltage signal input to the gate of the driving transistor into a current signal to achieve grayscale modulation, the digital programming range will be limited, causing a shift in the emission wavelength, and the display effect will be severely affected at low grayscale and low current levels. In order to accurately control the display grayscale, pulse width modulation (PWM) is generally used, where the brightness is proportional to the conduction time of the display driving TFT, to ensure the display effect.

[0003] Existing PWM driving schemes supporting micro LED displays are mainly divided into analog PWM driving and digital PWM driving. Digital PWM driving divides a frame into multiple subframes, each with a proportional duration. Linear grayscale is achieved by programming each subframe, requiring adjustable pulse widths for the light-emitting control signal to encode the subframes. However, in current technologies, the light-emitting control signal is primarily generated by an external driving chip, or based on a simultaneous light-emitting mode, making the light-emitting control signal a globally generated signal, with the gate driving circuit only needing to generate the serially transmitted scan pulses. The additional light-emitting control signal generation chip increases cost, makes it difficult to achieve narrow bezels, and significantly reduces luminous efficiency.

[0004] Miniature light-emitting diodes typically operate at high currents (on the order of 10μA-10mA, especially Mini-LED pixels), and the aspect ratio of transistors in pixel circuits is generally large. This significantly increases the load on the gate drive circuit. The gate drive circuit struggles to maintain sufficiently strong driving capability to ensure high frame rate display effects. Therefore, it is necessary to provide improved technical solutions to overcome the aforementioned technical problems in the existing technology. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a gate driving circuit, a pixel circuit, and an active light-emitting display, which can simultaneously output multiple types of programmable scanning signals and light emission control signals in a primary gate driving circuit, and cooperate with the pixel circuit to realize digital PWM subframe light emission, reduce the layout area, and improve the driving capability.

[0006] This invention provides a gate driving circuit, including a cascaded shift register module and a driving module connected to the shift register module. The driving module includes a scan signal generation module and a light emission control signal generation module. The shift register module includes a cascade signal output control terminal and a programming signal control terminal. The shift register module generates a cascade signal under the control of a clock signal and programs the levels of the cascade signal output control terminal and the programming signal control terminal. The scan signal generation module is connected to the cascade signal output control terminal and the programming signal control terminal, and outputs a scan signal under the control of the levels of the cascade signal output control terminal and the programming signal control terminal. The light emission control signal generation module is connected to the cascade signal output control terminal and outputs a light emission control signal under the control of the level of the cascade signal output control terminal.

[0007] Further, the shift register module includes a first pre-charge unit, a current-stage cascade signal output unit, a programming unit, and a first pull-down unit; the first pre-charge unit is used to charge the cascade signal output control terminal under the control of the previous stage cascade signal; the current-stage cascade signal output unit is used to output the current-stage cascade signal under the control of the level of the cascade signal output control terminal; the programming unit is used to program the pull-down and pull-up times of the level of the programming signal control terminal by the number of pulses of the input previous stage cascade signal; the first pull-down unit is used to pull down the level of the cascade signal output control terminal to a first low level under the control of the level of the programming signal control terminal, and reset the output current-stage cascade signal to a second low level, wherein the level value of the first low level is greater than the level value of the second low level.

[0008] Furthermore, the first pre-charge unit includes a first pre-charge control transistor and a first bootstrap capacitor; the control terminal of the first pre-charge control transistor is connected to the first path terminal of the first pre-charge control transistor and connected to the previous stage transmission signal; the second path terminal of the first pre-charge control transistor is connected to the first terminal of the first bootstrap capacitor to form the stage transmission signal output control terminal; the second terminal of the first bootstrap capacitor is connected to the current stage transmission signal output unit and the first pull-down unit.

[0009] Furthermore, the local cascade signal output unit includes a local cascade signal output transistor; the control terminal of the local cascade signal output transistor is connected to the cascade signal output control terminal, the first path terminal of the local cascade signal output transistor is connected to a first clock signal, and the second path terminal of the local cascade signal output transistor is connected to the second terminal of the first bootstrap capacitor and outputs the local cascade signal.

[0010] Further, the programming unit includes a first programming control transistor, a second programming control transistor, a third programming control transistor, a fourth programming control transistor, a reset control transistor, and a second capacitor; the control terminal of the first programming control transistor is connected to the subsequent stage transmission signal, the first path terminal of the first programming control transistor is connected to the control terminal of the fourth programming control transistor and connected to a second clock signal, the second path terminal of the first programming control transistor is connected to the control terminal of the second programming control transistor and the first path terminal of the second programming control transistor; the second path terminal of the second programming control transistor is connected to the first path terminal of the fourth programming control transistor and the first path terminal of the third programming control transistor; the control terminal of the third programming control transistor is connected to the preceding stage transmission signal, the second path terminal of the third programming control transistor is connected to the second terminal of the second capacitor and connected to a second low level; the second path terminal of the fourth programming control transistor is connected to the first terminal of the second capacitor to form the programming signal control terminal; the control terminal of the reset control transistor is connected to a reset signal, the first path terminal of the reset control transistor is connected to a global high level, and the second path terminal of the reset control transistor is connected to the programming signal control terminal.

[0011] Further, the first pull-down unit includes a first pull-down transistor and a second pull-down transistor; the control terminal of the first pull-down transistor is connected to the programming signal control terminal, the first path terminal of the first pull-down transistor is connected to the stage transmission signal output control terminal, and the second path terminal of the first pull-down transistor is connected to the first low level; the control terminal of the second pull-down transistor is also connected to the programming signal control terminal, the first path terminal of the second pull-down transistor is connected to the second terminal of the first bootstrap capacitor and the second path terminal of the stage transmission signal output transistor, and the second path terminal of the second pull-down transistor is connected to the second low level.

[0012] Furthermore, the scan signal generation module includes a second pre-charge unit, a current-level scan signal output unit, a second pull-down unit, and a sustaining unit; the second pre-charge unit is used to charge the scan signal output control terminal under the control of the previous-level scan signal; the current-level scan signal output unit is used to output the current-level scan signal under the control of the level of the scan signal output control terminal; the second pull-down unit is used to pull down the level signal of the scan signal output control terminal and the output current-level scan signal to a first low level under the control of the next-level scan signal, so that the current-level scan signal outputs a single positive pulse; the sustaining unit is used to maintain the level of the scan signal output control terminal and the output current-level scan signal at the first low level under the control of the level of the programming signal control terminal.

[0013] Furthermore, the second pre-charge unit includes a second pre-charge control transistor and a third bootstrap capacitor; the control terminal of the second pre-charge control transistor is connected to the previous stage scan signal, the first path terminal of the second pre-charge control transistor is connected to the stage signal output control terminal, and the second path terminal of the second pre-charge control transistor is connected to the first terminal of the third bootstrap capacitor to form the scan signal output control terminal; the second terminal of the third bootstrap capacitor is connected to the current stage scan signal output unit, the second pull-down unit, and the sustaining unit.

[0014] Furthermore, the local scan signal output unit includes a local scan signal output transistor; the control terminal of the local scan signal output transistor is connected to the scan signal output control terminal, the first path terminal of the local scan signal output transistor is also connected to the third clock signal, and the second path terminal of the local scan signal output transistor is connected to the second terminal of the third bootstrap capacitor and outputs the local scan signal.

[0015] Furthermore, the sustaining unit includes a third pull-down transistor and a fourth pull-down transistor; the control terminal of the third pull-down transistor is connected to the control terminal of the fourth pull-down transistor and is also connected to the programming signal control terminal; the first path terminal of the third pull-down transistor is connected to the scan signal output control terminal; the second path terminal of the third pull-down transistor is connected to the second path terminal of the fourth pull-down transistor and is connected to a first low-level signal; the first path terminal of the fourth pull-down transistor is connected to the second terminal of the third bootstrap capacitor and the second path terminal of the scan signal output transistor of this stage.

[0016] Furthermore, the second pull-down unit includes a fifth pull-down transistor and a sixth pull-down transistor; the control terminal of the fifth pull-down transistor is connected to the control terminal of the sixth pull-down transistor and connected to the subsequent stage scan signal; the first path terminal of the fifth pull-down transistor is connected to the second terminal of the third bootstrap capacitor and the second path terminal of the current stage scan signal output transistor; the second path terminal of the fifth pull-down transistor is connected to the second path terminal of the sixth pull-down transistor and connected to a first low-level signal; the first path terminal of the sixth pull-down transistor is connected to the scan signal output control terminal.

[0017] Furthermore, the light emission control signal generation module includes a first-stage inverter and a second-stage inverter; the first-stage inverter includes a first input transistor and a first control transistor, and the first-stage inverter includes a second input transistor, a second control transistor, a first light emission control signal output transistor, and a second light emission control signal output transistor;

[0018] The control terminal of the first input transistor is connected to the stage signal output control terminal. The first path terminal of the first input transistor is connected to the second path terminal of the first control transistor, the control terminal of the second input transistor, and the control terminal of the first light-emitting control signal output transistor. The second path terminal of the first input transistor is connected to a second low-level signal. The first path terminal of the second input transistor is connected to the second path terminal of the second control transistor and the control terminal of the second light-emitting control signal output transistor. The second path terminal of the second input transistor is connected to the second path terminal of the first light-emitting control signal output transistor and connected to a first low-level signal. The control terminal of the first control transistor is connected to the first path terminal of the first control transistor and connected to the global high-level signal. The control terminal of the second control transistor is connected to the first path terminal of the second control transistor and connected to the global high-level signal. The first path terminal of the first light-emitting control signal output transistor is connected to the second path terminal of the second light-emitting control signal output transistor and outputs the light-emitting control signal of this stage. The first path terminal of the second light-emitting control signal output transistor is connected to the global high-level signal.

[0019] The present invention also provides a pixel circuit for receiving a scanning signal and a light emission control signal output by the gate driving circuit as described above, so as to perform light emission control of the pixel circuit. The pixel circuit includes a data input transistor, a first reference transistor, a first storage capacitor, a second storage capacitor, a PWM driving transistor, a light emission control transistor, a PAM driving transistor, a second reference transistor, an initialization transistor, a threshold compensation transistor, and a miniature light-emitting diode.

[0020] The control terminal of the data input transistor is connected to the next stage scan signal. The first path terminal of the data input transistor is connected to the data voltage. The second path terminal of the data input transistor is connected to the second path terminal of the first reference transistor, the second terminal of the first storage capacitor, and the control terminal of the PWM drive transistor. The control terminal of the first reference transistor is connected to the current stage scan signal, and the first path terminal of the first reference transistor is connected to a first low level. The first terminal of the first storage capacitor is connected to the first path terminal of the PWM drive transistor and the first terminal of the second storage capacitor and is connected to a global high level. The control terminal of the light-emitting control transistor is connected to the next two stages of light-emitting control signals. The first path terminal of the light-emitting control transistor is connected to the second path terminal of the second reference transistor and the second path terminal of the PAM drive transistor. The second path terminal of the light-emitting control transistor... The terminal of the PAM driving transistor is connected to the anode of the micro LED; the control terminal of the PAM driving transistor is connected to the first path terminal of the initialization transistor and the second path terminal of the threshold compensation transistor, and the first path terminal of the PAM driving transistor is connected to the first path terminal of the threshold compensation transistor; the control terminal of the second reference transistor is connected to the current stage scan signal, and the first path terminal of the second reference transistor is connected to the reference voltage; the control terminal of the initialization transistor is connected to the previous stage scan signal, and the second path terminal of the initialization transistor is connected to the initialization voltage; the control terminal of the threshold compensation transistor is connected to the current stage scan signal, and the first path terminal of the threshold compensation transistor is connected to the second path terminal of the PWM driving transistor, and the second path terminal of the threshold compensation transistor is connected to the second terminal of the second storage capacitor; the cathode of the micro LED is connected to the first low level.

[0021] The present invention also provides an active light-emitting display, including the gate driving circuit and pixel circuit as described above.

[0022] The gate driving circuit, pixel circuit, and active-matrix display provided by this invention can integrate the shift register module, scan signal generation module, and light emission control signal generation module into a single-stage gate driving circuit. This allows the scan signal and light emission control signal to be generated synchronously and in parallel with the stage transmission signal. At the same time, the pulse width of the light emission control signal can be programmed. This works in conjunction with the pixel circuit to achieve digital PWM subframe light emission, reducing the layout area of ​​the active-matrix display and improving the stability and driving capability of the circuit. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of the circuit structure of a gate driving circuit provided in one embodiment;

[0025] Figure 2 A timing diagram of the gate drive circuit provided in one embodiment;

[0026] Figure 3 A schematic diagram of the circuit structure of a shift register module provided in one embodiment;

[0027] Figure 4 This is a schematic diagram of the circuit structure of a scanning signal generation module provided in one embodiment;

[0028] Figure 5 A schematic diagram of the circuit structure of a light emission control signal generation module provided in one embodiment;

[0029] Figure 6 A schematic diagram of a pixel circuit structure provided in one embodiment;

[0030] Figure 7 A timing diagram of a pixel circuit provided in one embodiment;

[0031] Figure 8 This is a cascaded block diagram of a gate drive circuit and a pixel circuit provided in one embodiment. Detailed Implementation

[0032] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the present invention; some well-known parts may not be shown. In the various drawings, the same elements are represented by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0033] One embodiment of the present invention provides a gate driving circuit, such as Figure 1 As shown, it includes a cascaded shift register module 110 and a driver module connected to the shift register module 110, wherein the driver module includes a scan signal generation module 120 and a light emission control signal generation module 130.

[0034] The shift register module 110 includes a cascade signal output control terminal Qa and a programming signal control terminal Qc. The shift register module 110 is used to generate a cascade signal under the control of a clock signal and to program and control the level of the cascade signal output control terminal Qa and the level of the programming signal control terminal Qc. The scan signal generation module 120 is connected to the cascade signal output control terminal Qa and the programming signal control terminal Qc and is used to output a scan signal under the control of the level of the cascade signal output control terminal Qa and the level of the programming signal control terminal Qc. The light emission control signal generation module 130 is connected to the cascade signal output control terminal Qa and is used to output a light emission control signal under the control of the level of the cascade signal output control terminal Qa.

[0035] like Figure 3 The circuit structure of the shift register module shown is as follows: the shift register module 110 includes a first precharge unit 111, a current stage transmission signal output unit 112, a programming unit 113, and a first pull-down unit 114. The first precharge unit 111 is used to charge the transmission signal output control terminal Qa under the control of the previous stage transmission signal C[n-1]. The current stage transmission signal output unit 112 is used to output the current stage transmission signal C[n] under the control of the level of the transmission signal output control terminal Qa. The programming unit 113 is used to program the pull-down and pull-up times of the programming signal control terminal Qc by the number of pulses of the input previous stage transmission signal C[n-1]. The first pull-down unit 114 is used to pull down the level of the transmission signal output control terminal Qa to a first low level VSS under the control of the level of the programming signal control terminal Qc, and reset the output current stage transmission signal C[n] to a second low level VSSL, wherein the level value of the first low level VSS is greater than the level value of the second low level VSSL.

[0036] Specifically, the first pre-charge unit 111 includes a first pre-charge control transistor T1a and a first bootstrap capacitor C1a; the control terminal of the first pre-charge control transistor T1a is connected to the first path terminal of the first pre-charge control transistor T1a and connected to the previous stage transmission signal C[n-1]; the second path terminal of the first pre-charge control transistor T1a is connected to the first terminal of the first bootstrap capacitor C1a to form the stage transmission signal output control terminal Qa; the second terminal of the first bootstrap capacitor C1a is connected to the current stage transmission signal output unit 112 and the first pull-down unit 114.

[0037] Specifically, the current stage transmission signal output unit 112 includes a current stage transmission signal output transistor T4a; the control terminal of the current stage transmission signal output transistor T4a is connected to the transmission signal output control terminal Qa, the first path terminal of the current stage transmission signal output transistor T4a is connected to the first clock signal CK1, and the second path terminal of the current stage transmission signal output transistor T4a is connected to the second terminal of the first bootstrap capacitor C1a and outputs the current stage transmission signal C[n].

[0038] Specifically, the programming unit 113 includes a first programming control transistor T2a, a second programming control transistor T3a, a third programming control transistor T7a, a fourth programming control transistor T8a, a reset control transistor T9a, and a second capacitor C2a. The control terminal of the first programming control transistor T2a is connected to the subsequent stage transmission signal. The first path terminal of the first programming control transistor T2a is connected to the control terminal of the fourth programming control transistor T8a and connected to the second clock signal CK2. The second path terminal of the first programming control transistor T2a is connected to the control terminal of the second programming control transistor T3a and the first path terminal of the second programming control transistor T3a. The second path terminal of the second programming control transistor T3a is connected to the fourth programming control transistor T8a. The first path terminal of the programming control transistor T8a is connected to the first path terminal of the third programming control transistor T7a; ​​the control terminal of the third programming control transistor T7a is connected to the previous stage transmission signal C[n-1], and the second path terminal of the third programming control transistor T7a is connected to the second terminal of the second capacitor C2a and connected to the second low level VSSL; the second path terminal of the fourth programming control transistor T8a is connected to the first terminal of the second capacitor C2a to form the programming signal control terminal Qc; the control terminal of the reset control transistor T9a is connected to the reset signal RST, the first path terminal of the reset control transistor T9a is connected to the global high level VDD, and the second path terminal of the reset control transistor T9a is connected to the programming signal control terminal Qc.

[0039] Specifically, the first pull-down unit 114 includes a first pull-down transistor T5a and a second pull-down transistor T6a; the control terminal of the first pull-down transistor T5a is connected to the programming signal control terminal Qc, the first path terminal of the first pull-down transistor T5a is connected to the stage transfer signal output control terminal Qa, and the second path terminal of the first pull-down transistor T5a is connected to the first low level VSS; the control terminal of the second pull-down transistor T6a is also connected to the programming signal control terminal Qc, the first path terminal of the second pull-down transistor T6a is connected to the second terminal of the first bootstrap capacitor C1a and the second path terminal of the stage transfer signal output transistor T4a of this stage, and the second path terminal of the second pull-down transistor T6a is connected to the second low level VSSL.

[0040] Please refer to Figure 2 the working timing diagram of the gate driving circuit shown in Figure 3 to explain in detail the working principle of the shift register module 110 shown in. In some embodiments, multiple shift register modules are cascaded with each other to achieve the stage transfer of continuous pulses, that is, when M pulses are input to the (n - x)-th stage, the n-th stage also outputs M pulses, and the phase difference between the output pulse signals of two interconnected stages is the width of one pulse. The stage transfer signal C[n - 1] of the previous stage shift register module and the stage transfer signal C[n + 1] of the next stage shift register module, as well as the first clock signal CK1 and the second clock signal CK2, are respectively input between adjacent shift register modules for outputting the stage transfer signal C[n] of this stage. For the shift register module of the n-th stage, it has five working states during the process of outputting the stage transfer signal C[n] of this stage, which are P1a, P2a, P3a, P4a, and P5a respectively. The following specifically describes the five working states of the shift register module.

[0041] It should be noted that the period of the clock signal used to generate the stage transfer signal of this stage is T1, and the ratio of the effective level time to the clock period is k1 (0 < k1 < 1). Taking the two-phase non-overlapping clock (CK1, CK2) with a period of T1 and a duty cycle of 50% as an example for illustrative purposes.

[0042] P1a state: The reset signal RST is a global high level VDD, which controls the reset control transistor T9a to be in the on state. The on reset control transistor T9a provides the global high level VDD to the first terminal of the second capacitor C2a and the control terminals of the first pull-down transistor T5a and the second pull-down transistor T6a. At this time, the programming signal control terminal, i.e., the level of the second stage transmission node Qc, is pulled high to the global high level VDD, which makes the first pull-down transistor T5a and the second pull-down transistor T6a of the first pull-down unit 114 in the on state. The on pull-down transistor T5a provides the first low level VSS to the control terminal of the stage transmission signal output transistor T4a and the first terminal of the first bootstrap capacitor C1a, and resets the stage transmission signal output control terminal, i.e., the first stage transmission node Qa, to the first low level VSS. The on pull-down transistor T6a resets the output terminal of the stage transmission signal C[n] to the second low level VSSL, which is lower than the first low level VSS.

[0043] At this time, the previous stage transmission signal C[n-1] and the next stage transmission signal C[n+1] are both at the second low level VSSL, controlling the first precharge control transistor T1a, the first programming control transistor T2a, the second programming control transistor T3a and the third programming control transistor T7a to be in the off state; at this time, the second clock signal CK2 is also at the second low level VSSL, controlling the fourth programming control transistor T8a to also be in the off state.

[0044] P2a state: The reset signal RST becomes the second low level VSSL, controlling the reset control transistor T9a to be in the off state; at this time, the second clock signal CK2 becomes the global high level VDD, controlling the fourth programming control transistor T8a to be in the on state; the previous stage transmission signal C[n-1] also becomes the global high level VDD, controlling the first precharge control transistor T1a and the third programming control transistor T7a to be in the on state. The on fourth programming control transistor T8a provides the second low level VSSL to the second stage transmission node Qc through the on third programming control transistor T7a, so that the level of the second stage transmission node Qc is pulled down to the second low level VSSL, thereby turning off the first pull-down transistor T5a and the second pull-down transistor T6a of the first pull-down unit 114. Since the first precharge control transistor T1a enters saturation conduction at this time, the voltage of the first stage transmission node Qa becomes the first precharge level VD1 = VSS + Vth (Vth is the threshold voltage of the first precharge control transistor T1a). Charge is stored through the first bootstrap capacitor C1a to maintain the potential of the first stage transmission node Qa, and the stage transmission signal output transistor T4a is turned on. Thus, the first clock signal CK1 is output to the output terminal of the stage transmission signal C[n] through the stage transmission signal output transistor T4a. Since the first clock signal CK1 is at the second low level VSSL, the output of the stage transmission signal C[n] is also at the second low level VSSL.

[0045] P3a state: At this time, both the previous stage transmission signal C[n-1] and the next stage transmission signal C[n+1] are at the second low level VSSL, causing the first precharge control transistor T1a, the first programming control transistor T2a, the second programming control transistor T3a, and the third programming control transistor T7a to be in the off state. The second clock signal CK2 also becomes the second low level VSSL, controlling the fourth programming control transistor T8a to also be in the off state. The reset signal RST is still at the second low level VSSL, causing the reset control transistor T9a to remain in the off state. The level of the second stage transmission node Qc remains at the second low level VSSL state, so the first pull-down transistor T5a and the second pull-down transistor T6a of the first pull-down unit 114 are also in the off state; due to the bootstrap effect of the first bootstrap capacitor C1a, the transmission signal output transistor T4a of this stage is in the linear region. At this time, the potential of the first stage transmission node Qa becomes the second precharge level VD2, which is higher than the first precharge level VD1. Since the first clock signal CK1 is the global high level VDD, the transmission signal C[n] output of this stage is the global high level VDD.

[0046] P4a State: After P3a state, if the stage pass signal C[n-1] of the previous stage shift register module and the stage pass signal C[n+1] of the next stage shift register module are both globally high (VDD), then the system will enter P4a state. At this time, the first precharge control transistor T1a, the first programming control transistor T2a, and the third programming control transistor T7a are in the on state. Since the second clock signal CK2 is also globally high (VDD), it controls the fourth programming control transistor T8a to turn on. The on first programming control transistor T2a provides the globally high (VDD) to the control terminal and the first path terminal of the second programming control transistor T3a, causing the second programming control transistor T3a to turn on. The on third programming control transistor... T7a provides the second low level VSSL to the second stage transmission node Qc, so that the level of the second stage transmission node Qc remains at the second low level VSSL. Therefore, the first pull-down transistor T5a and the second pull-down transistor T6a of the first pull-down unit 114 are still in the off state. Since the first precharge control transistor T1a enters the saturation conduction state at this time, the voltage of the first stage transmission node Qa becomes the first precharge level VD1 = VSS + Vth again, and stores charge through the first bootstrap capacitor C1a to maintain the potential of the first stage transmission node Qa, and turns on the transmission signal output transistor T4a of this stage, so that the first clock signal CK1 is output to the output terminal of the transmission signal C[n] of this stage through the transmission signal output transistor T4a. At this time, since the first clock signal CK1 is the second low level VSSL, the output of the transmission signal C[n] of this stage is the second low level VSSL.

[0047] At this time, since the previous stage transmission signal C[n+1] and the next stage transmission signal C[n+1] are both at the second low level VSSL again, after the P4a state, it will enter the P3a state again, so that the current stage transmission signal C[n] will output a global high level VDD once again.

[0048] P5a State: After P3a state, if the output of the previous stage transmission signal C[n-1] is the second low level VSS, and the output of the next stage transmission signal C[n+1] is the global high level VDD, then P5a state will be entered. At this time, the first programming control transistor T2a is in the on state. Since the second clock signal CK2 is the global high level VDD, it controls the fourth programming control transistor T8a to be turned on. The turned-on first programming control transistor T2a provides the global high level VDD to the control terminal and the first path terminal of the second programming control transistor T3a, causing the second programming control transistor T3a to be turned on. The turned-on second programming control transistor T3a provides the global high level VDD to the first path terminal of the fourth programming control transistor T8a. The turned-on fourth programming control transistor T8a provides the global high level VDD to the first path terminal of the fourth programming control transistor T8a. DD is provided to the second-stage transmission node Qc. The level of the second-stage transmission node Qc is pulled high again to the global high level VDD, so that the first pull-down transistors T5a and T6a of the first pull-down unit 114 are turned on again. The turned-on first pull-down transistor T5a provides the first low level VSS to the control terminal of the transmission signal output transistor T4a and the first terminal of the first capacitor, that is, the first-stage transmission node Qa is reset to the first low level VSS. The turned-on T6a resets the output terminal of the transmission signal C[n] of this stage to the second low level VSSL, thereby ending the output of the transmission signal of this stage.

[0049] As can be seen from the working principle of the first pre-charge unit 111 and the stage transmission signal output unit 112, the first pre-charge unit 111 outputs a first pre-charge level VD1 or a second pre-charge level VD2 through the first stage transmission node Qa. Both the first pre-charge level VD1 and the second pre-charge level VD2 are greater than the global low level, i.e., the first low level VSS, and less than the global high level VDD. The stage transmission signal output transistor T4a is turned on under the control of the first pre-charge level VD1 or the second pre-charge level VD2, so that the stage transmission signal C[n] output to the stage transmission signal output terminal follows the level of the first clock signal CK1.

[0050] As can be seen from the working principle of the shift register module described above, when the shift register module receives only one pulse, each shift register module sequentially goes through states P1a, P2a, P3a, and P5a to achieve single-pulse cascade signal output. When the shift register module receives multiple pulses, each shift register module repeatedly goes through states P3a and P4a according to the number of pulses to achieve multi-pulse scan signal output. The number of cascade signal pulses input from the previous stage shift register module is used to program the timing of the pull-up of the programming signal control terminal, i.e., the second-stage transmission node Qc, thereby changing the duration of the high-level pulse width of the cascade signal output control terminal, i.e., the first-stage transmission node Qa, and thus changing the number of pulses output by the current stage cascade signal C[n].

[0051] like Figure 4 The circuit structure of the scan signal generation module shown is as follows: the scan signal generation module 120 includes a second pre-charge unit 121, a current-stage scan signal output unit 122, a second pull-down unit 124, and a sustaining unit 123. The second pre-charge unit 121 is used to charge the scan signal output control terminal Qb under the control of the previous stage scan signal Scan[n-1]. The current-stage scan signal output unit 122 is used to output the current-stage scan signal Scan[n] under the control of the level of the scan signal output control terminal Qb. The second pull-down unit 124 is used to pull down the level signal of the scan signal output control terminal Qb and the output current-stage scan signal Scan[n] to a first low level VSS under the control of the next stage scan signal Scan[n+1], so that the current-stage scan signal Scan[n] outputs a single positive pulse. The sustaining unit 123 is used to maintain the level of the scan signal output control terminal Qb and the output current-stage scan signal Scan[n] at the first low level VSS under the control of the level of the programming signal control terminal.

[0052] Specifically, the second pre-charge unit 121 includes a second pre-charge control transistor T1b and a third bootstrap capacitor C3b; the control terminal of the second pre-charge control transistor T1b is connected to the previous stage scan signal Scan[n-1], the first path terminal of the second pre-charge control transistor T1b is connected to the stage signal output control terminal Qa, the second path terminal of the second pre-charge control transistor T1b is connected to the first terminal of the third bootstrap capacitor C3b to form the scan signal output control terminal Qb; the second terminal of the third bootstrap capacitor C3b is connected to the current stage scan signal output unit 122, the second pull-down unit 124 and the sustaining unit 123.

[0053] Specifically, the local scan signal output unit 122 includes a local scan signal output transistor T5b; the control terminal of the local scan signal output transistor T5b is connected to the scan signal output control terminal Qb, the first path terminal of the local scan signal output transistor T5b is also connected to the third clock signal CK1L, and the second path terminal of the local scan signal output transistor T5b is connected to the second terminal of the third bootstrap capacitor C3b and outputs the local scan signal Scan[n].

[0054] Specifically, the sustaining unit 123 includes a third pull-down transistor T2b and a fourth pull-down transistor T3b; the control terminal of the third pull-down transistor T2b is connected to the control terminal of the fourth pull-down transistor T3b and is also connected to the programming signal control terminal Qc; the first path terminal of the third pull-down transistor T2b is connected to the scan signal output control terminal Qb; the second path terminal of the third pull-down transistor T2b is connected to the second path terminal of the fourth pull-down transistor T3b and is connected to the first low level VSS; the first path terminal of the fourth pull-down transistor T3b is connected to the second terminal of the third bootstrap capacitor C3b and the second path terminal of the scan signal output transistor T5b of this stage.

[0055] Specifically, the second pull-down unit 124 includes a fifth pull-down transistor T4b and a sixth pull-down transistor T6b; the control terminal of the fifth pull-down transistor T4b is connected to the control terminal of the sixth pull-down transistor T6b and connected to the next stage scan signal Scan[n+1]; the first path terminal of the fifth pull-down transistor T4b is connected to the second terminal of the third bootstrap capacitor C3b and the second path terminal of the current stage scan signal output transistor T5b; the second path terminal of the fifth pull-down transistor T4b is connected to the second path terminal of the sixth pull-down transistor T6b and connected to the first low level VSS; the first path terminal of the sixth pull-down transistor T6b is connected to the scan signal output control terminal Qb.

[0056] Please combine Figure 2 The timing diagram of the gate drive circuit shown is for... Figure 4 The working principle of the scan signal generation module is explained in detail below. The scan signal generation module is electrically connected to the first-stage transfer node Qa and the second-stage transfer node Qc of the shift register module. Adjacent scan signal generation modules are respectively input with the scan signal Scan[n-1] of the previous stage scan signal generation module and the scan signal Scan[n+1] of the next stage scan signal generation module, as well as the third clock signal CK1L, to output the scan signal Scan[n] of the current stage. It should be noted that the third clock signal CK1L is the same clock signal as the first clock signal CK1, but the low level of the third clock signal CK1L is lower than that of the first clock signal CK1 to improve the stability of the gate drive circuit. The following explanation will use the first clock signal CK1 as an example to explain the working principle of the scan signal generation module instead of the third clock signal CK1L. For the nth stage scan signal generation module, it has four working states in the process of outputting the scan signal Scan[n] of the current stage, namely P2a, P3a, P4a and P5a. The four working states of the scan signal generation module are explained in detail below.

[0057] P2a state: At this time, the previous stage scan signal Scan[n-1] is at a global high level VDD, controlling the second precharge control transistor T1b to be in the conducting state. Since the level of the first stage transmission node Qa connected to the first terminal of the second precharge control transistor T1b is the first precharge level VD1, the conducting second precharge control transistor T1b provides the first precharge level VD1 to the control terminal of the current stage scan signal output transistor T5b and the first terminal of the third bootstrap capacitor C3b, making the current stage scan signal output transistor T5b in the conducting state, and the level of the scan signal output control terminal Qb is pulled high to the first precharge level VD1. Charge is stored through the third bootstrap capacitor C3b to maintain the potential of the scan signal output control terminal Qb, thereby outputting the third clock signal CK1L to the output terminal of the current stage scan signal Scan[n] through the current stage scan signal output transistor T5b. At this time, since the third clock signal CK1L is the first low level VSS, the output of the current stage scan signal Scan[n] is the first low level VSS.

[0058] Since the level of the second-stage transmission node Qc changes to the second low level VSSL state at this time, the third pull-down transistor T2b and the fourth pull-down transistor T3b of the pull-down unit are in the off state; at this time, the scan signal Scan[n+1] of the next stage scan signal generation circuit is in the first low level VSS state, so the fifth pull-down transistor T4b and the sixth pull-down transistor T6b of the second pull-down unit are also in the off state.

[0059] P3a state: Since the previous stage scan signal Scan[n-1] and the next stage scan signal Scan[n+1] are both in the first low level VSS state, the second precharge control transistor T1b of the second precharge unit and the fifth pull-down transistor T4b and the sixth pull-down transistor T6b of the second pull-down unit are in the off state; Since the level of the second stage transmission node Qc is still in the second low level VSSL state, the third pull-down transistor T2b and the fourth pull-down transistor T3b of the maintenance unit are still in the off state; At this time, due to the bootstrap effect of the third bootstrap capacitor C3b, the potential of the first stage transmission node Qa becomes the second precharge level VD2, which is higher than the first precharge level VD1, so that the current stage scan signal output transistor T5b continues to be in the on state. At this time, the third clock signal CK1L is in the global high level VDD state, so the current stage scan signal Scan[n] output is the global high level VDD.

[0060] P4a State: After P3a state, if the previous stage scan signal Scan[n-1] is in the first low level VSS state, and the level of the first stage transmission node Qa is the first pre-charge level VD1, then it will enter P4a state. When entering P4a state for the first time, the next stage scan signal Scan[n+1] transmitted to the current stage scan signal generation circuit is in the global high level VDD state, controlling the fifth pull-down transistor T4b and the sixth pull-down transistor T6b of the second pull-down unit to be in the on state. The on- state of the sixth pull-down transistor T6b provides the first low level VSS to the control of the current stage scan signal output transistor T5b. The first terminal of the control terminal and the third bootstrap capacitor C3b pulls down the level of the scan signal output control terminal Qb to the first low level VSS, so that the scan signal output transistor T5b of this stage is in the cut-off state, preventing the high level signal of the scan signal output control terminal Qb from being further programmed, and ensuring that the scan signal Scan[n] of this stage outputs a single positive pulse; the conducting fifth pull-down transistor T4b provides the first low level VSS to the output terminal of the scan signal Scan[n] of this stage, and promptly pulls down the output terminal of the scan signal Scan[n] of this stage to the first low level VSS, thereby improving the driving capability of the scan signal Scan[n]. Since each scanning signal generation circuit outputs only a single positive pulse scanning signal, when entering the P4a state again after the first time, the subsequent scanning signal Scan[n+1] transmitted to the current scanning signal generation circuit is at the first low level VSS. The fifth pull-down transistor T4b and the sixth pull-down transistor T6b of the second pull-down unit will be in the off state. Since the previous scanning signal Scan[n-1] is at the first low level VSS in the P4a state, the second precharge control transistor T1b will be in the off state. The second stage transmission node Qc will maintain the second low level VSSL state. Therefore, the third pull-down transistor T2b and the fourth pull-down transistor T3b of the maintenance unit will still be in the off state.

[0061] At this time, since the previous stage scan signal Scan[n-1] is still in the first low level VSS state, and the level of the first stage transmission node Qa changes to the second pre-charge level VD2 again, it will enter the P3a state after the P4a state. Since the current stage transmission signal C[n] has already output a global high level VDD pulse once when entering the P3a state for the first time, the current stage transmission signal C[n] will no longer output a global high level VDD pulse when entering the P3a state again. Therefore, the current stage scan signal Scan[n] will maintain the first low level VSS.

[0062] P5a State: After P3a state, if the level of the first-stage transmission node Qa is pulled low to the first low level VSS, then it will enter the P5a state. At this time, since the scanning signal Scan[n-1] of the previous stage and the scanning signal Scan[n+1] of the next stage scanning signal generation circuit are both in the first low level VSS state, the second precharge control transistor T1b of the second precharge unit and the fifth pull-down transistor T4b and the sixth pull-down transistor T6b of the second pull-down unit are in the off state; since the second-stage transmission node Qc is pulled high to the global high level VDD, the third pull-down transistor T2b and the fourth pull-down transistor T3b of the control and maintenance unit are in the on state, and the on-state third pull-down transistor T1b... 2b provides the first low level VSS to the control terminal of the scan signal output transistor T5b and the first terminal of the third bootstrap capacitor C3b, further pulling down the level of the scan signal output control terminal Qb to the first low level VSS, so that the scan signal output transistor T5b is in the off state. The conducting fourth pull-down transistor T3b provides the first low level VSS to the output terminal of the scan signal Scan[n] of this stage, and keeps the output terminal of the scan signal Scan[n] in the first low level VSS state, thereby ending the output of the scan signal of this stage.

[0063] As can be seen from the working principle of the above-mentioned scanning signal generation circuit, the sixth pull-down transistor T6b of the second pull-down unit 124 pulls down the level of the scanning signal output control terminal Qb to the first low level VSS, preventing the high level signal of the scanning signal output control terminal Qb from being further programmed, thus ensuring that the scanning signal Scan[n] of this stage outputs a single positive pulse; and the level of the scanning signal output control terminal Qb and the level of the output terminal of the scanning signal Scan[n] of this stage are maintained at the first low level VSS state by the sustaining unit 123. The double-layer pull-down structure of the second pull-down unit 124 and the sustaining unit 123 improves the driving capability of the scanning signal Scan[n] of this stage.

[0064] like Figure 5 The circuit structure of the light emission control signal generation module shown is as follows: the light emission control signal generation module 130 includes a first-stage inverter 131 and a second-stage inverter 132.

[0065] Specifically, the first-stage inverter 131 includes a first input transistor T6c and a first control transistor T5c, and the second-stage inverter 132 includes a second input transistor T2c, a second control transistor T1c, a first light-emitting control signal output transistor T3c, and a second light-emitting control signal output transistor T4c. The control terminal of the first input transistor T6c is connected to the stage signal output control terminal. The first path terminal of the first input transistor T6c is connected to the second path terminal of the first control transistor T5c, the control terminal of the second input transistor T2c, and the control terminal of the first light-emitting control signal output transistor T3c. The second path terminal of the first input transistor T6c is connected to a second low-level voltage VSSL. The first path terminal of the second input transistor T2c is connected to the second path terminal of the second control transistor T1c and the control terminal of the second light-emitting control signal output transistor T4c. The second path terminal of the second input transistor T2c is connected to the first light-emitting control signal output transistor T4c. The second path terminal of transistor T3c is connected to and connected to the first low level VSS; the control terminal of the first control transistor T5c is connected to and connected to the first path terminal of the first control transistor T5c and connected to the global high level VDD; the control terminal of the second control transistor T1c is connected to and connected to the first path terminal of the second control transistor T1c and connected to the global high level VDD; the first path terminal of the first light-emitting control signal output transistor T3c is connected to and connected to the second path terminal of the second light-emitting control signal output transistor T4c and outputs the light-emitting control signal EM[n] of this stage; the first path terminal of the second light-emitting control signal output transistor T4c is connected to the global high level.

[0066] Please combine Figure 2 The timing diagram of the gate drive circuit shown is for... Figure 5 The working principle of the shift register module shown is explained in detail. Under the control of the first-stage transmission node Qa level, the light emission control signal generation module outputs the current-stage light emission control signal EM[n] to the light emission control signal output terminal to control the micro-LEDs of the pixel circuit to emit light. For the nth-stage light emission control signal generation module, it has three working states during the output of the current-stage light emission control signal EM[n]: P1d, P2d, and P3d. The process of outputting the current-stage light emission control signal EM[n] is explained in detail below.

[0067] P1d State: When the potential of the first stage transmission node Qa at the nth stage output is the first low level VSS, the light emission control signal generation module enters the P1d state. At this time, the first input transistor T6c is in the off state, and the second control transistor T1c and the first control transistor T5c are in the on state. The on-state first control transistor T5c provides the global high level VDD to the control terminals of the second input transistor T2c and the first light emission control signal output transistor T3c, controlling the second input transistor T2c and the first light emission control signal output transistor T3c to be on. The on-state second input transistor T2c provides the first low level VSS to the control terminal of the second light emission control signal output transistor T4c, controlling the second light emission control signal output transistor T4c to be in the off state. The on-state first light emission control signal output transistor T3c provides the first low level VSS to the output terminal of the light emission control signal EM[n] of this stage, so that the output of the light emission control signal EM[n] of this stage is the first low level VSS.

[0068] P2d state: When the potential of the first-stage transmission node Qa at the nth stage output is the first pre-charge level VD1 or the second pre-charge level VD2, the light emission control signal generation module enters the P2d state. At this time, the first precharge level VD1 or the second precharge level VD2 causes the first input transistor T6c to be in the conducting state. The conducting first input transistor T6c provides the second low level VSSL to the control terminals of the second input transistor T2c and the first light-emitting control signal output transistor T3c, controlling the second input transistor T2c and the first light-emitting control signal output transistor T3c to be in the off state. At this time, the second control transistor T1c and the first control transistor T5c are still in the conducting state. The conducting second control transistor T1c provides the global high level VDD to the control terminal of the second light-emitting control signal output transistor T4c. Due to the bootstrap effect of the intrinsic capacitance of the second light-emitting control signal output transistor T4c, the potential of the control terminal of the second light-emitting control signal output transistor T4c rises to VDD, controlling the second light-emitting control signal output transistor T4c to be conducting. Thus, the conducting second light-emitting control signal output transistor T4c transmits the global high level VDD to the output terminal of the light-emitting control signal EM[n] of this stage without loss, making the output of the light-emitting control signal EM[n] of this stage a global high level VDD.

[0069] P3d State: When the potential of the first stage transmission node Qa at the nth stage output returns to the first low level VSS, the light emission control signal generation module enters the P3d state. At this time, the first input transistor T6c is in the off state, while the second control transistor T1c and the first control transistor T5c are still in the on state. The on-state first control transistor T5c provides the global high level VDD to the control terminals of the second input transistor T2c and the first light emission control signal output transistor T3c again, controlling the second input transistor T2c and the first light emission control signal output transistor T3c to turn on again. The on-state second input transistor T2c provides the first low level VSS to the control terminal of the second light emission control signal output transistor T4c, controlling the second light emission control signal output transistor T4c to be in the off state. The on-state first light emission control signal output transistor T3c provides the first low level VSS to the output terminal of the light emission control signal EM[n] of this stage, so that the light emission control signal EM[n] of this stage is reset to the first low level VSS.

[0070] As can be seen from the working principle of the light emission control signal generation module, its main function is to perform two-stage reverse rectification on the level signal of the first-stage transmission node Qa. When the light emission control signal generation module receives a low level input, i.e., when the level of the first-stage transmission node Qa is the first low level VSS, the first light emission control signal output transistor T3c is turned on, the second light emission control signal output transistor T4c is turned off, and the light emission control signal generation module outputs a low-level light emission control signal. When the light emission control signal generation module receives a high level input, i.e., when the level of the first-stage transmission node Qa is the first pre-charge level VD1 or the second pre-charge level VD2, the second light emission control signal output transistor T4c is turned on, the first light emission control signal output transistor T3c is turned off, and the light emission control signal generation module outputs a high-level light emission control signal. Since the VTC curve of the TFT inverter is relatively flat, by inputting a first low level VSS at the second path terminal of the first light-emitting control signal output transistor T3c and a lower second low level VSSL at the second path terminal of the first input transistor T6c in the first stage inverter, the low level of the first stage inverter is coupled to the lower second low level VSSL using the double low level structure. This allows the light-emitting control signal generation module to output a high-level light-emitting control signal without loss, thereby achieving the full swing of the output local light-emitting control signal EM[n]. Furthermore, the bootstrap effect of the intrinsic capacitance of the first light-emitting control signal output transistor T3c and the second light-emitting control signal output transistor T4c is used to improve the driving capability of the light-emitting control signal EM[n].

[0071] Furthermore, since the light emission control signal generation module outputs a high-level light emission control signal EM[n] under the control of the first pre-charge level VD1 or the second pre-charge level VD2 of the first-stage transmission node Qa, the signal width of the light emission control signal EM[n] is consistent with the width of the first pre-charge level VD1 or the second pre-charge level VD2. For each pulse input to the transmission signal of the shift register module, the first-stage transmission node Qa will generate the first pre-charge level VD1 or the second pre-charge level VD2 once. Therefore, the pulse width of the light emission control signal EM[n] is positively correlated with the number of pulses of the transmission signal C[n]. The signal width of the light emission control signal EM[n] is N*T1, which is the product of the number of pulses N and the period T1 of the first clock signal CK1.

[0072] In summary, the gate driving circuit proposed in this invention integrates the shift register module 110, the scan signal generation module 120, and the light emission control signal generation module 130 in a single-stage gate driving circuit. This allows the current-stage light emission control signal EM[n], the current-stage scan signal Scan[n], and the current-stage transmission signal C[n] to be generated synchronously and in parallel. Furthermore, the pulse width of the current-stage light emission control signal EM[n] can be programmed. By combining it with the current-stage scan signal Scan[n] to write data, digital PWM subframe illumination can be achieved, thereby reducing the area occupied by the circuit layout and facilitating the implementation of narrow-bezel display panels. Moreover, through the line-by-line light emission digital subframe PWM driving method, the light emission control signal EM[n] can be generated line by line, improving luminous efficiency and significantly enhancing the display effect of MLED. Additionally, the use of a dual low-potential structure improves circuit stability and driving capability.

[0073] This invention also provides a pixel circuit, such as... Figure 6 As shown, the pixel circuit includes a data input transistor M3, a first reference transistor M5, a first storage capacitor C1, a second storage capacitor C2, a PWM drive transistor M4, a light emission control transistor M1, a PAM drive transistor M2, a second reference transistor M6, an initialization transistor M7, a threshold compensation transistor M8, and a micro light-emitting diode MLED.

[0074] Specifically, the control terminal of data input transistor M3 is connected to the next stage scan signal Scan[n+1], the first path terminal of data input transistor M3 is connected to the data voltage Vdata, and the second path terminal of data input transistor M3 is connected to the second path terminal of first reference transistor M5, the second terminal of first storage capacitor C1, and the control terminal of PWM drive transistor M4; the control terminal of first reference transistor M5 is connected to the scan signal of this stage, and the first path terminal of first reference transistor M5 is connected to the first low level VSS; the first terminal of first storage capacitor C1 is connected to the first path terminal of PWM drive transistor M4 and the first terminal of second storage capacitor C2 and connected to the global high level VDD; the control terminal of light-emitting control transistor M1 is connected to the next two stages of light-emitting control signals EM[n+2], the first path terminal of light-emitting control transistor M1 is connected to the second path terminal of second reference transistor M6 and the second path terminal of PAM drive transistor M2, and the second path terminal of light-emitting control transistor M1 is connected to the second path terminal of second reference transistor M6 and the second path terminal of PAM drive transistor M2. The terminal of the PAM driving transistor M2 is connected to the anode of the micro LED; the control terminal of the PAM driving transistor M2 is connected to the first path terminal of the initialization transistor M7 and the second path terminal of the threshold compensation transistor M8, and the first path terminal of the PAM driving transistor M2 is connected to the first path terminal of the threshold compensation transistor M8; the control terminal of the second reference transistor M6 is connected to the current stage scan signal Scan[n], and the first path terminal of the second reference transistor M6 is connected to the reference voltage Vref; the control terminal of the initialization transistor M7 is connected to the previous stage scan signal Scan[n-1], and the second path terminal of the initialization transistor M7 is connected to the initialization voltage Vinit; the control terminal of the threshold compensation transistor M8 is connected to the current stage scan signal, the first path terminal of the threshold compensation transistor M8 is connected to the second path terminal of the PWM driving transistor M4, and the second path terminal of the threshold compensation transistor M8 is connected to the second terminal of the second storage capacitor C2; the cathode of the micro LED MLED is connected to the first low level VSS.

[0075] Please combine Figure 7 The timing diagram of the pixel circuit shown is for... Figure 6 The working principle of the pixel circuit shown is explained in detail. The pixel circuit's light-emitting process includes three stages: P1, P2, and P3. In different operating stages, the transistors in the pixel circuit are turned on or off accordingly to achieve functions such as reset, data writing, threshold compensation, and light-emitting control. The following provides a detailed explanation of the P1, P2, and P3 stages of the pixel circuit.

[0076] P1 initialization phase: The previous stage scan signal Scan[n-1] goes high, controlling the initialization transistor M7 to be in the conducting state; the conducting initialization transistor M7 provides the initialization voltage Vinit to the first terminal of the second storage capacitor C2 and the control terminal of the PAM driving transistor M2, so the voltage Vg at the control terminal of the PAM driving transistor M2 is Vinit, and the PAM driving transistor M2 is pre-turned on; the second terminal of the second storage capacitor C2 is charged to Vinit, and at this time the voltage across the second storage capacitor C2 is Vc2 = VDD - Vinit. Since the current stage scan signal Scan[n], the next stage scan signal Scan[n+1], and the next two stage light emission control signals EM[n+2] are low, the other transistors in the pixel circuit are all in the off state.

[0077] P2 Programming and Compensation Stage: The current scan signal Scan[n] goes high, controlling the first reference transistor M5, the second reference transistor M6, and the threshold compensation transistor M8 to be in the conducting state. The conducting first reference transistor M5 provides a low voltage VSS to the first terminal of the first storage capacitor C1, and the second terminal of the first storage capacitor C1 is charged to VSS. At this time, the voltage across the first storage capacitor C1 is Vc1 = VDD - VSS. The conducting second reference transistor M6 provides a reference voltage Vref to the second terminal of the PAM driving transistor M2. The conducting threshold compensation transistor M8 short-circuits the control terminal and the first path terminal of the PAM driving transistor, making the PAM driving transistor M2 form a diode electrical connection structure. Therefore, the PAM driving transistor M2 is also in the conducting state. Compared with the voltage across the second storage capacitor C2, which is Vc2 = VDD - Vinit, the above reference voltage Vref is lower. Therefore, the charge stored in the second storage capacitor C2 is discharged through the conducting PAM driving transistor M2 and the conducting threshold compensation transistor M8, causing the potential at the control terminal of the PAM driving transistor M2 to continuously rise until the voltage Vgs-Vth at the control terminal and the second path terminal of the PAM driving transistor M2 reaches 0. Vth is the threshold voltage of the PAM driving transistor M2, at which point the PAM driving transistor M2 is turned off, and the second storage capacitor C2 stops discharging. At this time, the voltage at the control terminal of the PAM driving transistor M2 is Vg = Vref + Vth. The voltage stored in the second storage capacitor C2 at this time is Vc2 = VDD - (Vref + Vth).

[0078] During the P2 stage, since the previous stage scanning signal Scan[n-1], the next stage Scan[n+1], and the light emission control signal EM[n+2] are all at low levels, the other transistors in the pixel circuit are all in the off state.

[0079] P3 Light Emission Stage: In the early stage of P3 light emission, the subsequent scanning signal Scan[n+1] goes high, controlling the data input transistor M3 to be in the conducting state. The conducting data input transistor M3 provides the data voltage Vdata to the control terminal of the PWM driving transistor M4, controlling the PWM driving transistor M4 to be in the conducting state. The conducting PWM driving transistor M4 provides the power supply voltage VDD to the first path terminal of the PAM driving transistor M2. At this time, the voltage across the first storage capacitor C1 is Vc1 = VDD - Vdata. The voltage stored in the second storage capacitor C2 is applied to the control terminal of the PAM driving transistor M2, causing the PAM driving transistor M2 to conduct. The light emission control signal EM[n+2] also goes high, controlling the light emission control transistor M1 to conduct. The conducting light emission control transistor M1 connects the second path terminal of the PAM driving transistor M2 to the anode of the micro light-emitting diode MLED. In this case, the light emission control transistor M1 is conducting, and the gate-source voltage Vgs of the PAM driving transistor M2 is Vref + Vth - (V LED +VSS). At this time, the PAM driving transistor M2 is in saturation, and the current path between the global high-level VDD terminal and the first low-level VSS terminal is open.

[0080] The luminous current I flowing through the miniature light-emitting diode (MLED) is:

[0081] I MLED =0.5(W / L)μ eff C OX (Vgs-Vth) 2

[0082] =0.5(W / L)μ eff C OX (Vref+Vth-V LED -VSS-Vth) 2

[0083] =0.5(W / L)μ eff C OX (Vref-V LED -VSS) 2 ,

[0084] Meanwhile, the luminous current I flowing through the miniature light-emitting diode MLED satisfies the IV characteristic curve relationship with the voltage across its terminals: I MLED =f(V LED ), where W is the channel width, L is the channel length, and μ eff It is the carrier mobility, C OX It is the capacitance between the gate electrode (control terminal) and the conductive channel, V LED It is the voltage difference across the MLED under a constant driving current.

[0085] Therefore, the luminous current I flowing through the miniature LED (MLED) can be uniquely determined. By adjusting the reference voltage Vref and the first low-level voltage VSS, the MLED can be made to operate within a suitable IV range. The MLED and the PWM driving transistor form a source-negative feedback structure, which effectively resists the drift of the PWM driving transistor's threshold voltage. Thus, the luminous current flowing through the MLED in this pixel circuit is independent of the threshold voltage of the PAM driving transistor M2, thereby compensating for threshold voltage drift and eliminating, to some extent, the influence of threshold voltage drift on the MLED's luminous current.

[0086] In the later stage of P3 light emission, the gate scan signal Scan[n+1] goes low, the control data input transistor M3 is in the off state, the voltage stored in the first storage capacitor C1 is applied to the control terminal of the PWM drive transistor M4, so that the PWM drive transistor M4 continues to be turned on, the light emission control signal EM[n+2] is still high, and the control light emission control transistor M1 continues to be turned on, maintaining the light emission of the miniature light-emitting diode MLED.

[0087] The pixel circuit provided in this embodiment of the invention integrates the PAM module and the PWM module, realizing compensation for threshold voltage drift and digital PWM subframe emission.

[0088] It should be noted that all the transistors mentioned above are N-type transistors; the same principle can also be applied to P-type transistors with slight modifications to the circuit connections. Furthermore, the control terminal of each transistor is the gate, the first pass terminal can be the source, and the second pass terminal can be the drain; alternatively, the first pass terminal can be the drain, and the second pass terminal can be the source.

[0089] The present invention also provides an active-matrix display, including the gate driving circuit and pixel circuit described above. A cascaded block diagram of the gate driving circuit and pixel circuit in the active-matrix display is shown below. Figure 8 As shown.

[0090] The gate driving circuit includes a shift register module and a driving module. The shift register module and the driving module are connected through a stage transmission signal output control terminal Qa and a programming signal control terminal Qc. The driving module includes a scan signal generation module and a light emission control signal generation module as described above. The driving module is used to output the scan signal generated in this stage to the previous stage pixel circuit, the current stage pixel circuit, and the next stage pixel circuit to complete the row-by-row scanning of the two-dimensional pixel matrix. The driving module is also used to output the light emission control signal generated in this stage to the pixel circuits of the next two stages to complete the light emission control of the two-dimensional pixel matrix.

[0091] The active-matrix display provided in this embodiment integrates a shift register module, a scan signal generation module, and a light emission control signal generation module in a first-stage gate drive circuit. This allows the scan signal and light emission control signal to be generated synchronously and in parallel with the stage transmission signal. At the same time, the pulse width of the light emission control signal can be programmed. This, in conjunction with the pixel circuit, enables digital PWM subframe light emission, reducing the area occupied by the circuit layout of the active-matrix display and facilitating the implementation of narrow-bezel display panels.

[0092] In the description of this invention, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0093] The terms “first,” “second,” “third,” etc., are used merely to distinguish elements with similar attributes, and do not indicate or imply relative importance or a specific order. The terms “including,” “comprising,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the listed elements but also other elements not expressly listed.

[0094] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A gate driving circuit, characterized in that, It includes a cascaded shift register module and a driver module connected to the shift register module, wherein the driver module includes a scan signal generation module and a light emission control signal generation module; The shift register module includes a cascade signal output control terminal and a programming signal control terminal. The shift register module is used to generate a cascade signal under the control of a clock signal, and to program and control the level of the cascade signal output control terminal and the level of the programming signal control terminal. The scanning signal generation module is connected to the cascade signal output control terminal and the programming signal control terminal, and is used to output a scanning signal under the control of the level of the cascade signal output control terminal and the level of the programming signal control terminal. The light emission control signal generation module is connected to the cascade signal output control terminal and is used to output a light emission control signal under the control of the level of the cascade signal output control terminal. The shift register module includes a first precharge unit, a local cascade signal output unit, a programming unit, and a first pull-down unit; The first pre-charging unit is used to charge the output control terminal of the transmission signal under the control of the previous stage transmission signal. The cascade signal output unit is used to output the cascade signal under the control of the level of the cascade signal output control terminal; The programming unit programs the pull-down and pull-up times of the programming signal control terminal based on the input reset signal, the previous stage transmission signal, and the next stage transmission signal. The first pull-down unit is used to pull down the level of the cascade signal output control terminal to a first low level under the control of the level of the programming signal control terminal, and reset the output cascade signal of this stage to a second low level, wherein the level value of the first low level is greater than the level value of the second low level.

2. The gate driving circuit according to claim 1, characterized in that, The first pre-charge unit includes a first pre-charge control transistor and a first bootstrap capacitor; the control terminal of the first pre-charge control transistor is connected to the first path terminal of the first pre-charge control transistor and connected to the previous stage transmission signal; the second path terminal of the first pre-charge control transistor is connected to the first terminal of the first bootstrap capacitor to form the stage transmission signal output control terminal; the second terminal of the first bootstrap capacitor is connected to the current stage transmission signal output unit and the first pull-down unit. The cascade signal output unit includes a cascade signal output transistor. The control terminal of the current stage transmission signal output transistor is connected to the transmission signal output control terminal. The first path terminal of the current stage transmission signal output transistor is connected to the first clock signal. The second path terminal of the current stage transmission signal output transistor is connected to the second terminal of the first bootstrap capacitor and outputs the current stage transmission signal.

3. The gate driving circuit according to claim 2, characterized in that, The programming unit includes a first programming control transistor, a second programming control transistor, a third programming control transistor, a fourth programming control transistor, a reset control transistor, and a second capacitor. The control terminal of the first programming control transistor is connected to the subsequent stage-by-stage signal transmission. The first path terminal of the first programming control transistor is connected to the control terminal of the fourth programming control transistor and connected to the second clock signal. The second path terminal of the first programming control transistor is connected to the control terminal of the second programming control transistor and the first path terminal of the second programming control transistor. The second path terminal of the second programming control transistor is connected to the first path terminal of the fourth programming control transistor and the first path terminal of the third programming control transistor. The control terminal of the third programming control transistor is connected to the signal transmitted by the previous stage, and the second path terminal of the third programming control transistor is connected to the second terminal of the second capacitor and connected to the second low level. The second terminal of the fourth programming control transistor is connected to the first terminal of the second capacitor to form the programming signal control terminal; The control terminal of the reset control transistor is connected to a reset signal, the first path terminal of the reset control transistor is connected to a global high level, and the second path terminal of the reset control transistor is connected to the programming signal control terminal.

4. The gate driving circuit according to claim 3, characterized in that, The first pull-down unit includes a first pull-down transistor and a second pull-down transistor; The control terminal of the first pull-down transistor is connected to the programming signal control terminal, the first path terminal of the first pull-down transistor is connected to the cascade signal output control terminal, and the second path terminal of the first pull-down transistor is connected to the first low level. The control terminal of the second pull-down transistor is also connected to the programming signal control terminal. The first path terminal of the second pull-down transistor is connected to the second terminal of the first bootstrap capacitor and the second path terminal of the stage-transmit signal output transistor. The second path terminal of the second pull-down transistor is connected to the second low level.

5. The gate driving circuit according to claim 4, characterized in that, The scan signal generation module includes a second pre-charge unit, a local scan signal output unit, a second pull-down unit, and a sustaining unit; The second pre-charge unit is used to charge the scan signal output control terminal under the control of the previous stage scan signal; The local scanning signal output unit is used to output the local scanning signal under the control of the level of the scanning signal output control terminal; The second pull-down unit is used to pull down the level signal of the scan signal output control terminal and the output scan signal of this stage to a first low level under the control of the scan signal of the next stage, so that the scan signal of this stage outputs a single positive pulse; The sustaining unit is used to maintain the level of the scan signal output control terminal and the output scan signal of this stage at a first low level under the control of the level of the programming signal control terminal.

6. The gate driving circuit according to claim 5, characterized in that, The second pre-charge unit includes a second pre-charge control transistor and a third bootstrap capacitor; the control terminal of the second pre-charge control transistor is connected to the previous stage scan signal, the first path terminal of the second pre-charge control transistor is connected to the stage signal output control terminal, and the second path terminal of the second pre-charge control transistor is connected to the first terminal of the third bootstrap capacitor to form the scan signal output control terminal; the second terminal of the third bootstrap capacitor is connected to the current stage scan signal output unit, the second pull-down unit, and the sustaining unit. The local scan signal output unit includes a local scan signal output transistor; the control terminal of the local scan signal output transistor is connected to the scan signal output control terminal, the first path terminal of the local scan signal output transistor is connected to a third clock signal, and the second path terminal of the local scan signal output transistor is connected to the second terminal of the third bootstrap capacitor and outputs the local scan signal. The sustaining unit includes a third pull-down transistor and a fourth pull-down transistor; The control terminal of the third pull-down transistor is connected to the control terminal of the fourth pull-down transistor and to the programming signal control terminal. The first path terminal of the third pull-down transistor is connected to the scan signal output control terminal. The second path terminal of the third pull-down transistor is connected to the second path terminal of the fourth pull-down transistor and is connected to a first low-level signal. The first path terminal of the fourth pull-down transistor is connected to the second terminal of the third bootstrap capacitor and the second path terminal of the scan signal output transistor of this stage. The pull-down unit includes a fifth pull-down transistor and a sixth pull-down transistor; the control terminal of the fifth pull-down transistor is connected to the control terminal of the sixth pull-down transistor and is connected to the subsequent stage scan signal; the first path terminal of the fifth pull-down transistor is connected to the second terminal of the third bootstrap capacitor and the second path terminal of the current stage scan signal output transistor; the second path terminal of the fifth pull-down transistor is connected to the second path terminal of the sixth pull-down transistor and is connected to a first low-level signal; the first path terminal of the sixth pull-down transistor is connected to the scan signal output control terminal.

7. The gate driving circuit according to claim 6, characterized in that, The light emission control signal generation module includes a first-stage inverter and a second-stage inverter. The first-stage inverter includes a first input transistor and a first control transistor. The first-stage inverter also includes a second input transistor, a second control transistor, a first light emission control signal output transistor, and a second light emission control signal output transistor. The control terminal of the first input transistor is connected to the stage signal output control terminal. The first path terminal of the first input transistor is connected to the second path terminal of the first control transistor, the control terminal of the second input transistor, and the control terminal of the first light emission control signal output transistor. The second path terminal of the first input transistor is connected to a second low-level signal. The first path terminal of the second input transistor is connected to the second path terminal of the second control transistor and the control terminal of the second light-emitting control signal output transistor. The second path terminal of the second input transistor is connected to the second path terminal of the first light-emitting control signal output transistor and is connected to the first low level. The control terminal of the first control transistor is connected to the first path terminal of the first control transistor and is connected to the global high level. The control terminal of the second control transistor is connected to the first path terminal of the second control transistor and is connected to the global high level. The first path terminal of the first light-emitting control signal output transistor is connected to the second path terminal of the second light-emitting control signal output transistor and outputs the light-emitting control signal of this stage. The first path terminal of the second light emission control signal output transistor is connected to the global high level.

8. A pixel circuit, characterized in that, Used to receive a scan signal and a light emission control signal output by the gate driving circuit as described in any one of claims 1 to 7, so as to perform light emission control of the pixel circuit; the pixel circuit includes a data input transistor, a first reference transistor, a first storage capacitor, a second storage capacitor, a PWM driving transistor, a light emission control transistor, a PAM driving transistor, a second reference transistor, an initialization transistor, a threshold compensation transistor, and a micro light-emitting diode; The control terminal of the data input transistor is connected to the next stage scan signal, the first path terminal of the data input transistor is connected to the data voltage, and the second path terminal of the data input transistor is connected to the second path terminal of the first reference transistor, the second terminal of the first storage capacitor, and the control terminal of the PWM drive transistor. The control terminal of the first reference transistor is connected to the local scan signal, and the first path terminal of the first reference transistor is connected to a first low level. The first terminal of the first storage capacitor is connected to the first path terminal of the PWM driving transistor and the first terminal of the second storage capacitor and is connected to a global high level. The control terminal of the light-emitting control transistor is connected to the last two stages of light-emitting control signals. The first path terminal of the light-emitting control transistor is connected to the second path terminal of the second reference transistor and the second path terminal of the PAM driving transistor. The second path terminal of the light-emitting control transistor is connected to the anode of the micro light-emitting diode. The control terminal of the PAM driving transistor is connected to the first path terminal of the initialization transistor and the second path terminal of the threshold compensation transistor, and the first path terminal of the PAM driving transistor is connected to the first path terminal of the threshold compensation transistor. The control terminal of the second reference transistor is connected to the scanning signal of this stage, and the first path terminal of the second reference transistor is connected to the reference voltage; The control terminal of the initialization transistor is connected to the pre-stage scan signal, and the second path terminal of the initialization transistor is connected to the initialization voltage; The control terminal of the threshold compensation transistor is connected to the local scanning signal, the first path terminal of the threshold compensation transistor is connected to the second path terminal of the PWM driving transistor, and the second path terminal of the threshold compensation transistor is connected to the second terminal of the second storage capacitor. The cathode of the miniature light-emitting diode is connected to the first low level.

9. An active-matrix display, characterized in that, It includes the gate driving circuit as described in any one of claims 1 to 7 and the pixel circuit as described in claim 8.

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