A power management chip and a load access detection method thereof

Abstract

The application discloses a power management chip and a load access detection method thereof, and belongs to the technical field of power management chips. The power management chip comprises a load access detection unit, an output light load detection unit and an output power supply unit. The input signal of the load access detection unit and the output light load detection unit is connected to the output OUT end of the output power supply unit. The output signal ON end of the load access detection unit is connected to the input end of the output power supply unit. The output signal RESET end of the output light load detection unit is connected to the input end of the load access detection unit. The output OUT end of the output power supply unit is also connected to a plurality of loads. The application can identify a plurality of load access detections by using only one output channel, and the chip does not need a plurality of output channels, thereby greatly reducing the cost required by the plurality of output channels, reducing the number of chip pins, and enabling the use of a more compact and cheaper package.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and in particular to a power management chip and a load access detection method thereof. Background Technology

[0002] With the increasing popularity of multi-output power banks and Bluetooth headsets, there is a significant demand for multi-load access detection and charging. This section uses a Bluetooth headset charging case as an example to illustrate multi-load detection. In Bluetooth headset charging case applications, the charging case charges the headsets. Due to the limited battery capacity of the charging case, to increase standby time, the charging case needs to power off and enter standby mode after the headset is fully charged to reduce system power consumption. If the existing single-channel output chip is used for the charging case chip, the charging input pins of the two headsets are physically connected together, i.e., both are connected to the same output OUT pin of the charging case chip. This presents a problem for the headset charging case: if only one headset is in the charging case and the charging case is already in standby mode (i.e., the OUT pin is already connected to a load in standby mode), placing another headset in will not wake up the charging case, preventing it from activating to charge the other headset. Both headsets must be manually removed and placed back in to activate the charging case, resulting in a poor user experience. Therefore, existing solutions address this issue by using a dual-channel independent output charging case power control chip, as shown in the attached diagram. Figure 3 As shown, the main output port of the switching power supply is VBUS, and a power switch is added between it and each USB branch output port. Each USB output branch is equipped with a load access detection circuit. Each output path is independent of each other. In standby mode, even if one output is connected to the headphone load, it will not affect the detection when the other headphone is put in. However, the drawback of this method is that multiple output ports require multiple output control power switches, which not only greatly increases the cost of the switching power supply, but also increases the number of pins in the chip package. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention provides a power management chip and a load access detection method thereof.

[0004] To achieve the above objectives, the present invention provides a power management chip, comprising: a load access detection unit, an output light load detection unit, and an output power supply unit; The input signals of the load access detection unit and the output light load detection unit are connected to the output OUT terminal of the output power supply unit, the output signal ON terminal of the load access detection unit is connected to the input terminal of the output power supply unit, and the output signal RESET terminal of the output light load detection unit is connected to the input terminal of the load access detection unit; the output OUT terminal of the output power supply unit is also connected to several loads.

[0005] Preferably, the load access detection unit includes: a reference voltage VREF, an output voltage clamping NMOS transistor MN0, multiple PMOS transistors, multiple current sources, multiple pulse generation modules, and a logic control module; The reference voltage VREF is connected to the gate of the NMOS transistor MN0, the source of the NMOS transistor MN0 is connected to the output OUT terminal of the output power supply unit and several loads, and the drain of the NMOS transistor MN0 is electrically connected to the corresponding terminals of several PMOS transistors. The drains of the multiple PMOS transistors are also electrically connected to the positive terminals of multiple current sources and the input terminals of multiple pulse generation modules, respectively; the negative terminals of the multiple current sources are grounded; the output terminals of the multiple pulse generation modules are all connected to the input terminals of the logic control module, and the output terminals of the logic control module are connected to the output power supply unit; the RESET terminal of the output light load detection unit is also electrically connected to the corresponding terminal of the logic control module.

[0006] Preferably, when the output power supply unit stops outputting, the standby voltage of the OUT pin is equal to the reference voltage VREF minus the gate-source voltage VGS of the NMOS transistor MN0.

[0007] Preferably, the plurality of PMOS transistors include PMOS transistors MPO, MP1, MP2, to MPn, where n is an integer greater than or equal to 2; The drain of the NMOS transistor MN0 is connected to the gate and drain of the PMOS transistor MP0. The gate of the PMOS transistor MP0 is connected to the gate of the PMOS transistors MP1, MP2, and MPn. The source of the PMOS transistors MP0, MP1, MP2, and MPn is connected to the power supply VDD terminal.

[0008] Preferably, the plurality of current sources includes current sources I1, I2, to Ix, where x is an integer greater than or equal to 2; The drains of the PMOS transistors MP1, MP2, and MPn are connected to the positive terminals of the current sources I1, I2, and Ix, respectively, and the negative terminals of I1, I2, and Ix are all grounded.

[0009] Preferably, the plurality of pulse generation modules include pulse generation module 1, pulse generation module 2, and pulse generation module t, where t is an integer greater than or equal to 2; The positive terminals of the current sources I1, I2, and Ix are also connected to the input terminals of pulse generation module 1, pulse generation module 2, and pulse generation module t, respectively. The output terminals of pulse generation module 1, pulse generation module 2, and pulse generation module t are also connected to the input terminals of the logic control module.

[0010] Preferably, when MP1, MP2, and MPn have the same size, the currents of the corresponding current sources I1, I2, and Ix increase progressively. When the dimensions of the PMOS transistors MP1, MP2, and MPn are different, the currents of the corresponding current sources I1, I2, and Ix are the same.

[0011] Preferably, when the PMOS transistors MP1, MP2, and MPn have different sizes, the currents of the corresponding current sources I1, I2, and Ix are the same.

[0012] The present invention also provides a load access detection method, comprising the following methods: S1: When a new load is connected to the output OUT port, the PMOS transistor current increases; S2: If the PMOS transistor current increases to a level greater than the current of the corresponding current source, the corresponding detection signal DETn will flip from low level to high level for detection by the pulse generation module. S3: After the pulse generation module detects the rising edge of DETn, it generates a corresponding positive pulse output signal SETn to the logic control unit; S4: The logic control unit output signal ON is set to a high level, activating the output power supply unit to charge the load connected to the OUT terminal; S5: After the connected load is fully charged, the light load detection unit outputs a RESET signal to the logic control module; S6: When the logic control module output signal ON is reset, it outputs a low level, turning off the output power supply unit. This method ensures that even if one or more loads are connected to the OUT terminal in standby mode, the output power supply unit can be reactivated as long as other new loads are connected, without the need to use multiple power supply output channels.

[0013] Preferably, the increase in PMOS transistor current includes: an increase in the current of PMOS transistor MP0 and an increase in the mirror current of PMOS transistors MP1, MP2, and MPn.

[0014] The technical solution of the present invention has the following advantages: the present invention only requires one output path to identify multiple load access detections, and the chip does not need multiple output paths, which greatly reduces the cost required for multi-path output, and also reduces the number of chip pins, allowing for a more compact and cheaper package. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the power management chip module of the present invention; Figure 2 This is a schematic diagram of the power management chip control principle of the present invention; Figure 3 This is a schematic diagram of a multi-channel detection method in the prior art. Detailed Implementation

[0016] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0017] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0018] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0019] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0020] In this invention, unless otherwise expressly specified and limited, the first feature is "on" or "on" the second feature. The term "below" can include situations where the first and second features are in direct contact, or situations where the first and second features are in contact through another feature between them. Furthermore, "above," "over," and "on top" of the first feature above the second feature includes situations where the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" of the first feature below the second feature includes situations where the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0021] Reference Figures 1 to 2 The present invention provides a power management chip 1, including: a load access detection unit 101, an output light load detection unit 102, and an output power supply unit 103; The input signals of the load access detection unit 101 and the output light load detection unit 102 are connected to the output OUT terminal of the output power supply unit. The output signal ON terminal of the load access detection unit 101 is connected to the input terminal of the output power supply unit 103. The output signal RESET terminal of the output light load detection unit 102 is connected to the input terminal of the load access detection unit 101. The output OUT terminal of the output power supply unit 103 is also connected to several loads 2.

[0022] Furthermore, the load access detection unit 101 includes: a reference voltage VREF, an output voltage clamping NMOS transistor MN0, multiple PMOS transistors, multiple current sources, multiple pulse generation modules, and a logic control module. The reference voltage VREF is connected to the gate of the NMOS transistor MN0. The source of the NMOS transistor MN0 is connected to the output OUT terminal of the output power supply unit and several loads. The drain of the NMOS transistor MN0 is electrically connected to the corresponding terminals of the multiple PMOS transistors. The drains of the multiple PMOS transistors are also electrically connected to the positive terminals of the multiple current sources and the input terminals of the multiple pulse generation modules, respectively. The negative terminals of the multiple current sources are grounded. The output terminals of the multiple pulse generation modules are all connected to the input terminals of the logic control module, and the output terminals of the logic control module are connected to the output power supply unit. The output signal RESET terminal of the output light load detection unit 102 is also electrically connected to the corresponding terminal of the logic control module. When the output power supply unit 103 stops outputting, the standby voltage of the OUT pin is equal to the reference voltage VREF minus the gate-source voltage VGS of the NMOS transistor MN0.

[0023] Furthermore, the plurality of PMOS transistors includes PMOS transistors MPO, MP1, MP2, to MPn, where n is an integer greater than or equal to 2; the drain of the NMOS transistor MN0 is connected to the gate and drain of the PMOS transistor MP0, and the gate of the PMOS transistor MP0 is connected to the gate of the PMOS transistors MP1, MP2, and MPn; the source of the PMOS transistors MP0, MP1, MP2, and MPn is connected to the power supply VDD terminal. The plurality of current sources includes current sources I1, I2, to Ix, where x is an integer greater than or equal to 2; the drains of the PMOS transistors MP1, MP2, and MPn are connected to the positive terminals of the current sources I1, I2, and Ix respectively, and the negative terminals of I1, I2, and Ix are all grounded. The plurality of pulse generation modules include pulse generation module 1, pulse generation module 2, and pulse generation module t, where t is an integer greater than or equal to 2; the positive terminals of the current sources I1, I2, and Ix are also connected to the input terminals of pulse generation module 1, pulse generation module 2, and pulse generation module t, respectively, and the output terminals of pulse generation module 1, pulse generation module 2, and pulse generation module t are also connected to the input terminals of the logic control module.

[0024] Furthermore, when the PMOS transistors MP1, MP2, and MPn have the same dimensions, the currents of the corresponding current sources I1, I2, and Ix increase progressively; when the PMOS transistors MP1, MP2, and MPn have different dimensions, the currents of the corresponding current sources I1, I2, and Ix are the same. Conversely, when the PMOS transistors MP1, MP2, and MPn have different dimensions, the currents of the corresponding current sources I1, I2, and Ix are the same.

[0025] The working principle of this invention is as follows: Taking PMOS transistors MP1, MP2, and MPn as having the same dimensions, and current sources I1, I2, and Ix increasing sequentially as an example, where x is an integer greater than or equal to 2, refer to... Figure 2 In standby mode, the boost output is turned off. At this time, the OUT standby voltage is equal to VREF-VGS, where VGS is the gate-source operating voltage of MN0.

[0026] 1. When there is no external load connected to the OUT pin, the current of PMOS transistor MP0 is 0, and the current mirrors MP1, MP2, and MPn are also all 0. Under the pull-down action of current sources I1, I2, and Ix, DET1, DET2, and DETn are always at a low level, the pulse generation module output is always at a low level, and the logic control module output signal ON is at a low level, having no effect on the output power supply unit 103. When load 2 is connected, load 2 generates a pull-down current under the action of the OUT standby voltage. This pull-down current flows entirely through PMOS transistor MP0, and MP0 then mirrors this current to PMOS transistors MP1, MP2, and MPn. As long as the current in any of the PMOS transistors MP1, MP2, and MPn is greater than... The current source current of the corresponding branch, for example, as long as the current of MP1 is greater than I1, DET1 immediately flips from low level to high level. After detecting the rising edge of DET1, the pulse generation module outputs a high-level pulse signal SET1. This high-level pulse signal is output to the logic control module, which sets the output signal ON of the logic control module to a high level, thereby activating the output power supply unit to charge the load connected to OUT. When the connected load is fully charged, the current consumed by the load drops to a very low level. At this time, the output light load detection unit detects that the load current is very small and outputs a reset RESET signal to the logic control module, which resets the output signal ON of the logic control module to a low level, shuts down the output power supply unit, and the system enters standby state again.

[0027] 2. In standby mode, if load 2 is continuously connected to the OUT output terminal of the power chip without being removed, current will continuously flow through MP0. Under the mirror effect of PMOS transistor MP0, PMOS transistors MP1, MP2, and MPn will also continuously flow. Here, it is assumed that under the current consumption of the connected load, the current of MP1 is greater than I1, the current of MP2 is greater than I2, and the current of MPn is less than Ix. Therefore, DET1 and DET2 are always at a high level, and DETn is always at a low level. Since the pulse generation module can only generate a positive pulse signal SETn under the rising edge of each DETn signal from low to high, the SETn signals at each level are invalid at this time. If another load is connected to the OUT port at the same time, the current flowing through MP0 will increase. Under the mirror effect of MP0, the current of PMOS transistors MP1, MP2, and MPn will also increase. DET1 and DET2 will always be at a high level. Since DET1 and DET2 do not have a low-to-high transition process, SET1 and SET2 will always remain at a low level. However, as long as the current in any MPn branch exceeds the corresponding current source Ix, DETn will immediately transition from low to high, causing the output signal SETn of the pulse control module n to output a high-level pulse. This will set the output signal ON of the logic control module to output a high level, activating the output power supply unit to charge the load connected to OUT.

[0028] 3. Similarly, if multiple loads are already connected to the OUT port in standby mode and have not been removed, the current of MP0 will increase as soon as another load is connected. Under the mirror effect of MP0, the current of PMOS transistors MP1, MP2, and MPn will increase. As long as the number of current sources I1, I2, and Ix is sufficient and the difference between adjacent current sources is small enough, the increased current of each newly connected load will trigger a new DETn signal to flip, and then activate the output power supply unit to charge the load connected to OUT.

[0029] The required number of current sources I1, I2, and Ix, as well as the difference between adjacent current sources, can be adjusted arbitrarily according to different situations and requirements to ensure that even the smallest actual load can be detected. Theoretically, the larger the value of x and the smaller the difference between adjacent current sources, the higher the detection sensitivity when the load is connected.

[0030] In summary, this invention can detect multiple load connections with only one OUT output port, eliminating the need for multiple OUT output ports. This invention requires only one output path to identify and detect multiple load connections, significantly reducing the cost of multi-path outputs and also reducing the number of chip pins, allowing for a more compact and cheaper package.

[0031] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A power management chip, characterized in that, include: Load connection detection unit, output light load detection unit, output power supply unit; The input signals of the load access detection unit and the output light load detection unit are connected to the output OUT terminal of the output power supply unit, the output signal ON terminal of the load access detection unit is connected to the input terminal of the output power supply unit, and the output signal RESET terminal of the output light load detection unit is connected to the input terminal of the load access detection unit; the output OUT terminal of the output power supply unit is also connected to several loads. The load access detection unit includes: a reference voltage VREF, an output voltage clamping NMOS transistor MN0, multiple PMOS transistors, multiple current sources, multiple pulse generation modules, and a logic control module; The reference voltage VREF is connected to the gate of the NMOS transistor MN0, the source of the NMOS transistor MN0 is connected to the output OUT terminal of the output power supply unit and several loads, and the drain of the NMOS transistor MN0 is electrically connected to the corresponding terminals of several PMOS transistors. The drains of the plurality of PMOS transistors are also electrically connected to the positive terminals of the plurality of current sources and the input terminals of the plurality of pulse generation modules, respectively; the negative terminals of the plurality of current sources are grounded; the output terminals of the plurality of pulse generation modules are all connected to the input terminals of the logic control module, and the output terminals of the logic control module are connected to the output power supply unit; the RESET terminal of the output light load detection unit is also electrically connected to the corresponding terminal of the logic control module.

2. The power management chip according to claim 1, characterized in that, When the output power supply unit stops outputting, the standby voltage of the OUT pin is equal to the reference voltage VREF minus the gate-source voltage VGS of the NMOS transistor MN0.

3. The power management chip according to claim 2, characterized in that, The plurality of PMOS transistors include PMOS transistors MPO, MP1, MP2, to MPn, where n is an integer greater than or equal to 2; The drain of the NMOS transistor MN0 is connected to the gate and drain of the PMOS transistor MP0. The gate of the PMOS transistor MP0 is connected to the gate of the PMOS transistors MP1, MP2, and MPn. The source of the PMOS transistors MP0, MP1, MP2, and MPn is connected to the power supply VDD terminal.

4. The power management chip according to claim 3, characterized in that, The plurality of current sources include current sources I1, I2, to Ix, where x is an integer greater than or equal to 2; The drains of the PMOS transistors MP1, MP2, and MPn are connected to the positive terminals of the current sources I1, I2, and Ix, respectively, and the negative terminals of I1, I2, and Ix are all grounded.

5. The power management chip according to claim 4, characterized in that, The plurality of pulse generation modules include pulse generation module 1, pulse generation module 2, and pulse generation module t, where t is an integer greater than or equal to 2; The positive terminals of the current sources I1, I2, and Ix are also connected to the input terminals of pulse generation module 1, pulse generation module 2, and pulse generation module t, respectively. The output terminals of pulse generation module 1, pulse generation module 2, and pulse generation module t are also connected to the input terminals of the logic control module.

6. The power management chip according to claim 5, characterized in that, When the PMOS transistors MP1, MP2, and MPn have the same size, the currents of the corresponding current sources I1, I2, and Ix increase step by step. When the dimensions of the PMOS transistors MP1, MP2, and MPn are different, the currents of the corresponding current sources I1, I2, and Ix are the same.

7. The power management chip according to claim 6, characterized in that, When the dimensions of the PMOS transistors MP1, MP2, and MPn are different, the currents of the corresponding current sources I1, I2, and Ix are the same.

8. The load access detection method for a power management chip according to any one of claims 1-7, characterized in that, Including the following methods: S1: When a new load is connected to the output OUT port, the PMOS transistor current increases; S2: If the PMOS transistor current increases to a level greater than the current of the corresponding current source, the corresponding detection signal DETn will flip from low level to high level for detection by the pulse generation module. S3: After the pulse generation module detects the rising edge of DETn, it generates a corresponding positive pulse output signal SETn to the logic control unit; S4: The logic control unit output signal ON is set to a high level, activating the output power supply unit to charge the load connected to the OUT terminal; S5: After the connected load is fully charged, the light load detection unit outputs a RESET signal to the logic control module. S6: When the logic control module output signal ON is reset, it outputs a low level, turning off the output power supply unit.

9. The load access detection method according to claim 8, characterized in that, The increase in PMOS transistor current includes an increase in the current of PMOS transistor MP0 and an increase in the mirror current of PMOS transistors MP1, MP2, and MPn.

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