DC-dc converter

Abstract

Embodiments of the present disclosure provide a DC-DC converter, which includes a voltage conversion circuit, a switching circuit, a voltage holding circuit, first and second voltage comparators, a zero-crossing detection circuit, a logic and driving circuit, a power transistor, a freewheeling transistor and an inductor. The voltage conversion circuit converts a first reference voltage into a second reference voltage during a non-dormant period, and otherwise stops working. The switching circuit connects the voltage conversion circuit to a first input terminal of the first voltage comparator during the non-dormant period, and otherwise disconnects. The voltage holding circuit holds the voltage at the first input terminal. A second input terminal of the first voltage comparator is provided with an output voltage. The logic and driving circuit controls the power transistor to be on and the freewheeling transistor to be off when a pulse width modulation signal outputted by the first voltage comparator is at an active level, controls the power transistor to be off and the freewheeling transistor to be on when an inductor current peak value indication signal is at the active level, and controls the power transistor and the freewheeling transistor to be off when a zero-crossing indication signal is at the active level.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to DC-DC converters. Background Technology

[0002] DC-DC converters are commonly used in various electronic devices for DC-DC voltage conversion. Traditional DC-DC converters require a voltage divider resistor between the output voltage terminal and the feedback voltage terminal to achieve different output voltages. The feedback voltage terminal is connected to the input of the error amplifier in the loop, and different output voltages are achieved by adjusting the voltage divider resistor. When a traditional DC-DC converter enters a light-load operating mode, it is desirable for it to switch to a low-power mode. However, this voltage divider resistor also consumes quiescent current, resulting in a high overall quiescent current and low light-load efficiency. In low-power applications, the quiescent current in this voltage divider resistor prevents the DC-DC converter's quiescent current from further decreasing, impacting efficiency. Summary of the Invention

[0003] The embodiments described herein provide a DC-DC converter.

[0004] According to a first aspect of this disclosure, a DC-DC converter is provided. The DC-DC converter includes: a voltage conversion circuit, a switching circuit, a voltage holding circuit, a first voltage comparator, a second voltage comparator, a zero-crossing detection circuit, logic and drive circuits, a power transistor, a freewheeling transistor, and an inductor. The voltage conversion circuit is configured to: convert a first reference voltage into a second reference voltage during a non-sleep period of the DC-DC converter; and to stop operating during a sleep period of the DC-DC converter. The switching circuit is configured to: during a non-sleep period of the DC-DC converter, connect the output of the voltage conversion circuit to a first input of the first voltage comparator via a first node, thereby providing the second reference voltage to the first input of the first voltage comparator; and to disconnect the connection between the voltage conversion circuit and the first input of the first voltage comparator during a sleep period of the DC-DC converter. The voltage holding circuit is configured to: hold the voltage at the first input of the first voltage comparator. A second input of the first voltage comparator is coupled to the output of the DC-DC converter. A pulse-width modulated signal is output from the output of the first voltage comparator. The second voltage comparator is configured to output an effective inductor current peak indication signal when the inductor current flowing through the inductor reaches the peak current threshold. The zero-crossing detection circuit is configured to output an effective zero-crossing indication signal when the inductor current is zero. The logic and drive circuits are configured to control the power transistor to turn on and the freewheeling transistor to turn off when the pulse width modulation signal is effective; control the power transistor to turn off and the freewheeling transistor to turn on when the inductor current peak indication signal is effective; and control both the power transistor and the freewheeling transistor to turn off when the zero-crossing indication signal is effective.

[0005] In some embodiments of this disclosure, the voltage conversion circuit includes: a reference voltage circuit, a first voltage-controlled switch, a first capacitor, an error amplifier, a first transistor, a first feedback resistor, and a second feedback resistor. The reference voltage circuit is configured to generate a first reference voltage. A first terminal of the first voltage-controlled switch is coupled to the output terminal of the reference voltage circuit. A second terminal of the first voltage-controlled switch is coupled to the first input terminal of the error amplifier. The first voltage-controlled switch is configured to close during a non-sleep period of the DC-DC converter and open during a sleep period of the DC-DC converter. A second input terminal of the error amplifier is coupled to the first terminal of the first feedback resistor and the first terminal of the second feedback resistor. The output terminal of the error amplifier is coupled to the control terminal of the first transistor. The error amplifier stops operating during a sleep period of the DC-DC converter. A first terminal of the first capacitor is coupled to the first input terminal of the error amplifier. A second terminal of the first capacitor is coupled to a second voltage terminal. A first terminal of the first transistor is coupled to the second terminal and a first node of the first feedback resistor. The second terminal of the first transistor is coupled to the first voltage terminal. A second terminal of the second feedback resistor is coupled to the second voltage terminal.

[0006] In some embodiments of this disclosure, the switching circuit includes a second voltage-controlled switch. A first terminal of the second voltage-controlled switch is coupled to a first node. A second terminal of the second voltage-controlled switch is coupled to a first input terminal of a first voltage comparator. The second voltage-controlled switch is configured to close during a non-dormant period of the DC-DC converter and to open during a dormant period of the DC-DC converter.

[0007] In some embodiments of this disclosure, the voltage holding circuit includes a second capacitor. A first terminal of the second capacitor is coupled to a first input terminal of a first voltage comparator. A second terminal of the second capacitor is coupled to a second voltage terminal.

[0008] In some embodiments of this disclosure, the first voltage comparator switches to a low-current mode during a dormant period of the DC-DC converter.

[0009] In some embodiments of this disclosure, the DC-DC converter further includes a sleep control circuit. The sleep control circuit is configured to generate a sleep indicator signal based on a zero-crossing indicator signal. Specifically, the sleep indicator signal is at an invalid level when the zero-crossing indicator signal is at an invalid level. The sleep indicator signal flips to an valid level when the zero-crossing indicator signal flips to an valid level. After a first time period following the start of the sleep indicator signal flipping to a valid level, the sleep indicator signal flips to an invalid level and remains at an invalid level for a second time period before flipping to a valid level.

[0010] In some embodiments of this disclosure, the sleep control circuit includes: a ramp signal generation circuit, a timing reset circuit, and a sleep signal output circuit. The ramp signal generation circuit is configured to generate a ramp signal and provide it to the sleep signal output circuit via a second node. The ramp signal rises to an active level when the ramp signal's rise time reaches a first time interval. The timing reset circuit is configured to reset the ramp signal when the sleep indicator signal flips to an inactive level for a second time interval. The sleep signal output circuit is configured to have an inactive sleep indicator signal when the zero-crossing indicator signal is at an inactive level or the ramp signal is at an active level; otherwise, the sleep indicator signal is at an active level.

[0011] In some embodiments of this disclosure, the ramp signal generation circuit includes a bias current source and a third capacitor. The bias current source is configured to provide a bias current to a first terminal of the third capacitor. The first terminal of the third capacitor is coupled to a second node. The second terminal of the third capacitor is coupled to a second voltage terminal.

[0012] In some embodiments of this disclosure, the timing reset circuit includes a first unidirectional delay circuit and a second transistor. The first unidirectional delay circuit is configured to control the second transistor to turn on when the time for the sleep indicator signal to flip to an invalid level reaches a second time period. The first terminal of the second transistor is coupled to a second voltage terminal. The second terminal of the second transistor is coupled to a second node.

[0013] In some embodiments of this disclosure, the sleep signal output circuit includes: a second unidirectional delay circuit, a first inverter, and an OR gate. The second unidirectional delay circuit is configured to output a delayed zero-crossing indication signal when the time it takes for the zero-crossing indication signal to flip to an effective level reaches a third time interval. The input of the first inverter is coupled to the output of the second unidirectional delay circuit. The output of the first inverter is coupled to the second input of the OR gate. The first input of the OR gate is coupled to a second node. The sleep indication signal is output from the output of the OR gate.

[0014] In some embodiments of this disclosure, the sleep control circuit includes: a bias current source, a third capacitor, a first inverter, a second inverter, a third inverter, a first unidirectional delay circuit, a second unidirectional delay circuit, a second transistor, a third transistor, and an OR gate. The bias current source is configured to provide a bias current to a first terminal of the third capacitor. The first terminal of the third capacitor is coupled to the input terminal of the second inverter, the second terminal of the second transistor, and the second terminal of the third transistor. The second terminal of the third capacitor is coupled to a second voltage terminal. The control terminal of the third transistor is coupled to the output terminal of the second inverter and the input terminal of the third inverter. The first terminal of the third transistor is coupled to a first voltage terminal. The output terminal of the third inverter is coupled to the first input terminal of the OR gate. The first unidirectional delay circuit is configured to control the second transistor to turn on when the time for the sleep indicator signal to flip to an invalid level reaches a second time period. The first terminal of the second transistor is coupled to the second voltage terminal. The second unidirectional delay circuit is configured to output a delayed zero-crossing indicator signal when the time for the zero-crossing indicator signal to flip to an valid level reaches a third time period. The input terminal of the first inverter is coupled to the output terminal of the second unidirectional delay circuit. The output of the first inverter is coupled to the second input of the OR gate. A sleep indicator signal is output from the output of the OR gate.

[0015] In some embodiments of this disclosure, the bias current source includes a fourth to an eighth transistor and a startup circuit. The startup circuit is configured to provide a startup current to the fourth transistor when the DC-DC converter is powered on, and to cease operation when the bias current source is capable of generating a bias current. The control terminal and second terminal of the fourth transistor are coupled to the output terminal of the startup circuit, the second terminal of the fifth transistor, the control terminal of the seventh transistor, and the control terminal of the eighth transistor. The first terminal of the fourth transistor is coupled to a first voltage terminal. The control terminal of the fifth transistor is coupled to the control terminal and the second terminal of the sixth transistor, as well as the second terminal of the seventh transistor. The first terminal of the fifth transistor is coupled to a first terminal of a first resistor. The second terminal of the first resistor is coupled to a first terminal of a second resistor and the first terminal of the sixth transistor. The second terminal of the second resistor is coupled to a second voltage terminal. The first terminal of the seventh transistor is coupled to the first voltage terminal. The first terminal of the eighth transistor is coupled to the first voltage terminal. The second terminal of the eighth transistor is coupled to a first terminal of a third capacitor.

[0016] According to a second aspect of this disclosure, a DC-DC converter is provided. The DC-DC converter includes: a reference voltage circuit, a first voltage-controlled switch, a first capacitor, an error amplifier, a first transistor, a first feedback resistor, a second feedback resistor, a second voltage-controlled switch, a second capacitor, a first voltage comparator, a second voltage comparator, a zero-crossing detection circuit, logic and drive circuitry, a power transistor, a freewheeling transistor, and an inductor. The reference voltage circuit is configured to generate a first reference voltage. A sleep indicator signal is provided at the controlled terminal of the first voltage-controlled switch. A first terminal of the first voltage-controlled switch is coupled to the output terminal of the reference voltage circuit. A second terminal of the first voltage-controlled switch is coupled to the first input terminal of the error amplifier. The sleep indicator signal is at an invalid level during a non-sleep period of the DC-DC converter and at an active level during a sleep period of the DC-DC converter. The second input terminal of the error amplifier is coupled to the first terminal of the first feedback resistor and the first terminal of the second feedback resistor. The output terminal of the error amplifier is coupled to the control terminal of the first transistor. The error amplifier stops operating during a sleep period of the DC-DC converter. A first terminal of the first capacitor is coupled to the first input terminal of the error amplifier. The second terminal of the first capacitor is coupled to the second voltage terminal. The first terminal of the first transistor is coupled to the second terminal of the first feedback resistor and the first terminal of the second voltage-controlled switch. The second terminal of the first transistor is coupled to the first voltage terminal. The second terminal of the second feedback resistor is coupled to the second voltage terminal. The controlled terminal of the second voltage-controlled switch is provided with a sleep indicator signal. The second terminal of the second voltage-controlled switch is coupled to the first input terminal of the first voltage comparator. The first terminal of the second capacitor is coupled to the first input terminal of the first voltage comparator. The second terminal of the second capacitor is coupled to the second voltage terminal. The second input terminal of the first voltage comparator is coupled to the output terminal of the DC-DC converter. A pulse width modulated signal is output from the output terminal of the first voltage comparator. The second voltage comparator is configured to output an effective level inductor current peak indicator signal when the inductor current flowing through the inductor reaches the peak current threshold. The zero-crossing detection circuit is configured to output an effective level zero-crossing indicator signal when the inductor current is zero. The logic and drive circuitry are configured to: control the power transistor to turn on and the freewheeling transistor to turn off when the pulse width modulation signal is at an active level; control the power transistor to turn off and the freewheeling transistor to turn on when the inductor current peak indication signal is at an active level; and control both the power transistor and the freewheeling transistor to turn off when the zero-crossing indication signal is at an active level.

[0017] According to a third aspect of this disclosure, a chip is provided. The chip includes a DC-DC converter as described in a first or second aspect of this disclosure.

[0018] According to a fourth aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in a third aspect of this disclosure. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0020] Figure 1 An exemplary topology diagram of a DC-DC converter;

[0021] Figure 2 This is a schematic block diagram of a DC-DC converter according to an embodiment of the present disclosure;

[0022] Figure 3 This is an exemplary circuit diagram of a DC-DC converter according to embodiments of the present disclosure;

[0023] Figure 4 This is a further exemplary circuit diagram of a DC-DC converter according to embodiments of the present disclosure;

[0024] Figure 5 yes Figure 4 A schematic block diagram of the sleep control circuit in the image;

[0025] Figure 6 yes Figure 4 An exemplary circuit diagram of the sleep control circuit in the example;

[0026] Figure 7 yes Figure 4 Another exemplary circuit diagram of the sleep control circuit in the diagram;

[0027] Figure 8 yes Figure 6 and Figure 7 An exemplary circuit diagram of the bias current source in the circuit; and

[0028] Figure 9 This is a timing diagram of some signals used in a DC-DC converter according to an embodiment of the present disclosure.

[0029] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0032] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0033] Figure 1 An exemplary topology diagram of a DC-DC converter 100 is shown. The DC-DC converter 100 converts the input voltage VIN into an output voltage VOUT. Figure 1 The DC-DC converter 100 shows an upper transistor Q1, a lower transistor Q2, a current sampling circuit sense, an inductor L, an output capacitor Cout, a first feedback resistor Rf1, a second feedback resistor Rf2, a reference voltage circuit BG, an error amplifier EA, a compensation capacitor C, a PWM voltage comparator COMP, logic and drive circuits, and a zero-crossing detection circuit.

[0034] The non-inverting input of error amplifier EA is coupled to the reference voltage circuit BG, thus providing a reference voltage Vref. The inverting input of error amplifier EA is coupled to the feedback voltage terminal FB between the first feedback resistor Rf1 and the second feedback resistor Rf2. The first feedback resistor Rf1 and the second feedback resistor Rf2 divide the output voltage VOUT of the DC-DC converter. The error signal Vea output from the output of error amplifier EA is provided to the non-inverting input of PWM voltage comparator COMP. The current sampling circuit sense acquires the current signal flowing through the upper transistor Q1. This current signal is superimposed with the ramp signal Slop and then provided to the inverting input of PWM voltage comparator COMP. PWM voltage comparator COMP outputs a pulse width modulation signal PWM to the logic and drive circuit. The logic and drive circuit generates the upper transistor drive signal DR_Q1 and the lower transistor drive signal DR_Q2 based on the pulse width modulation signal PWM, the clock signal CLK, and the zero-crossing detection signal ZCD output by the zero-crossing detection circuit. The upper transistor drive signal DR_Q1 is used to control the conduction and cutoff of the upper transistor Q1. The lower transistor drive signal DR_Q2 is used to control the conduction and cutoff of the lower transistor Q2.

[0035] exist Figure 1 In the example, different output voltages VOUT can be achieved by controlling the ratio of the resistance values ​​of the first feedback resistor Rf1 and the second feedback resistor Rf2. The first feedback resistor Rf1 and the second feedback resistor Rf2 are essential for voltage regulation. However, they generate additional quiescent current, reducing light-load efficiency.

[0036] Embodiments of this disclosure provide a DC-DC converter capable of eliminating quiescent current in the first feedback resistor Rf1 and the second feedback resistor Rf2 during sleep periods. Figure 2 A schematic block diagram of a DC-DC converter 200 according to an embodiment of the present disclosure is shown. The DC-DC converter 200 includes: a voltage conversion circuit 210, a switching circuit 220, a voltage holding circuit 230, a first voltage comparator CMP1, a second voltage comparator CMP2, a zero-crossing detection circuit 250, a logic and drive circuit 240, a power transistor, a freewheeling transistor, and an inductor L.

[0037] Figure 2 Let's take a buck converter as an example. Figure 2In the example, the upper transistor Q1 is a power transistor, and the lower transistor Q2 is a freewheeling transistor. The control terminal of the upper transistor Q1 is provided with the upper transistor drive signal DR_Q1 output by the logic and drive circuit 240. The first terminal of the upper transistor Q1 is coupled to the input voltage terminal VIN. The second terminal of the upper transistor Q1 is coupled to the second terminal of the lower transistor Q2 and the first terminal (node ​​SW) of the inductor L. The control terminal of the lower transistor Q2 is provided with the lower transistor drive signal DR_Q2 output by the logic and drive circuit 240. The first terminal of the lower transistor Q2 is coupled to the second voltage terminal V2. The second terminal of the inductor L is coupled to the output voltage terminal VOUT and the first terminal of the output capacitor Cout. The second terminal of the output capacitor Cout is coupled to the second voltage terminal V2.

[0038] The DC-DC converter according to embodiments of this disclosure can also be a boost converter. In the boost converter, the upper transistor Q1 is a freewheeling transistor, and the lower transistor Q2 is a power transistor.

[0039] The input terminal of voltage conversion circuit 210 is coupled to a first reference voltage terminal Vref1 and a sleep indicator signal terminal SLP. The output terminal of voltage conversion circuit 210 is coupled to switching circuit 220 via a first node N1. Voltage conversion circuit 210 is configured to: convert the first reference voltage Vref1 to a second reference voltage Vref2 during a non-sleep period of DC-DC converter 200; and to stop operating during a sleep period of DC-DC converter 200. In some embodiments of this disclosure, DC-DC converter 200 can be controlled to enter a sleep period by a sleep indicator signal SLP from the sleep indicator signal terminal SLP. DC-DC converter 200 is in a sleep period when sleep indicator signal SLP is at an active level. DC-DC converter 200 is in a non-sleep period when sleep indicator signal SLP is at an inactive level. In some embodiments of this disclosure, when voltage conversion circuit 210 stops operating, the second reference voltage Vref2 is equal to zero volts. When voltage conversion circuit 210 is operating normally, the second reference voltage Vref2 is greater than the first reference voltage Vref1.

[0040] Switching circuit 220 is coupled to the sleep indicator signal terminal SLP. Switching circuit 220 is coupled to the output terminal of voltage conversion circuit 210 via first node N1. Switching circuit 220 is also coupled to the first input terminal of first voltage comparator CMP1 and voltage holding circuit 230. Switching circuit 220 is configured to: when the DC-DC converter 200 is in a non-sleep period (sleep indicator signal SLP is at an invalid level), connect the output terminal of voltage conversion circuit 210 to the first input terminal of first voltage comparator CMP1 via first node N1, thereby providing the second reference voltage Vref2 to the first input terminal of first voltage comparator CMP1; and disconnect the connection between voltage conversion circuit 210 and the first input terminal of first voltage comparator CMP1 when the DC-DC converter 200 is in a sleep period (sleep indicator signal SLP is at an active level).

[0041] Voltage holding circuit 230 is coupled to the first input terminal of the first voltage comparator CMP1. Voltage holding circuit 230 is configured to hold the voltage Vea at the first input terminal of the first voltage comparator CMP1.

[0042] The second input terminal of the first voltage comparator CMP1 is coupled to the output terminal of the DC-DC converter 200, thereby providing an output voltage VOUT. A pulse width modulation (PWM) signal is output from the output terminal of the first voltage comparator CMP1. In some embodiments of this disclosure, the first voltage comparator CMP1 is a hysteresis comparator. In some embodiments of this disclosure, during the sleep period of the DC-DC converter 200, the first voltage comparator CMP1 switches to a low-current mode, that is, the bias current in the first voltage comparator CMP1 decreases to reduce power consumption.

[0043] The first input of the second voltage comparator CMP2 is coupled to the peak reference voltage terminal Vref_peak. The second input of the second voltage comparator CMP2 is coupled to node SW. The output of the second voltage comparator CMP2 outputs an inductor current peak indication signal PeakOut. When the inductor current IL is zero, the voltage at node SW is higher than the peak reference voltage Vref_peak from the peak reference voltage terminal Vref_peak, and the inductor current peak indication signal PeakOut is at an invalid level. As the inductor current IL increases, the voltage at node SW decreases. When the voltage at node SW decreases to the peak reference voltage Vref_peak, the inductor current peak indication signal PeakOut output by the second voltage comparator CMP2 flips to an active level. In other words, the second voltage comparator CMP2 is configured to: output an invalid inductor current peak indication signal PeakOut when the inductor current IL flowing through inductor L has not reached the peak current threshold; and output an active inductor current peak indication signal PeakOut when the inductor current IL flowing through inductor L has reached the peak current threshold. In some embodiments of this disclosure, the second voltage comparator CMP2 is a hysteresis voltage comparator.

[0044] Zero-crossing detection circuit 250 is coupled to node SW and logic and drive circuit 240. Zero-crossing detection circuit 250 is configured to output a valid zero-crossing indication signal ZCD when the inductor current IL is zero. When the inductor current IL is not zero, the zero-crossing indication signal ZCD output by zero-crossing detection circuit 250 is invalid. In some embodiments of this disclosure, the valid level of the zero-crossing indication signal ZCD is high, and the invalid level of the zero-crossing indication signal ZCD is low.

[0045] The logic and drive circuit 240 is configured to: control the power transistor to turn on and the freewheeling transistor to turn off when the pulse width modulation signal PWM is at an active level; control the power transistor to turn off and the freewheeling transistor to turn on when the inductor current peak indication signal PeakOut is at an active level; and control both the power transistor and the freewheeling transistor to turn off when the zero-crossing indication signal ZCD is at an active level. In some embodiments of this disclosure, when the zero-crossing indication signal ZCD is at an active level, the sleep indication signal SLP is at an active level, and the DC-DC converter 200 is in a sleep period. When the zero-crossing indication signal ZCD is at an inactive level, the sleep indication signal SLP is at an inactive level, and the DC-DC converter 200 is in a non-sleep period.

[0046] In some embodiments of this disclosure, the active level of the sleep indicator signal SLP is low. The inactive level of the sleep indicator signal SLP is high.

[0047] exist Figure 2In the example, the second voltage terminal V2 is grounded. The upper transistor Q1 is a PMOS transistor. The lower transistor Q2 is an NMOS transistor. The first input terminal of the first voltage comparator CMP1 is a non-inverting input terminal. The second input terminal of the first voltage comparator CMP1 is an inverting input terminal. The effective level of the pulse width modulation signal PWM is high. The ineffective level of the pulse width modulation signal PWM is low. The first input terminal of the second voltage comparator CMP2 is a non-inverting input terminal. The second input terminal of the second voltage comparator CMP2 is an inverting input terminal. The effective level of the inductor current peak indication signal PeakOut is high. The ineffective level of the inductor current peak indication signal PeakOut is low. Those skilled in the art should understand that, based on the above inventive concept... Figure 2 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 2 The examples shown have different settings.

[0048] When the DC-DC converter 200 is in its non-sleep period (normal operation), the second reference voltage Vref2 is provided to the first input terminal of the first voltage comparator CMP1. The voltage Vea at the first input terminal of the first voltage comparator CMP1 is equal to the second reference voltage Vref2. When the output voltage VOUT < Vea, the pulse width modulation signal PWM output by the first voltage comparator CMP1 is at an active level (high level), the upper transistor Q1 is turned on and the lower transistor Q2 is turned off, and the inductor current IL rises. When the current flowing through the upper transistor Q1 reaches the peak current, the voltage at node SW drops to the peak reference voltage Vref_peak. Therefore, the peak inductor current indication signal PeakOut output by the second voltage comparator CMP2 flips to an active level (high level). At this time, the upper transistor Q1 is turned off and the lower transistor Q2 is turned on, and the inductor current IL decreases. When the inductor current IL drops to 0A, the zero-crossing indication signal ZCD flips to an active level (high level), and both the upper transistor Q1 and the lower transistor Q2 are turned off. In some embodiments of this disclosure, the second voltage comparator CMP2 stops operating when the zero-crossing indication signal ZCD is at an active level.

[0049] With both upper transistor Q1 and lower transistor Q2 off, if the output voltage VOUT > Vea, the DC-DC converter 200 enters a sleep phase. When the load pulls the output voltage VOUT down to less than Vea, the pulse width modulation signal (PWM) flips to an active level (high level), turning on upper transistor Q1 again. This process is then repeated. Therefore, the average value of the output voltage VOUT is approximately Vea, and Vea is equal to the second reference voltage Vref2. The second reference voltage Vref2 is generated from the first reference voltage Vref1; therefore, the voltage conversion circuit 210 can regulate the output voltage VOUT according to the first reference voltage Vref1.

[0050] During the sleep period of the DC-DC converter 200, the switching circuit 220 disconnects the voltage conversion circuit 210 from the first input terminal of the first voltage comparator CMP1. The voltage conversion circuit 210 stops operating, thereby reducing the quiescent current during the sleep period. The voltage holding circuit 230 maintains the voltage Vea at the first input terminal of the first voltage comparator CMP1 at the second reference voltage Vref2. This allows the loop to be quickly established when the DC-DC converter 200 returns to the non-sleep period.

[0051] Figure 3 An exemplary circuit diagram of a DC-DC converter 300 according to an embodiment of the present disclosure is shown. The voltage conversion circuit 310 includes: a reference voltage circuit BG, a first voltage-controlled switch S1, a first capacitor C1, an error amplifier EA, a first transistor M1, a first feedback resistor Rf1, and a second feedback resistor Rf2.

[0052] A reference voltage circuit BG is configured to generate a first reference voltage Vref1. A first terminal of a first voltage-controlled switch S1 is coupled to the output of the reference voltage circuit BG. A second terminal of the first voltage-controlled switch S1 is coupled to the first input of the error amplifier EA. The controlled terminal of the first voltage-controlled switch S1 is coupled to the sleep indicator signal terminal SLP. The first voltage-controlled switch S1 is configured to close during the non-sleep period of the DC-DC converter 300 and open during the sleep period of the DC-DC converter 300.

[0053] The second input terminal of the error amplifier EA is coupled to the first terminal of the first feedback resistor Rf1 and the first terminal of the second feedback resistor Rf2. The output terminal of the error amplifier EA is coupled to the control terminal of the first transistor M1. The error amplifier EA stops operating when the DC-DC converter 300 is in a sleep period (the sleep indicator signal SLP is at an active level). In some embodiments of this disclosure, the sleep indicator signal SLP can control the supply voltage of the error amplifier EA, and the error amplifier EA can be stopped by setting the supply voltage of the error amplifier EA to zero volts. In other embodiments of this disclosure, the sleep indicator signal SLP can control the bias current of the error amplifier EA, and the error amplifier EA can be stopped by setting the bias current of the error amplifier EA to zero amperes.

[0054] The first terminal of the first capacitor C1 is coupled to the first input terminal of the error amplifier EA. The second terminal of the first capacitor C1 is coupled to the second voltage terminal V2. The first terminal of the first transistor M1 is coupled to the second terminal of the first feedback resistor Rf1 and the first node N1. The second terminal of the first transistor M1 is coupled to the first voltage terminal V1. The second terminal of the second feedback resistor Rf2 is coupled to the second voltage terminal V2.

[0055] The switching circuit 320 includes a second voltage-controlled switch S2. A first terminal of the second voltage-controlled switch S2 is coupled to a first node N1. A second terminal of the second voltage-controlled switch S2 is coupled to a first input terminal of a first voltage comparator CMP1. The controlled terminal of the second voltage-controlled switch S2 is coupled to a sleep indicator signal terminal SLP, thereby providing a sleep indicator signal SLP. The second voltage-controlled switch S2 is configured to close during the non-sleep period of the DC-DC converter 300 and to open during the sleep period of the DC-DC converter 300.

[0056] The voltage holding circuit 330 includes a second capacitor C2. The first terminal of the second capacitor C2 is coupled to the first input terminal of the first voltage comparator CMP1. The second terminal of the second capacitor C2 is coupled to a second voltage terminal V2.

[0057] exist Figure 3 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1 is an NMOS transistor. The first input terminal of the error amplifier EA is the non-inverting input terminal. The second input terminal of the error amplifier EA is the inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 3 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 3 The examples shown have different settings.

[0058] When the DC-DC converter 300 is in its non-sleep period (normal operation), according to the virtual short and virtual open characteristics of the error amplifier EA, the voltage at the first terminal of the first feedback resistor Rf1 is equal to the first reference voltage Vref1. Therefore:

[0059] Vref2=Vref1×(Rf1+Rf2) / Rf2 (1)

[0060] Where Vref2 represents the voltage value of the second reference voltage Vref2, Vref1 represents the voltage value of the first reference voltage Vref1, Rf1 represents the resistance value of the first feedback resistor Rf1, and Rf2 represents the resistance value of the second feedback resistor Rf2. When the second voltage-controlled switch S2 is closed, the second reference voltage Vref2 is provided to the first input terminal of the first voltage comparator CMP1. Thus, through loop adjustment, the output voltage VOUT of the DC-DC converter 300 is set to the second reference voltage Vref2. According to equation (1), the voltage conversion circuit 310 can adjust the output voltage VOUT by adjusting the resistance value of the first feedback resistor Rf1 or the resistance value of the second feedback resistor Rf2.

[0061] During the sleep period of the DC-DC converter 300, the second voltage-controlled switch S2 is open, and the second reference voltage Vref2 is no longer supplied to the first input terminal of the first voltage comparator CMP1. The second capacitor C2 ensures that the voltage Vea at the first input terminal of the first voltage comparator CMP1 is maintained at the second reference voltage Vref2. This allows the loop to be quickly established when the DC-DC converter 300 returns to the non-sleep period. At this time, the error amplifier EA stops operating. Therefore, the current flowing through the first feedback resistor Rf1 and the second feedback resistor Rf2 is zero, thereby reducing the quiescent current of the DC-DC converter 300 during the sleep period.

[0062] The inventors of this disclosure discovered that the components in the DC-DC converter 300 may have leakage problems. Therefore, during the sleep period, it is necessary to periodically refresh the voltage Vref1 at the first input terminal of the error amplifier EA and the voltage Vea at the first input terminal of the first voltage comparator CMP1. Figure 4 The embodiment proposes to further include a sleep control circuit 460 in the DC-DC converter 400. The sleep control circuit 460 is configured to generate a sleep indicator signal SLP based on a zero-crossing indicator signal ZCD. Specifically, the sleep indicator signal SLP is at an invalid level when the zero-crossing indicator signal ZCD is at an invalid level. The sleep indicator signal SLP flips to an valid level when the zero-crossing indicator signal ZCD flips to an valid level. After a first time period following the start of the sleep indicator signal SLP flipping to an valid level, the sleep indicator signal SLP flips to an invalid level and remains at an invalid level for a second time period before flipping to an valid level. The lengths of the first and second time periods can be set according to the specific application.

[0063] In this way, the DC-DC converter 400 is periodically woken up during the sleep period to refresh Vref1 and Vea, thereby avoiding the instability of the output voltage VOUT caused by component leakage.

[0064] Figure 5 yes Figure 4 A schematic block diagram of the sleep control circuit 460. The sleep control circuit 560 includes: a ramp signal generation circuit 561, a timing clearing circuit 562, and a sleep signal output circuit 563.

[0065] The output of the ramp signal generation circuit 561 is coupled to the output of the timing reset circuit 562 and the input of the sleep signal output circuit 563 via the second node N2. The ramp signal generation circuit 561 is configured to generate a ramp signal and provide it to the sleep signal output circuit 563 via the second node N2. Specifically, the ramp signal rises to an effective level when the rise time of the ramp signal reaches a first time interval.

[0066] The timing clear circuit 562 is coupled to the output of the ramp signal generation circuit 561 and the input of the sleep signal output circuit 563 via the second node N2. The timing clear circuit 562 is configured to: reset the ramp signal (i.e., clear the voltage at the second node N2) when the sleep indicator signal SLP has been flipped to an invalid level for a second time period; otherwise, it does not affect the voltage at the second node N2.

[0067] The input of the sleep signal output circuit 563 is coupled to the output of the ramp signal generation circuit 561 and the output of the timing clear circuit 562 via the second node N2. The sleep signal output circuit 563 is also coupled to the output of the zero-crossing detection circuit 250. The sleep signal output circuit 563 is configured such that: when the zero-crossing indicator signal ZCD is at an invalid level or the ramp signal is at an active level, the sleep indicator signal SLP is at an invalid level; otherwise, the sleep indicator signal SLP is at an active level.

[0068] When the zero-crossing indicator signal ZCD is at an invalid level, the sleep indicator signal SLP is also at an invalid level. The ramp signal is reset when the sleep indicator signal SLP has been at an invalid level for a second time interval. When the zero-crossing indicator signal ZCD flips to an active level, the sleep indicator signal SLP flips to an active level. The timing clearing circuit 562 does not affect the voltage at the second node N2, and the ramp signal begins to rise. When the ramp signal rises for a first time interval, the ramp signal rises to an active level, causing the sleep indicator signal SLP to flip to an invalid level. The ramp signal is reset when the sleep indicator signal SLP has been at an invalid level for a second time interval, causing the sleep indicator signal SLP to flip to an active level.

[0069] In this way, the DC-DC converter 400 is woken up during the first time period during the sleep period to refresh Vref1 and Vea, and then enters the sleep period again when the wake-up time reaches the second time period.

[0070] As described above, in some embodiments of this disclosure, the first voltage comparator CMP1 switches to a low-current mode during the DC-DC converter's sleep period. In other embodiments of this disclosure, the first voltage comparator CMP1 switches to a low-current mode when the zero-crossing indicator signal ZCD is at an active level. Thus, during the aforementioned second wake-up period, the first voltage comparator CMP1 is also in a low-current mode, further reducing power consumption.

[0071] Figure 6 yes Figure 4 An exemplary circuit diagram of the sleep control circuit 460 in the circuit. Figure 6In the sleep control circuit 660, the ramp signal generation circuit 661 includes a bias current source IS and a third capacitor C3. The bias current source IS is configured to provide a bias current Ibias to the first terminal of the third capacitor C3. The first terminal of the third capacitor C3 is coupled to the second node N2. The second terminal of the third capacitor C3 is coupled to the second voltage terminal V2.

[0072] The timer reset circuit 662 includes a first unidirectional delay circuit DL1 and a second transistor M2. The first unidirectional delay circuit DL1 is configured to control the second transistor M2 to turn on when the time for the sleep indicator signal SLP to flip to an invalid level reaches a second time period. The first unidirectional delay circuit DL1 is also configured to directly control the second transistor M2 to turn off when the sleep indicator signal SLP flips to an active level.

[0073] The first terminal of the second transistor M2 is coupled to the second voltage terminal V2. The second terminal of the second transistor M2 is coupled to the second node N2.

[0074] The sleep signal output circuit 663 includes a second unidirectional delay circuit DL2, a first inverter NG1, and an OR gate. The second unidirectional delay circuit DL2 is configured to output a delayed zero-crossing indication signal when the time for the zero-crossing indicator signal ZCD to flip to an active level reaches a third time interval. In other words, the second unidirectional delay circuit DL2 delays the transition edge of the zero-crossing indicator signal ZCD from an inactive level to an active level by the aforementioned third time interval. The second unidirectional delay circuit DL2 is also configured to output an invalid zero-crossing indication signal when the time for the zero-crossing indicator signal ZCD to flip to an active level has not reached the third time interval or when the zero-crossing indicator signal ZCD is at an invalid level. The input of the first inverter NG1 is coupled to the output of the second unidirectional delay circuit DL2. The output of the first inverter NG1 is coupled to the second input of the OR gate. The first input of the OR gate is coupled to the second node N2. The sleep indicator signal SLP is output from the output of the OR gate. By setting the second unidirectional delay circuit DL2, noise on the zero-crossing indicator signal ZCD can be prevented from causing the sleep indicator signal SLP to erroneously flip to an active level. Furthermore, setting the second unidirectional delay circuit DL2 can also prevent the zero-crossing indicator signal ZCD from being active for too short a time, thus preventing the DC-DC converter from quickly exiting the sleep period after entering it. The length of the third time period can be set according to the specific application.

[0075] When the zero-crossing indicator signal ZCD is at an invalid level (low level), the sleep indicator signal SLP output by the OR gate is at an invalid level (high level). When the sleep indicator signal SLP has been at an invalid level for a second time interval, the second transistor M2 turns on, and the ramp signal is reset to zero volts. When the zero-crossing indicator signal ZCD has been at an active level (high level) for a third time interval, the sleep indicator signal SLP output by the OR gate turns on to an active level (low level), and the second transistor M2 turns off. At this time, the bias current Ibias begins to charge the third capacitor C3, and the ramp signal begins to rise. When the ramp signal rises for a first time interval, the ramp signal rises to an active level, and the first input of the OR gate receives a high-level signal, causing the sleep indicator signal SLP to flip to an invalid level (high level). When the sleep indicator signal SLP has been at an invalid level for a second time interval, the second transistor M2 turns on, and the ramp signal is reset to zero volts, causing the sleep indicator signal SLP to flip to an active level (low level).

[0076] Figure 7 yes Figure 4 Another exemplary circuit diagram of the sleep control circuit 760 in the circuit. Figure 6 Based on the sleep control circuit 660 shown, the sleep control circuit 760 further includes: a second inverter NG2, a third inverter NG3, and a third transistor M3. Figure 7In the example, the bias current source IS is configured to provide a bias current Ibias to the first terminal of the third capacitor C3. The first terminal of the third capacitor C3 is coupled to the input terminal of the second inverter NG2, the second terminal of the second transistor M2, and the second terminal of the third transistor M3. The second terminal of the third capacitor C3 is coupled to the second voltage terminal V2. The control terminal of the third transistor M3 is coupled to the output terminal of the second inverter NG2 and the input terminal of the third inverter NG3. The first terminal of the third transistor M3 is coupled to the first voltage terminal V1. The output terminal of the third inverter NG3 is coupled to the first input terminal of the OR gate OR. The first unidirectional delay circuit DL1 is configured to control the second transistor M2 to turn on when the time for the sleep indicator signal SLP to flip to an invalid level reaches a second time period. The first terminal of the second transistor M2 is coupled to the second voltage terminal V2. The second unidirectional delay circuit DL2 is configured to output a delayed zero-crossing indicator signal when the time for the zero-crossing indicator signal ZCD to flip to an active level reaches a third time period. In other words, the second unidirectional delay circuit DL2 delays the transition edge of the zero-crossing indicator signal ZCD from an invalid level to an valid level by the aforementioned third time period. The second unidirectional delay circuit DL2 is also configured to output an invalid zero-crossing indicator signal if the time for the zero-crossing indicator signal ZCD to transition to an valid level has not reached the third time period or if the zero-crossing indicator signal ZCD is at an invalid level. The input of the first inverter NG1 is coupled to the output of the second unidirectional delay circuit DL2. The output of the first inverter NG1 is coupled to the second input of the OR gate. The sleep indicator signal SLP is output from the output of the OR gate.

[0077] When the zero-crossing indicator signal ZCD is at an invalid level (low level), the sleep indicator signal SLP output by the OR gate is at an invalid level (high level). When the sleep indicator signal SLP flips to an invalid level for the second time interval, the second transistor M2 turns on, and the ramp signal is reset to zero volts. At this time, the second inverter NG2 outputs a high-level signal, and the third transistor M3 is off. When the zero-crossing indicator signal ZCD flips to an active level (high level) for the third time interval, the sleep indicator signal SLP output by the OR gate flips to an active level (low level), and the second transistor M2 is off. At this time, the bias current Ibias begins to charge the third capacitor C3, and the ramp signal begins to rise. After the inversion effect of the second inverter NG2, the third transistor M3 turns on, thereby accelerating the rise speed of the ramp signal. When the rise time of the ramp signal reaches the first time interval, the ramp signal rises to an active level (high level). The third inverter NG3 provides a high-level signal to the first input terminal of the OR gate, thereby causing the sleep indicator signal SLP to flip to an invalid level (high level). When the second time period arrives at the time when the sleep indicator signal SLP flips to an invalid level, the second transistor M2 is turned on, the ramp signal is reset to zero volts, thereby causing the sleep indicator signal SLP to flip to an active level (low level).

[0078] exist Figure 7 In the example, the rise time of the ramp signal is accelerated by the third transistor M3, so the bias current Ibias can be set to be faster than... Figure 6 The Ibias is smaller to further save static power consumption.

[0079] Figure 8 Show Figure 6 and Figure 7An exemplary circuit diagram of the bias current source IS is shown below. The bias current source IS includes: a fourth transistor M4 to an eighth transistor M8 and a startup circuit ST. The startup circuit ST is configured to provide a startup current to the fourth transistor M4 when the DC-DC converter is powered on, and to stop operating when the bias current source IS is able to generate a bias current Ibias. The control terminal and the second terminal of the fourth transistor M4 are coupled to the output terminal of the startup circuit ST, the second terminal of the fifth transistor M5, the control terminal of the seventh transistor M7, and the control terminal of the eighth transistor M8. The first terminal of the fourth transistor M4 is coupled to a first voltage terminal V1. The control terminal of the fifth transistor M5 is coupled to the control terminal and the second terminal of the sixth transistor M6 and the second terminal of the seventh transistor M7. The first terminal of the fifth transistor M5 is coupled to the first terminal of the first resistor Ra. The second terminal of the first resistor Ra is coupled to the first terminal of the second resistor Rb and the first terminal of the sixth transistor M6. The second terminal of the second resistor Rb is coupled to a second voltage terminal V2. The first terminal of the seventh transistor M7 is coupled to the first voltage terminal V1. The first terminal of the eighth transistor M8 is coupled to the first voltage terminal V1. The second terminal of the eighth transistor M8 is coupled to the first terminal of the third capacitor C3. The current flowing through the fourth transistor M4 is mirrored to the eighth transistor M8, thus obtaining the bias current Ibias.

[0080] Figure 9 A timing diagram of some signals for a DC-DC converter according to an embodiment of the present disclosure is shown. At a first moment T1, the output voltage VOUT drops to Vea, therefore the pulse width modulation signal PWM toggles high. The logic and drive circuit 240 controls the upper transistor drive signal DR_Q1 to toggle low, the upper transistor Q1 turns on, and the inductor current IL increases. The zero-crossing indicator signal ZCD toggles low, therefore the sleep indicator signal SLP toggle high.

[0081] Since the first voltage comparator CMP1 is a hysteresis comparator, when the output voltage VOUT is higher than Vea by a preset value at the second time T2, the pulse width modulation signal PWM flips to a low level.

[0082] At the third moment T3, the inductor current IL rises to the peak current. The logic and drive circuit 240 controls the upper transistor drive signal DR_Q1 and the lower transistor drive signal DR_Q2 to flip to a high level. The upper transistor Q1 is turned off and the lower transistor Q2 is turned on, and the inductor current IL begins to decrease.

[0083] At time T4, the inductor current IL drops to zero, the zero-crossing indicator signal ZCD flips to high, and therefore the sleep indicator signal SLP flips to low. The logic and drive circuit 240 controls the lower transistor drive signal DR_Q2 to flip to low, both the upper transistor Q1 and the lower transistor Q2 are turned off, and the inductor current IL remains zero.

[0084] From time T4 (the fourth time period) through the first time interval to time T5 (the fifth time period), the ramp signal rises to a high level. The sleep indicator signal SLP toggles to a high level. During the second time interval (from time T5 to time T6), when the sleep indicator signal SLP is high, the second transistor M2 is turned on, the ramp signal is reset to zero volts, and the sleep indicator signal SLP toggles to a low level.

[0085] In this way, the DC-DC converter is woken up after the first time period during its sleep phase to refresh Vref1 and Vea, and then enters the sleep phase again when the wake-up time reaches the second time period. Disabling the voltage conversion circuit during the sleep phase reduces the DC-DC converter's quiescent current. Furthermore, timed wake-up of the DC-DC converter can prevent component leakage from causing unstable output voltage VOUT.

[0086] Embodiments of this disclosure also provide a chip. This chip includes a DC-DC converter according to embodiments of this disclosure. This chip is, for example, a power management chip.

[0087] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer or smartphone.

[0088] In summary, the DC-DC converter according to embodiments of this disclosure can reduce quiescent current, thereby reducing power consumption. The DC-DC converter according to embodiments of this disclosure can also be periodically woken up to prevent output voltage VOUT instability caused by component leakage.

[0089] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0090] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0091] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A DC-DC converter, comprising: Voltage conversion circuit, switching circuit, voltage holding circuit, first voltage comparator, second voltage comparator, zero-crossing detection circuit, logic and drive circuit, power transistor, freewheeling transistor, and inductor. The voltage conversion circuit is configured to: convert a first reference voltage into a second reference voltage during the non-sleep period of the DC-DC converter; and to stop operating during the sleep period of the DC-DC converter. The switching circuit is configured to: during the non-sleep period of the DC-DC converter, connect the output of the voltage conversion circuit to the first input of the first voltage comparator via a first node, thereby providing the second reference voltage to the first input of the first voltage comparator; and during the sleep period of the DC-DC converter, disconnect the voltage conversion circuit from the first input of the first voltage comparator. The voltage holding circuit is configured to maintain the voltage at the first input terminal of the first voltage comparator. The second input terminal of the first voltage comparator is coupled to the output terminal of the DC-DC converter, and a pulse width modulation signal is output from the output terminal of the first voltage comparator. The second voltage comparator is configured to output an inductor current peak indication signal at an effective level when the inductor current flowing through the inductor reaches a peak current threshold. The zero-crossing detection circuit is configured to output a zero-crossing indication signal at an effective level when the inductor current is zero. The logic and driving circuit are configured to: control the power transistor to turn on and the freewheeling transistor to turn off when the pulse width modulation signal is at an active level; control the power transistor to turn off and the freewheeling transistor to turn on when the inductor current peak indication signal is at an active level; and control both the power transistor and the freewheeling transistor to turn off when the zero-crossing indication signal is at an active level.

2. The DC-DC converter according to claim 1, wherein, The voltage conversion circuit includes: a reference voltage circuit, a first voltage-controlled switch, a first capacitor, an error amplifier, a first transistor, a first feedback resistor, and a second feedback resistor. The reference voltage circuit is configured to generate the first reference voltage; The first terminal of the first voltage-controlled switch is coupled to the output terminal of the reference voltage circuit, and the second terminal of the first voltage-controlled switch is coupled to the first input terminal of the error amplifier. The first voltage-controlled switch is configured to close during the non-sleep period of the DC-DC converter and to open during the sleep period of the DC-DC converter. The second input terminal of the error amplifier is coupled to the first terminal of the first feedback resistor and the first terminal of the second feedback resistor, the output terminal of the error amplifier is coupled to the control terminal of the first transistor, and the error amplifier stops working during the sleep period of the DC-DC converter. The first terminal of the first capacitor is coupled to the first input terminal of the error amplifier, and the second terminal of the first capacitor is coupled to the second voltage terminal. The first terminal of the first transistor is coupled to the second terminal of the first feedback resistor and the first node, and the second terminal of the first transistor is coupled to the first voltage terminal. The second terminal of the second feedback resistor is coupled to the second voltage terminal.

3. The DC-DC converter according to claim 1, wherein, The switching circuit includes: a second voltage-controlled switch, Wherein, the first terminal of the second voltage-controlled switch is coupled to the first node, the second terminal of the second voltage-controlled switch is coupled to the first input terminal of the first voltage comparator, and the second voltage-controlled switch is configured to close during the non-sleep period of the DC-DC converter and to open during the sleep period of the DC-DC converter.

4. The DC-DC converter according to claim 1, wherein, The voltage holding circuit includes: a second capacitor, Wherein, the first end of the second capacitor is coupled to the first input terminal of the first voltage comparator, and the second end of the second capacitor is coupled to the second voltage terminal.

5. The DC-DC converter according to any one of claims 1 to 4, wherein, The DC-DC converter also includes a sleep control circuit. The sleep control circuit is configured to: generate a sleep indicator signal based on the zero-crossing indicator signal; wherein, when the zero-crossing indicator signal is at an invalid level, the sleep indicator signal is at an invalid level; when the zero-crossing indicator signal flips to an valid level, the sleep indicator signal flips to an valid level; after a first time period following the start of the sleep indicator signal flipping to an valid level, the sleep indicator signal flips to an invalid level and remains at an invalid level for a second time period before flipping to an valid level.

6. The DC-DC converter according to claim 5, wherein, The sleep control circuit includes: a ramp signal generation circuit, a timer reset circuit, and a sleep signal output circuit. The ramp signal generating circuit is configured to generate a ramp signal and provide the ramp signal to the sleep signal output circuit via a second node, wherein the ramp signal rises to an effective level when the rise time of the ramp signal reaches the first time period. The timed reset circuit is configured to reset the ramp signal when the time for the sleep indicator signal to flip to an invalid level reaches the second time period. The sleep signal output circuit is configured such that: when the zero-crossing indicator signal is at an invalid level or the ramp signal is at an active level, the sleep indicator signal is at an invalid level; otherwise, the sleep indicator signal is at an active level.

7. The DC-DC converter according to claim 6, wherein, The ramp signal generation circuit includes: a bias current source and a third capacitor. The bias current source is configured to provide bias current to the first terminal of the third capacitor. The first end of the third capacitor is coupled to the second node, and the second end of the third capacitor is coupled to the second voltage terminal.

8. The DC-DC converter according to claim 6, wherein, The timing reset circuit includes: a first unidirectional delay circuit and a second transistor. The first unidirectional delay circuit is configured to control the second transistor to turn on when the time for the sleep indicator signal to flip to an invalid level reaches the second time period. The first terminal of the second transistor is coupled to the second voltage terminal, and the second terminal of the second transistor is coupled to the second node.

9. The DC-DC converter according to claim 5, wherein, The sleep control circuit includes: a bias current source, a third capacitor, a first inverter, a second inverter, a third inverter, a first unidirectional delay circuit, a second unidirectional delay circuit, a second transistor, a third transistor, and an OR gate. The bias current source is configured to provide bias current to the first terminal of the third capacitor. The first terminal of the third capacitor is coupled to the input terminal of the second inverter, the second terminal of the second transistor, and the second terminal of the third transistor; the second terminal of the third capacitor is coupled to the second voltage terminal. The control terminal of the third transistor is coupled to the output terminal and the input terminal of the second inverter, and the first terminal of the third transistor is coupled to the first voltage terminal. The output of the third inverter is coupled to the first input of the OR gate; The first unidirectional delay circuit is configured to control the second transistor to turn on when the time for the sleep indicator signal to flip to an invalid level reaches a second time period; The first terminal of the second transistor is coupled to the second voltage terminal; The second unidirectional delay circuit is configured to output a delayed zero-crossing indication signal when the time for the zero-crossing indication signal to flip to an effective level reaches a third time interval; The input terminal of the first inverter is coupled to the output terminal of the second unidirectional delay circuit, and the output terminal of the first inverter is coupled to the second input terminal of the OR gate. The sleep indication signal is output from the output of the OR gate.

10. A DC-DC converter, comprising: The circuit includes a reference voltage circuit, a first voltage-controlled switch, a first capacitor, an error amplifier, a first transistor, a first feedback resistor, a second feedback resistor, a second voltage-controlled switch, a second capacitor, a first voltage comparator, a second voltage comparator, a zero-crossing detection circuit, logic and drive circuits, a power transistor, a freewheeling transistor, and an inductor. The reference voltage circuit is configured to generate a first reference voltage. The controlled terminal of the first voltage-controlled switch is provided with a sleep indication signal. The first terminal of the first voltage-controlled switch is coupled to the output terminal of the reference voltage circuit, and the second terminal of the first voltage-controlled switch is coupled to the first input terminal of the error amplifier. The sleep indication signal is at an invalid level during the non-sleep period of the DC-DC converter and at an active level during the sleep period of the DC-DC converter. The second input terminal of the error amplifier is coupled to the first terminal of the first feedback resistor and the first terminal of the second feedback resistor, the output terminal of the error amplifier is coupled to the control terminal of the first transistor, and the error amplifier stops working during the sleep period of the DC-DC converter. The first terminal of the first capacitor is coupled to the first input terminal of the error amplifier, and the second terminal of the first capacitor is coupled to the second voltage terminal. The first terminal of the first transistor is coupled to the second terminal of the first feedback resistor and the first terminal of the second voltage-controlled switch, and the second terminal of the first transistor is coupled to the first voltage terminal. The second terminal of the second feedback resistor is coupled to the second voltage terminal; The controlled terminal of the second voltage-controlled switch is provided with the sleep indication signal, and the second terminal of the second voltage-controlled switch is coupled to the first input terminal of the first voltage comparator; The first terminal of the second capacitor is coupled to the first input terminal of the first voltage comparator, and the second terminal of the second capacitor is coupled to the second voltage terminal; The second input terminal of the first voltage comparator is coupled to the output terminal of the DC-DC converter, and a pulse width modulation signal is output from the output terminal of the first voltage comparator. The second voltage comparator is configured to output an inductor current peak indication signal at an effective level when the inductor current flowing through the inductor reaches a peak current threshold. The zero-crossing detection circuit is configured to output a zero-crossing indication signal at an effective level when the inductor current is zero. The logic and driving circuit are configured to: control the power transistor to turn on and the freewheeling transistor to turn off when the pulse width modulation signal is at an active level; control the power transistor to turn off and the freewheeling transistor to turn on when the inductor current peak indication signal is at an active level; and control both the power transistor and the freewheeling transistor to turn off when the zero-crossing indication signal is at an active level.

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