Memory sectors with trimmed reference current and methods of improving memory read margins thereof

Abstract

A memory sector with trimmed reference current includes eight even column word line cells and eight odd column word line cells, each having an erased state and a written state. The logical state of the odd column word line cells is determined based on a first reference current determined from the cell current of the eight even column word line cells in the written state and the cell current of the eight odd column word line cells in the erased state. The logical state of the even column word line cells is determined based on a second reference current determined from the cell current of the eight even column word line cells in the erased state and the cell current of the eight odd column word line cells in the written state.

Description

Technical Field

[0001] The present invention is generally related to a memory sector and a method for improving its read margin, and more specifically, to a memory sector having a trimmed reference current and a method for improving its memory read margin. Background Technology

[0002] Flash memory uses trimming to determine a reference current to ensure that the memory cells reach the expected current level during programming and erasure. Sensing circuits are used to monitor the logic state of these memory cells, and the current level of the memory cells is accurately sensed and determined during the reading process.

[0003] However, if the uniformity of the memory is not well controlled during manufacturing, it can cause inherent variations in the reference current. For example, excessive misalignment between the contacts and the connected polysilicon active regions can lead to performance differences between cells on two adjacent word lines, resulting in severely uneven measured cell currents and significant parity differences between adjacent word lines. Generally, this problem can be solved by tightening the misalignment specification between the contacts and the active regions, but this is sometimes challenging due to various uncontrollable factors and process limitations during manufacturing. Therefore, those skilled in the art need to research and develop new memory structures and read determination methods to address the problem of uneven properties between memory cells. Summary of the Invention

[0004] To address the issue of uneven cell properties between odd-numbered and even-numbered word lines in the aforementioned memory, this invention proposes a novel memory sector with a adjusted reference current and a method for improving memory read margin. The key feature is that different reference currents are generated through an adjustment method for the read operations of cells in odd-numbered and even-numbered word lines, thereby resolving the problem of uneven properties.

[0005] One aspect of this invention is to provide a memory sector with a adjusted reference current, comprising 8 cells corresponding to even-numbered column word lines and 8 cells corresponding to odd-numbered column word lines. Each cell has two logic states: an erase state and a write state. The logic state of the cell corresponding to the odd-numbered column word line is determined by a first reference current based on the cell currents of the 8 cells corresponding to the even-numbered column word lines in the write state and the cell currents of the 8 cells corresponding to the odd-numbered column word lines in the erase state. The logic state of the cell corresponding to the even-numbered column word line is determined by a second reference current based on the cell currents of the 8 cells corresponding to the even-numbered column word lines in the erase state and the cell currents of the 8 cells corresponding to the odd-numbered column word lines in the write state.

[0006] Another aspect of the present invention is to propose a method for adjusting a reference current to improve memory read margin, the steps of which include providing a memory sector containing 8 cells corresponding to even-numbered column word lines and 8 cells corresponding to odd-numbered column word lines, each cell having two logic states: an erase state and a write state; defining a first reference current based on the cell current of the 8 cells corresponding to even-numbered column word lines in the write state and the cell current of the 8 cells corresponding to odd-numbered column word lines in the erase state, the first reference current being used to determine the logic state of the cell corresponding to the odd-numbered column word line; and defining a second reference current based on the cell current of the 8 cells corresponding to even-numbered column word lines in the erase state and the cell current of the 8 cells corresponding to odd-numbered column word lines in the write state, the second reference current being used to determine the logic state of the cell corresponding to the even-numbered column word line.

[0007] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description

[0008] This specification includes accompanying drawings, which form part of the document, to provide the reader with a further understanding of embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings:

[0009] Figure 1 This is a diagram showing the distribution of cell current in the erasure state between the number of cells with odd-numbered and even-numbered column word lines in the prior art.

[0010] Figure 2 This is a graph showing the distribution of the number of cells with odd-numbered column word lines in the erase state according to a preferred embodiment of the present invention, and...

[0011] Figure 3 This is a graph showing the distribution of cell current based on the number of even-numbered column word lines in the erase state according to a preferred embodiment of the present invention.

[0012] It should be noted that all illustrations in this specification are for illustrative purposes only. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.

[0013] The labels in the diagram are explained as follows:

[0014] 10 Distribution Curve

[0015] 20 Distribution Curve

[0016] 100 memory sectors

[0017] Unit 102

[0018] Unit 104

[0019] 200 memory sectors

[0020] Unit 202

[0021] Unit 204

[0022] 300 memory sectors

[0023] Unit 302

[0024] Unit 304

[0025] d1 constant

[0026] d2 constant

[0027] even WL even column line

[0028] Unit current

[0029] I REF Reference currents I1 and I2

[0030] odd WL (odd column line) Detailed Implementation

[0031] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various non-conflicting features thereof can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0032] Readers can generally understand terms at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a," "an," "the," or "the" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partially on the context.

[0033] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0034] The memory structure and related methods of this invention are primarily applied to embedded flash memory (EFlash) architectures. Flash memory is an integrated circuit capable of storing and, if needed, reading information. It may contain multiple writable cells, each capable of storing one bit or more of data. Taking a cell storing one bit of data as an example, the cell will be in one of two possible critical voltage distributions, namely, one of the two logic states "1" and "0". The following embodiments will focus on a memory structure for reading one bit of data; however, it should be noted that this invention is not limited to one bit of data and can also be used for reading multi-bit data.

[0035] First, please refer to... Figure 1 It is a graph showing the distribution of cell current based on the number of cells with odd-numbered and even-numbered column word lines in the erase state ("1" logic state) in the prior art. Figure 1 The X-axis represents the cell current I, which is the cell current in the erase state. Figure 1 The Y-axis represents the number of cells, specifically the number of cells with a current of I in the entire memory. The normal distribution curves shown in the figure represent the distribution of cell currents measured across all cells in the entire memory. Curve 10 on the right represents the cell number distribution for odd-numbered word lines (odd WL), while curve 20 on the left represents the cell number distribution for even-numbered word lines (even WL). As can be seen from the figure, due to process variability, not all cells have an ideal, uniform cell current; instead, they exhibit a normal distribution. Furthermore, certain processes or memory architectures can easily lead to significant differences in parity between odd and even-numbered word lines. For example, the average cell current of curve 20 for even-numbered word lines is significantly lower than that of curve 10 for odd-numbered word lines. The normal current distribution range of curve 20 on the left is also larger than that of curve 10 on the right, indicating a more uneven distribution among cells corresponding to even-numbered word lines.

[0036] Refer to Figure 1 During flash memory read operations, the reference current I... REFThis will be provided as a reference to determine whether the cell is in an erase state ("1" logic state) or a write state ("0" logic state). In general trimming methods, such as... Figure 1 As shown, it typically defines a memory sector 100 in the main array region. This memory sector 100 corresponds to two adjacent word lines, including an even-numbered word line (even WL) and an odd-numbered word line (odd WL). It contains eight cells 102 corresponding to the even-numbered word line and eight cells 104 corresponding to the odd-numbered word line. Each cell 102, 104 has two logic states: erase (hollow dot) and write (solid dot). A common practice is to randomly program eight cells in the memory sector 100 into the write state and erase the other eight cells into the erase state, then measure the cell current of these cells, where the reference current I... REF It will be set to the average value of the cell current of these 16 cells under this logic state setting.

[0037] Refer to Figure 1 When a cell is read to have a cell current greater than the reference current I. REF It will be determined to be in an erased state, and when the cell is read and its cell current is less than the reference current I, it will be considered to be in an erased state. REF It will be determined to be in the write state. Taking the embodiment in the figure as an example, distribution curve 10 and distribution curve 20 correspond to the actual distribution of cells of odd-numbered and even-numbered word lines in the erase state, respectively. Ideally, distribution curve 10 and distribution curve 20 in the erase state should both be located at the reference voltage I. REF On the right side. However, as can be seen from the figure, due to process variations and differences in word line parity, in reality, part of the distribution curve 20 (the shaded area in the figure) will fall on the reference voltage I. REF On the left, the cells corresponding to the even-numbered column word lines that are in the erase state will be judged as being in the write state, causing read failure.

[0038] To solve this problem, please refer to Figure 2 This is a diagram showing the distribution of the number of cells in the erase state on odd-numbered word lines according to a preferred embodiment of the present invention, in relation to the cell current. In this embodiment, a memory sector 200 is also provided, corresponding to two adjacent word lines, including an even-numbered word line (even WL) and an odd-numbered word line (odd WL), and containing eight cells 202 corresponding to the even-numbered word line and eight cells 204 corresponding to the odd-numbered word line. Each cell 202, 204 has two logic states: erase state (hollow dot) and write state (solid dot). Unlike the prior art, the cells in the memory sector 200 of the present invention, where the reference current is taken, are not randomly configured into eight write states and eight erase states. Figure 2 As shown, when defining the reference current I1 for the cells corresponding to the odd-numbered word lines, the eight cells in memory sector 200 corresponding to the even-numbered word lines (even WL) are programmed into a write state, and the eight cells corresponding to the odd-numbered word lines (odd WL) are erased into an erase state. The cell currents of these cells are then measured. The reference current I1 for the cells corresponding to the odd-numbered word lines is defined as the average cell current of these 16 cells under this logic state setting. Alternatively, in some embodiments, the reference current I1 for the cells corresponding to the odd-numbered word lines is defined as the average cell current of these 16 cells under this logic state setting minus a predetermined value, which is preferably greater than half the normal current distribution range of the cells corresponding to the odd-numbered word lines, i.e., d1 in the figure.

[0039] Refer to Figure 2 The advantage of the above-described method of the present invention is that, due to process variations and differences in word line parity, the cell current (i.e., distribution curve 10 in the figure) of the cell corresponding to the odd-numbered word lines in the erase state will, on average, exceed the reference current I defined by the conventional method. REF Many. Therefore, in the present invention, all eight cells in the erase state correspond to an odd number of column word lines rather than being randomly sampled, and the calculated reference current I1 will be different from the originally defined reference current I. REF A larger current, which more closely reflects the actual behavior of cells corresponding to odd-numbered column word lines, is more suitable as a reference voltage for determining the logic state of cells corresponding to odd-numbered column word lines. Thus, during a read operation, when the cell current read for the cell corresponding to the odd-numbered column word line is greater than the reference current I1, the cell is determined to be in the erase state, and when the cell current read for the cell corresponding to the odd-numbered column word line is less than the reference current I1, the cell is determined to be in the write state.

[0040] Please refer to now. Figure 3 This is a diagram showing the distribution of the number of cells in the erase state relative to the cell current in a preferred embodiment of the present invention. In this embodiment, a memory sector 300 is also provided, corresponding to two adjacent word lines, including an even-numbered word line (even WL) and an odd-numbered word line (odd WL), and containing eight cells 302 corresponding to the even-numbered word line and eight cells 304 corresponding to the odd-numbered word line. Each cell 302, 304 has two logic states: an erase state (hollow dot) and a write state (solid dot). Unlike the prior art, the cells in the memory sector 300 of the present invention, where the reference current is taken, are not randomly configured into eight write states and eight erase states. Figure 3As shown, when defining the reference current I2 for the cell corresponding to the even-numbered word line, the eight cells in memory sector 300 corresponding to the odd-numbered word line (odd WL) are programmed into a write state, and the eight cells corresponding to the even-numbered word line (even WL) are erased into an erase state. The cell current of these cells is then measured. The reference current I2 for the even-numbered word line cells is defined as the average cell current of these 16 cells under this logic state setting. Alternatively, in some embodiments, the reference current I2 for the even-numbered word line cells is defined as the average cell current of these 16 cells under this logic state setting minus a predetermined value. This predetermined value is preferably greater than half the normal current distribution range of the cell corresponding to the even-numbered word line, i.e., d2 in the figure.

[0041] Refer to Figure 3 The advantage of the above-described method of the present invention is that, due to process variations and differences in word line parity, the cell current (i.e., the distribution curve 20 in the figure) of the cells corresponding to even-numbered word lines in the erase state is, on average, very close to the reference current I defined by conventional methods. REF Thus, the portion located on the left edge of distribution curve 20 easily falls into the original reference current I. REF The range on the left causes read failure. Therefore, in the present invention, all 8 cells in the erase state correspond to even-numbered column word lines instead of random sampling, and the calculated reference current I2 will be different from the originally defined reference current I. REF A smaller voltage, which more closely reflects the actual behavior of cells corresponding to even-numbered column word lines, is more suitable as a reference voltage for determining the logic state of cells corresponding to even-numbered column word lines. Thus, during a read operation, when the cell current read for the cell corresponding to the even-numbered column word line is greater than the reference current I2, the cell is determined to be in the erase state; and when the cell current read for the cell corresponding to the even-numbered column word line is less than the reference current I2, the cell is determined to be in the write state.

[0042] Based on the above embodiments, the key point of the present invention is to generate different reference currents through a trimming method for reading and determining the units of odd-numbered and even-numbered column word lines, thereby solving the problem of reading errors caused by uneven current performance.

[0043] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. A memory sector having a trimmed reference current, comprising 8 cells corresponding to even-numbered column word lines and 8 cells corresponding to odd-numbered column word lines, each cell having two logic states: an erase state and a write state. The logic state of the cell corresponding to the odd-numbered column word line is determined by a first reference current based on the cell currents of the 8 cells corresponding to the even-numbered column word lines in the write state and the cell currents of the 8 cells corresponding to the odd-numbered column word lines in the erase state. The logic state of the cell corresponding to the even-numbered column word line is determined by a second reference current based on the cell currents of the 8 cells corresponding to the even-numbered column word lines in the erase state and the cell currents of the 8 cells corresponding to the odd-numbered column word lines in the write state.

2. The memory sector with a trimmed reference current as described in claim 1, wherein the first reference current is a first average cell current obtained by averaging the cell currents of the eight cells corresponding to even-numbered column word lines in the write state and the cell currents of the eight cells corresponding to odd-numbered column word lines in the erase state.

3. The memory sector with a trimmed reference current as described in claim 1, wherein the first reference current is the average of the cell currents of the eight cells corresponding to even-numbered column word lines in the write state and the cell currents of the eight cells corresponding to odd-numbered column word lines in the erase state, minus a fixed value.

4. The memory sector with a adjusted reference current as described in claim 3, wherein the set value is greater than half of the normal current distribution range of the cell corresponding to the odd-numbered column word line.

5. The memory sector with a trimmed reference current as described in claim 1, wherein the second reference current is a second average cell current obtained by averaging the cell currents of the eight cells corresponding to even-numbered column word lines in the erase state and the cell currents of the eight cells corresponding to odd-numbered column word lines in the write state.

6. The memory sector with a trimmed reference current as described in claim 1, wherein the second reference current is the average of the cell currents of the eight cells corresponding to even-numbered column word lines in the erase state and the cell currents of the eight cells corresponding to odd-numbered column word lines in the write state, minus a fixed value.

7. The memory sector with a adjusted reference current as claimed in claim 6, wherein the set value is greater than half of the normal current distribution range of the cell corresponding to the even-numbered column word line.

8. The memory sector with a trimmed reference current as claimed in claim 1, wherein when the cell current corresponding to the cell of the odd-numbered column word line is greater than the first reference current, the cell is determined to be in the erase state, and when the cell current corresponding to the cell of the odd-numbered column word line is less than the first reference current, the cell is determined to be in the write state.

9. The memory sector with a trimmed reference current as claimed in claim 1, wherein when the cell current of the cell corresponding to the even-numbered column word line is greater than the second reference current, the cell is determined to be in the erase state, and when the cell current of the cell corresponding to the even-numbered column word line is less than the second reference current, the cell is determined to be in the write state.

10. A method for adjusting a reference current to improve memory read margin, comprising: Provide memory sectors, which contain 8 cells corresponding to even-numbered word lines and 8 cells corresponding to odd-numbered word lines. Each cell has two logical states: erase and write. A first reference current is defined based on the cell currents of the 8 cells corresponding to even-numbered column word lines in the write state and the cell currents of the 8 cells corresponding to odd-numbered column word lines in the erase state. This first reference current is used to determine the logic state of the cell corresponding to the odd-numbered column word line. A second reference current is defined based on the cell currents of the 8 cells corresponding to even-numbered column word lines in the erase state and the cell currents of the 8 cells corresponding to odd-numbered column word lines in the write state. The second reference current is used to determine the logic state of the cell corresponding to the even-numbered column word line.

11. The method of adjusting a reference current to improve memory read margin as described in claim 10, wherein the step of defining the first reference current includes: The first average cell current is obtained by averaging the cell currents of the 8 cells corresponding to the even-numbered column word lines in the write state and the cell currents of the 8 cells corresponding to the odd-numbered column word lines in the erase state. as well as The first reference current is defined as the first average cell current.

12. The method of adjusting a reference current to improve memory read margin as described in claim 10, wherein the step of defining the first reference current includes: The first average cell current is obtained by averaging the cell currents of the 8 cells corresponding to the even-numbered column word lines in the write state and the cell currents of the 8 cells corresponding to the odd-numbered column word lines in the erase state. as well as The first reference current is defined as the first average unit current minus a fixed value.

13. The method of adjusting the reference current to improve memory read margin as described in claim 12, wherein the set value is greater than half of the normal current distribution range of the cell corresponding to the odd-numbered column word line.

14. The method of adjusting a reference current to improve memory read margin as described in claim 10, wherein the step of defining the second reference current includes: The second average cell current is obtained by averaging the cell currents of the 8 cells corresponding to even-numbered column word lines in the erase state and the cell currents of the 8 cells corresponding to odd-numbered column word lines in the write state. as well as The second reference current is defined as the second average unit current.

15. The method of adjusting a reference current to improve memory read margin as described in claim 10, wherein the step of defining the second reference current includes: The second average cell current is obtained by averaging the cell currents of the 8 cells corresponding to even-numbered column word lines in the erase state and the cell currents of the 8 cells corresponding to odd-numbered column word lines in the write state. as well as The second reference current is defined as the second average unit current minus a fixed value.

16. The method of adjusting the reference current to improve memory read margin as described in claim 15, wherein the set value is greater than half of the normal current distribution range of the cell corresponding to the even-numbered column word line.

17. The method for adjusting the reference current to improve memory read margin as described in claim 10, further comprising: Read the cell current of these cells; When the cell current corresponding to the odd-numbered column word line is greater than the first reference current, the cell is determined to be in the erase state. as well as When the cell current corresponding to the odd-numbered column word line is less than the first reference current, the cell is determined to be in the write state.

18. The method for adjusting the reference current to improve memory read margin as described in claim 10, further comprising: Read the cell current of these cells; When the cell current of the cell corresponding to the even-numbered column word line is greater than the second reference current, the cell is determined to be in the erase state. as well as When the cell current corresponding to the even-numbered column word line is less than the second reference current, the cell is determined to be in the write state.

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