A current reference circuit

Abstract

This application provides a current reference circuit, including a current reference core module, a first switch, and a startup module. The current reference core module outputs a reference current. The first switch is connected to the current reference core module. The startup module is connected to the first switch and, during power-on, controls the first switch to connect to the current reference core module, transmitting a startup current to the current reference core module via the first switch to start the current reference core module. After transmitting the startup current to the current reference core module, the startup module controls the first switch to disconnect. By controlling the first switch to disconnect after transmitting the startup current to the current reference core module, the problem of no startup current being transmitted to the current reference core module due to the first switch not conducting or insufficient conducting during slow power-on is avoided, thus improving the reliability of the current reference circuit during power-on startup.

Description

Technical Field

[0001] This application relates to the field of reference circuit technology, and in particular to a current reference circuit. Background Technology

[0002] In integrated circuit chip design, bandgap reference circuits provide low-temperature drift voltage and current references for various circuit modules inside the chip. However, bandgap reference circuits often have two operating points: a reasonable operating point required for normal circuit operation and a "0" operating point. Therefore, bandgap reference circuits generally require a startup circuit to help complete the normal startup process, move away from the "0" operating point, and make the circuit work at the only stable static operating point. Existing startup circuits often fail to start normally during the slow power-on process, thus preventing the bandgap reference circuit from working properly. Summary of the Invention

[0003] This application provides a current reference circuit to solve some of the problems in related technologies.

[0004] The current reference circuit provided in this application includes:

[0005] The current reference core module is used to output a reference current;

[0006] The first switch is a PMOS transistor and is connected to the current reference core module.

[0007] A startup module, connected to the first switch, is used to control the first switch to connect with the current reference core module during the power-on process at the power supply end, transmit a startup current to the current reference core module through the first switch to start the current reference core module, and control the first switch to disconnect after completing the transmission of startup current to the current reference core module.

[0008] Optionally, the current reference core module includes a first PMOS transistor; the first PMOS transistor is connected between the first switch and the power supply terminal, the first switch is connected between the first PMOS transistor and the ground terminal, and the gate and drain of the first PMOS transistor are connected.

[0009] The startup module includes a second PMOS transistor, a first node, a second node, and a capacitor. The first node is connected between the first switch and the first PMOS transistor. The source of the second PMOS transistor is connected to the power supply terminal, and the drain of the second PMOS transistor is grounded through the capacitor. The second node is connected between the second PMOS transistor and the capacitor. The gate of the second PMOS transistor is connected to the first node, the gate of the first switch is connected to the second node, and the source of the first switch is connected to the first node.

[0010] Optionally, a resistive element is connected between the first switch and the grounding terminal.

[0011] Optionally, the resistive element is a first NMOS transistor, the gate of the first NMOS transistor is connected to a voltage source or an enable terminal, the source of the first NMOS transistor is connected to the ground terminal, and the drain of the first NMOS transistor is connected to the first switch.

[0012] Optionally, a current-limiting resistive device is connected between the second PMOS transistor and the ground terminal.

[0013] Optionally, the current-limiting resistive device is a second NMOS transistor, the gate of which is connected to the upper plate of the capacitor, the source of which is connected to the ground terminal, and the drain of which is connected to the second node.

[0014] Optionally, the gates of the first PMOS transistor and the second PMOS transistor are connected, and the first PMOS transistor and the second PMOS transistor form a current mirror; the startup module is used to control the first switch to connect with the current reference core module when the power supply is powered on, inject startup current into the current reference core module through the first switch, and control the first switch to disconnect after completing the transmission of startup current to the current reference core module.

[0015] Optionally, the current reference core module includes a first branch current generation module, a second branch current generation module, and a current synthesis module. The first branch current generation module includes a first adjustable resistor. The first branch current generation module is used to generate a first branch current, which is a current proportional to temperature.

[0016] The second branch current generating module includes a second adjustable resistor. The second branch current generating module is used to generate a second branch current, which is a current that is inversely proportional to temperature.

[0017] The current synthesis module is connected to the first branch current generation module and the second branch current generation module respectively, and is used to generate a reference current based on the first branch current and the second branch current.

[0018] Optionally, the first branch current generating module further includes a first PMOS transistor, a third NMOS transistor, a first transistor, a third PMOS transistor, a fourth NMOS transistor, and a second transistor. The sources of the first PMOS transistor and the third PMOS transistor are both connected to the power supply terminal. The gates of the first PMOS transistor and the third PMOS transistor are connected. The drain of the first PMOS transistor is connected to the drain of the third NMOS transistor. The drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the fourth NMOS transistor and the gate of the fourth NMOS transistor are connected. The gate of the third NMOS transistor and the gate of the fourth NMOS transistor are connected. The source of the third NMOS transistor is connected to the collector of the first transistor. The first adjustable resistor is connected between the emitter of the first transistor and the ground terminal. The source of the fourth NMOS transistor is connected to the collector of the second transistor. The emitter of the second transistor is connected to the ground terminal. The base of the first transistor and the base of the second transistor are connected.

[0019] Optionally, the second branch current generating module further includes a fourth PMOS transistor, a fifth NMOS transistor, and a second transistor. The source of the fourth PMOS transistor is connected to the power supply terminal, the gate and drain of the fourth PMOS transistor are connected, the drain of the fourth PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the gate of the fourth NMOS transistor, the source of the fifth NMOS transistor is connected to the base of the second transistor, and the second adjustable resistor is connected between the source of the fifth NMOS transistor and the ground terminal.

[0020] Optionally, the current synthesis module includes a fifth PMOS transistor and a sixth PMOS transistor. The sources of the fifth PMOS transistor and the sixth PMOS transistor are both connected to the power supply terminal. The gate of the fifth PMOS transistor is connected to the gate of the first PMOS transistor. The gate of the sixth PMOS transistor is connected to the gate of the fourth PMOS transistor. The drains of the fifth PMOS transistor and the drain of the sixth PMOS transistor are connected to each other for outputting the reference current.

[0021] Optionally, the first adjustable resistor includes a first resistor and a plurality of first optional resistors connected in series with the first resistor, and each of the first optional resistors is connected in parallel with a first control switch;

[0022] The second adjustable resistor includes a second resistor and a plurality of second optional resistors connected in series with the second resistor, and each of the second optional resistors is connected in parallel with a second control switch.

[0023] Optionally, the second branch current generation module of the current reference module is equipped with a transmission gate switch. The current reference circuit provided in this application includes a current reference core module, a first switch, and a startup module. The current reference core module outputs a reference current. The first switch is a PMOS transistor connected to the current reference core module. The startup module is connected to the first switch and is used to control the first switch to connect to the current reference core module during power-on, transmitting a startup current to the current reference core module through the first switch to start the current reference core module. After transmitting the startup current to the current reference core module, the startup module controls the first switch to disconnect. By controlling the first switch to disconnect after transmitting the startup current to the current reference core module, it is ensured that a startup current is transmitted to the current reference core module. This avoids the problem that the first switch may not be conducting or may not be conducting sufficiently during slow power-on, resulting in no startup current being transmitted to the current reference core module and causing the current reference circuit to fail to start normally. This improves the reliability of the current reference circuit during power-on startup. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0025] Figure 1 This is a schematic block diagram of a current reference circuit according to one embodiment of this application;

[0026] Figure 2 This is a circuit diagram of a current reference circuit according to one embodiment of this application;

[0027] Figure 3 This is a circuit diagram of a current reference circuit shown in another embodiment of this application;

[0028] Figure 4 The circuit diagram shows a current reference circuit in another embodiment of this application.

[0029] Reference numerals in the figures: Current reference circuit 1, Start-up module 10, Current reference core module 20, First switch 11, First PMOS transistor 12, Second PMOS transistor 13, First node A, Second node B, Capacitor 14, First NMOS transistor 15, Second NMOS transistor 16, First branch current generation module 21, Second branch current generation module 22, Current synthesis module 23, Third NMOS transistor 211, First transistor 212, First adjustable resistor 213, Fourth NMOS transistor 214, Third PMOS transistor 215, Second transistor 223, Second adjustable resistor 224, Fifth NMOS transistor 221, Fourth PMOS transistor 222, Fifth PMOS transistor 231, Sixth PMOS transistor 232, First resistor 2131, First optional resistor 2132, First control switch 2133, Second resistor 2241, Second optional resistor 2242, Second control switch 2243, Transmission gate switch 25, Power supply terminal VDD, Ground terminal GND. Detailed Implementation

[0030] This application provides a current reference circuit. The current reference circuit of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0031] Please refer to Figure 1 , Figure 1 This is a schematic block diagram of a current reference circuit 1 according to one embodiment of this application. Figure 1 In the illustrated embodiment, the current reference circuit 1 includes a current reference core module 20, a first switch 11, and a startup module 10. The current reference core module 20 is used to output a reference current.

[0032] The current reference core module 20 typically has two operating points: a reasonable operating point required for normal circuit operation and a "0" operating point. Therefore, the current reference core module 20 generally requires the startup module 10 to generate a startup current to help complete the normal startup process, move away from the "0" operating point, and enable the circuit to operate at the unique and stable static operating point. After the current reference core module 20 moves away from the "0" operating point and operates at the unique and stable static operating point, the startup module 10 needs to be turned off to reduce the power consumption of the current reference circuit 1.

[0033] like Figure 1As shown, the startup module 10 is connected to the first switch 11. During the power-on process at the power supply terminal VDD, it controls the first switch 11 to connect with the current reference core module 20, transmitting a startup current to the current reference core module 20 to start it up. After transmitting the startup current to the current reference core module 20, it controls the first switch 11 to disconnect. By controlling the first switch to disconnect after transmitting the startup current to the current reference core module, it ensures that a startup current is transmitted to the current reference core module. This avoids the problem of no startup current being transmitted to the current reference core module due to the first switch not conducting or insufficient conducting during the slow power-on process, which would prevent the current reference circuit from starting normally. This improves the reliability of the current reference circuit startup during power-on.

[0034] Please refer to Figure 2 , Figure 2 This is a circuit diagram of a current reference circuit 1 according to one embodiment of this application. Figure 2 In the illustrated embodiment, the current reference core module 20 includes a first PMOS transistor 12, which is connected between a first switch 11 and a power supply terminal VDD. The first switch 11 is connected between the first PMOS transistor 12 and a ground terminal GND. The gate and drain of the first PMOS transistor 12 are connected. The startup module 10 includes a second PMOS transistor 13, a first node A, a second node B, and a capacitor 14. The first node A is connected between the first switch 11 and the first PMOS transistor 12. The source of the second PMOS transistor 13 is connected to the power supply terminal VDD, and the drain of the second PMOS transistor 13 is grounded through the capacitor 14. The second node B is connected between the second PMOS transistor 13 and the capacitor 14. The gate of the second PMOS transistor 13 is connected to the first node A, the gate of the first switch 11 is connected to the second node B, and the source of the first switch 11 is connected to the first node A.

[0035] In the circuit structure provided by the embodiments of this application, the first node A and the second node B do not represent actual existing components, but rather represent the junction points where related components in the circuit diagram are connected. In other words, these nodes are equivalent to the junction points where related components in the circuit diagram are connected.

[0036] The startup module 10 controls the first switch 11 to turn on during the power-on process at the power supply terminal VDD. Specifically, because the gate and drain of the first PMOS transistor 12 are connected in a diode configuration, when the first switch 11 is not turned on during the power-on process at the power supply terminal VDD, the potential of the gate and drain of the first PMOS transistor 12, i.e., the potential of the first node A, follows the voltage of the power supply terminal VDD. As the voltage of the power supply terminal VDD increases, the potential of the first node A also increases. The source of the second PMOS transistor 13 is connected to the power supply terminal VDD, and the gate of the second PMOS transistor 13 is connected to the first node A. Since the potential of the first node A follows the potential of the power supply terminal VDD, the second PMOS transistor 13 is in the off state at this time. When the second node B is at a low potential and the absolute value of the voltage difference between the first node A and the second node B is greater than the absolute value of the threshold voltage of the first switch 11, the first switch 11 turns on.

[0037] After the first switch 11 is turned on, a path is formed between the power supply terminal VDD, the first PMOS transistor 12, the first switch 11, and the ground terminal GND, forming a startup current. The startup current is injected into the current reference core module 20 through the first switch 11, causing the current reference core module 20 to start.

[0038] The first switch 11 is connected between the first PMOS transistor 12 and the ground terminal GND. The first PMOS transistor 12 is connected in a diode configuration. After the first switch 11 is turned on, the potential of the first node A will automatically correct and decrease. The conduction of the first switch 11 lowers the potential of the first node A, thus turning on the second PMOS transistor 13. Specifically, because the gate of the second PMOS transistor 13 is connected to the first node A and the source of the second PMOS transistor 13 is connected to the power supply terminal VDD, the absolute value of the voltage difference between the gate and source of the second PMOS transistor 13 is greater than the absolute value of the threshold voltage of the second PMOS transistor 13, causing the second PMOS transistor 13 to conduct.

[0039] The power supply VDD charges capacitor 14 through the second PMOS transistor 13, raising the potential of the second node B. When the potential of the second node B rises to the point where the absolute value of the voltage difference between the second node B and the first node A is less than the absolute value of the threshold voltage of the first switch 11, the first switch 11 turns off. Due to the presence of capacitor 14, it takes a certain amount of time for the potential of the second node B to be pulled up; that is, there is a certain time difference between the first switch 11 turning on and off. This ensures that a starting current is transmitted to the current reference core module 20 through the first switch 11 before the first switch 11 turns off, thus controlling the first switch to turn off after transmitting the starting current to the current reference core module. This avoids the problem of the first switch not conducting or conducting sufficiently during the slow power-on process, which could result in no starting current being transmitted to the current reference core module and prevent the current reference circuit from starting normally, thereby improving the reliability of the current reference circuit during power-on startup.

[0040] Please refer to Figure 3 , Figure 3 This is a circuit diagram of a current reference circuit 1 according to another embodiment of this application. Figure 3 In the illustrated embodiment, a resistive element is connected between the first switch 11 and the ground terminal GND to generate a startup current based on the voltage at the power supply terminal VDD. The resistive element can be a resistor. By setting a resistor, a path is formed between the first switch 11 being turned on, the power supply terminal VDD, the first PMOS transistor 12, the first switch 11, and the ground terminal GND, and a startup current is generated in this path. The magnitude of the startup current can be adjusted by changing the resistance value, thereby ensuring that the startup current meets the requirements. The resistance value should not be too large to ensure sufficient driving capability to transmit the startup current and complete the startup process.

[0041] exist Figure 3 In the embodiment shown, the resistive element is a first NMOS transistor 15. The gate of the first NMOS transistor 15 is connected to a voltage source or an enable terminal, the source of the first NMOS transistor 15 is connected to the ground terminal GND, and the drain of the first NMOS transistor 15 is connected to the first switch 11.

[0042] When the gate of the first NMOS transistor 15 is connected to a voltage source, it is off when the power supply terminal VDD is not powered on. As the power supply terminal VDD is powered on, the gate potential of the first NMOS transistor 15 increases, causing it to turn on. After the first NMOS transistor 15 turns on, it has an on-resistance. This on-resistance allows a path to be formed between the first switch 11, the first NMOS transistor 15, the power supply terminal VDD, the first PMOS transistor 12, the first switch 11, and the ground terminal GND. A startup current is generated in this path. The magnitude of the startup current can be adjusted by adjusting the on-resistance of the first NMOS transistor 15, thus ensuring that the startup current meets the requirements. The resistance value should not be too large to ensure sufficient driving capability to transmit the startup current and complete the startup process.

[0043] When the gate of the first NMOS transistor 15 is connected to the enable terminal, a voltage that can turn the first NMOS transistor 15 on or off can be applied to the enable terminal to control its on or off state. When a path needs to be formed between the power supply terminal VDD, the first PMOS transistor 12, the first switch 11, and the ground terminal GND, a high-level signal is applied to the enable terminal to control the first NMOS transistor 15 to turn on. And when the first switch 11 is turned off after transmitting the startup current to the current reference core module 20, a low-level signal is applied to the enable terminal to control the first NMOS transistor 15 to turn off. In this way, when the first switch 11 is turned off after transmitting the startup current to the current reference core module 20, the first NMOS transistor 15 can also be turned off, avoiding incomplete turn-off of the first switch 11 which would generate additional power consumption and increase the energy consumption of the current reference circuit 1, thereby reducing energy consumption.

[0044] Please continue to refer to this. Figure 3 ,exist Figure 3 In the embodiment shown, a current-limiting resistive device is connected between the second PMOS transistor 13 and the ground terminal GND. The current in this path is limited by adjusting the resistance value of the current-limiting resistive device. This can prevent the power consumption of the startup circuit from increasing due to excessive driving of the second PMOS transistor 13, thereby further reducing the power consumption of the startup circuit.

[0045] exist Figure 3 In the embodiment shown, the current-limiting resistive device is a second NMOS transistor 16. The gate of the second NMOS transistor 16 is connected to the upper plate of the capacitor 14, the source of the second NMOS transistor 16 is connected to the ground terminal GND, and the drain of the second NMOS transistor 16 is connected to the second node B.

[0046] After the second PMOS transistor 13 is turned on, the power supply VDD charges capacitor 14 through the second PMOS transistor 13, which increases the potential of the second node B, i.e., the potential of the upper plate of capacitor 14. As the potential of the upper plate of capacitor 14 continues to increase, when the potential difference between the upper plate of capacitor 14 and ground GND exceeds the threshold voltage of the second NMOS transistor 16, the second NMOS transistor 16 is turned on. A path is formed between the power supply VDD, the second PMOS transistor 13, and the second NMOS transistor 16. By adjusting the on-resistance of the second NMOS transistor 16, the current in this path can be limited. This avoids excessive power consumption in the startup circuit due to overly strong drive of the second PMOS transistor 13, thereby further reducing the power consumption of the startup circuit.

[0047] exist Figure 3In the illustrated embodiment, the gates of the first PMOS transistor 12 and the second PMOS transistor 13 are connected, forming a current mirror. After the current reference core module 20 is started, when the reference current is abnormally low (in the tens of nA range), the current of the first PMOS transistor 12 is also abnormally low, and the current mirrored from the first PMOS transistor 12 to the second PMOS transistor 13 is also abnormally low. The startup module 10 controls the first switch 11 to connect with the current reference core module 20, injecting startup current into the current reference core module 20, and after completing the transmission of startup current to the current reference core module, controls the first switch to disconnect.

[0048] Specifically, when the reference current is abnormally low (in the tens of nA range), almost no current flows through the first PMOS transistor 12 and the second PMOS transistor 13. This causes the current in the second PMOS transistor 13 to be less than the current in the second NMOS transistor 16, resulting in a low potential at the second node B. Furthermore, the absolute value of the potential difference between the second node B and the first node A is greater than the absolute value of the threshold voltage of the first switch 11, causing the first switch 11 to conduct. The first switch 11 connects to the current reference core module 20, injecting startup current into the current reference core module 20 and completing the startup of the reference core circuit. At this time, due to the current mirroring of the first and second PMOS transistors, the pull-up of the second PMOS transistor 13 is greater than the pull-down of the second NMOS transistor 16, charging the capacitor 14 and raising the potential of the second node B. When the absolute value of the potential difference between the second node B and the first node A is less than the absolute value of the threshold voltage of the first switch 11, the first switch 11 turns off, reducing the power consumption of the current reference circuit 1.

[0049] When current flows through the current reference core module 20, if the reference current is too large, both the first PMOS transistor 12 and the second PMOS transistor 13 will have current flowing through them. Because of the presence of capacitor 14, the potential of the second node B will not be immediately pulled high by the second PMOS transistor 13. Instead, it will charge capacitor 14. Therefore, the potential of the second node B will gradually increase from low to high. The first switch 11 will then go through a process of turning on and off, meaning that a startup current will be transferred to the current reference core module, completing the normal startup. Afterward, the first switch 11 will turn off. This ensures a stable startup of the current reference core module 20 and improves the reliability of the current reference circuit 1 during startup.

[0050] exist Figure 3In the illustrated embodiment, the current reference core module 20 includes a first branch current generation module 21, a second branch current generation module 22, and a current synthesis module 23. The first branch current generation module 21 includes a first adjustable resistor 213 and is used to generate a first branch current I1, which is a current proportional to temperature. The second branch current generation module 22 includes a second adjustable resistor 224 and is used to generate a first branch current I2, which is a current inversely proportional to temperature. The current synthesis module 23 is connected to both the first branch current generation module 21 and the second branch current generation module 22, and is used to generate a reference current I based on the first branch current I1 and the first branch current I2. ref .

[0051] exist Figure 3 In the embodiment shown, the first branch current generation module 21 further includes a first PMOS transistor 12, a third NMOS transistor 211, a first transistor 212, a third PMOS transistor 215, a fourth NMOS transistor 214, and a second transistor 223. The sources of the first PMOS transistor 12 and the third PMOS transistor 215 are both connected to the power supply terminal VDD. The gates of the first PMOS transistor 12 and the third PMOS transistor 215 are connected. The drain of the first PMOS transistor 12 is connected to the drain of the third NMOS transistor 211. The drain of the third PMOS transistor 215 is connected to the drain of the fourth NMOS transistor 214. The drain and gate of the fourth NMOS transistor 214 are connected. The gate of the third NMOS transistor 211 is connected to the gate of the fourth NMOS transistor 214. The source of the third NMOS transistor 211 is connected to the collector of the first transistor 212. The first adjustable resistor 213 is connected between the emitter of the first transistor 212 and the ground terminal GND. The source of the fourth NMOS transistor 214 is connected to the collector of the second transistor 223. The emitter of the second transistor 223 is connected to the ground terminal GND. The base of the first transistor 212 and the base of the second transistor 223 are connected.

[0052] The second branch current generation module 22 also includes a fourth PMOS transistor 222, a fifth NMOS transistor 221, and a second transistor 223. The source of the fourth PMOS transistor 222 is connected to the power supply terminal VDD, the gate and drain of the fourth PMOS transistor 222 are connected, the drain of the fourth PMOS transistor 222 is connected to the drain of the fifth NMOS transistor 221, the gate of the fifth NMOS transistor 221 is connected to the gate of the fourth NMOS transistor 224, the source of the fifth NMOS transistor 221 is connected to the base of the second transistor 223, and the second adjustable resistor 224 is connected between the source of the fifth NMOS transistor 221 and the ground terminal GND.

[0053] The current synthesis module 23 includes a fifth PMOS transistor 231 and a sixth PMOS transistor 232. The sources of both the fifth PMOS transistor 231 and the sixth PMOS transistor 232 are connected to the power supply terminal VDD. The gate of the fifth PMOS transistor 231 is connected to the gate of the first PMOS transistor 12, and the gate of the sixth PMOS transistor is connected to the gate of the fourth PMOS transistor 222. The drains of the fifth PMOS transistor 231 and the sixth PMOS transistor 232 are connected to each other for outputting a reference current I. ref .

[0054] The first branch current I1 is directly proportional to temperature, which is the PTAT current. The second branch current I2 is inversely proportional to temperature, which is the CTAT current. I1 is the magnitude of the current I1 in the first branch, I2 is the magnitude of the current I2 in the first branch, V BE1 V is the voltage difference between the base and emitter of the first transistor 212. BE2 V is the voltage difference between the base and emitter of the second transistor 223. T This is thermal voltage.

[0055] The fifth PMOS transistor 231 and the first PMOS transistor 12 form a current mirror to mirror the PTAT current I1 generated by the first branch current generation module 21 to the fifth PMOS transistor 231. The sixth PMOS transistor 232 and the fourth PMOS transistor 222 form a current mirror to mirror the CTAT current generated by the second branch current generation module 22 to the sixth PMOS transistor 232. The first branch current I1 and the second branch current I2 are combined by the current synthesis module 23 to generate a reference current I. ref .

[0056] By including a first adjustable resistor 213 in the first branch current generation module 21 and a second adjustable resistor 224 in the second branch current generation module 22, a reference current with a positive temperature drift coefficient, a reference current with a negative temperature drift coefficient, or a reference current with a zero temperature drift coefficient can be generated.

[0057] Specifically, based on the characteristics of the PTAT current I1 and CTAT current I2 generated by the current reference core module 20, the reference current generated based on the PTAT current I1 and CTAT current I2 is...

[0058] The partial derivative of I1 with respect to temperature is The partial derivative of I2 with respect to temperature is Wherein, the partial derivative of I1 with respect to temperature is the temperature drift coefficient of current I1, and the partial derivative of I2 with respect to temperature is the temperature drift coefficient of current I2. For the reference current I... refThe temperature drift coefficient of the reference current is obtained by performing a partial derivative with respect to temperature.

[0059] The temperature drift coefficient of the reference current is related to the resistance values ​​of the first adjustable resistor 213 and the second adjustable resistor 224. By adjusting the resistance values ​​of the first adjustable resistor 213 and the second adjustable resistor 224, the temperature drift coefficients of the first branch current I1 and the second branch current I2 can be adjusted respectively, thereby achieving the purpose of adjusting the temperature drift coefficient of the current reference Iref. According to the actual circuit requirements, a reference current with a positive temperature drift coefficient, a reference current with a negative temperature drift coefficient, and a reference current that is almost independent of temperature can be generated, improving the flexibility and practicality of the current reference circuit.

[0060] To generate a reference current with a positive temperature drift coefficient, the resistance values ​​of the first adjustable resistor 213 and the second adjustable resistor 224 are adjusted to achieve this. Right now

[0061] To generate a reference current with a negative temperature drift coefficient, the resistance values ​​of the first adjustable resistor 213 and the second adjustable resistor 224 are adjusted to achieve this. Right now

[0062] To generate a reference current with zero temperature drift, the resistance values ​​of the first adjustable resistor 213 and the second adjustable resistor 224 are adjusted to achieve this. Right now

[0063] Please refer to Figure 4 , Figure 4 This is a circuit diagram of a current reference circuit according to another embodiment of this application. Figure 4 In the embodiment shown, the first adjustable resistor 213 includes a first resistor 2131 and a plurality of first optional resistors 2132 connected in series with the first resistor 2131, and each first optional resistor 2132 is connected in parallel with a first control switch 2133.

[0064] By controlling the on / off state of the first control switch 2133, the short-circuit status of the first optional resistor 2132 connected in parallel with the first control switch 2133 is controlled. When the first control switch 2133 is on, the first optional resistor 2132 connected in parallel with the first control switch 2133 is short-circuited; when the first control switch 2133 is off, the first optional resistor 2132 connected in parallel with the first control switch 2133 is not short-circuited. The resistance of the first adjustable resistor 213 is the sum of the resistance of the first resistor 2131 and the resistance of the first optional resistor 2132 that is not short-circuited.

[0065] exist Figure 4In the illustrated embodiment, the first control switch 2133 is an NMOS transistor. The gate of the NMOS transistor is connected to an enable signal, and the source and drain of the NMOS transistor are respectively connected to the two ends of the first selectable resistor 2132. By controlling the on / off state of the NMOS transistor, the resistance value of the first adjustable resistor 213 can be adjusted.

[0066] exist Figure 4 In the embodiment shown, the second adjustable resistor 224 includes a second resistor 2241 and a plurality of second optional resistors 2242 connected in series with the second resistor 2241, and each second optional resistor 2242 is connected in parallel with a second control switch 2243.

[0067] By controlling the on / off state of the second control switch 2243, the short-circuit status of the second optional resistor 2242 connected in parallel with the second control switch 2243 is controlled. When the second control switch 2243 is on, the second optional resistor 2242 connected in parallel with the second control switch 2243 is short-circuited; when the second control switch 2243 is off, the second optional resistor 2242 connected in parallel with the second control switch 2243 is not short-circuited. The resistance value of the second adjustable resistor 224 is the sum of the resistance value of the second resistor 2241 and the resistance value of the second optional resistor 2242 that is not short-circuited.

[0068] The second control switch 2243 is an NMOS transistor. The gate of the NMOS transistor is connected to an enable signal, and the source and drain of the NMOS transistor are respectively connected to the two ends of the second selectable resistor 2242. By controlling the on and off of the NMOS transistor, the resistance value of the second adjustable resistor 224 can be adjusted.

[0069] Please continue to refer to this. Figure 4 ,exist Figure 4 In the illustrated embodiment, the second branch current generation module 22 of the current reference core module 20 is equipped with a transmission gate switch 25, which consists of an NMOS transistor and a PMOS transistor connected in parallel. When the transmission gate switch 25 is not turned on, the operation of the current reference circuit 1 is cut off, thereby reducing the power consumption of the current reference circuit 1. By using the transmission gate switch 25, the power consumption of the current reference circuit 1 can be effectively turned off or reduced when the reference current is not needed, achieving the purpose of saving energy.

[0070] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0071] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A current reference circuit, characterized by, include: The current reference core module is used to output a reference current; The first switch is a PMOS transistor and is connected to the current reference core module. A startup module, connected to the first switch, is used to control the first switch to connect with the current reference core module during the power-on process at the power supply end, transmit a startup current to the current reference core module through the first switch to start the current reference core module, and control the first switch to disconnect after completing the transmission of startup current to the current reference core module.

2. The current reference circuit of claim 1, wherein, The current reference core module includes a first PMOS transistor; the first PMOS transistor is connected between the first switch and the power supply terminal, the first switch is connected between the first PMOS transistor and the ground terminal, and the gate and drain of the first PMOS transistor are connected. The startup module includes a second PMOS transistor, a first node, a second node, and a capacitor. The first node is connected between the first switch and the first PMOS transistor. The source of the second PMOS transistor is connected to the power supply terminal, and the drain of the second PMOS transistor is grounded through the capacitor. The second node is connected between the second PMOS transistor and the capacitor. The gate of the second PMOS transistor is connected to the first node, the gate of the first switch is connected to the second node, and the source of the first switch is connected to the first node.

3. The current reference circuit according to claim 2, characterized in that, A resistive element is connected between the first switch and the grounding terminal.

4. The current reference circuit according to claim 3, characterized in that, The resistive element is a first NMOS transistor. The gate of the first NMOS transistor is connected to a voltage source or an enable terminal, the source of the first NMOS transistor is connected to the ground terminal, and the drain of the first NMOS transistor is connected to the first switch.

5. The current reference circuit according to claim 2, characterized in that, A current-limiting resistive device is connected between the second PMOS transistor and the ground terminal.

6. The current reference circuit according to claim 5, characterized in that, The current-limiting resistive device is a second NMOS transistor. The gate of the second NMOS transistor is connected to the upper plate of the capacitor, the source of the second NMOS transistor is connected to the ground terminal, and the drain of the second NMOS transistor is connected to the second node.

7. The current reference circuit according to claim 2, characterized in that, The gates of the first PMOS transistor and the second PMOS transistor are connected, and the first PMOS transistor and the second PMOS transistor form a current mirror; the startup module is used to control the first switch to connect with the current reference core module when the power supply is powered on, inject startup current into the current reference core module through the first switch, and control the first switch to disconnect after completing the transmission of startup current to the current reference core module.

8. The current reference circuit according to claim 2, characterized in that, The current reference core module includes a first branch current generation module, a second branch current generation module, and a current synthesis module. The first branch current generation module includes a first adjustable resistor and is used to generate a first branch current, which is a current proportional to temperature. The second branch current generating module includes a second adjustable resistor. The second branch current generating module is used to generate a second branch current, which is a current that is inversely proportional to temperature. The current synthesis module is connected to the first branch current generation module and the second branch current generation module respectively, and is used to generate a reference current based on the first branch current and the second branch current.

9. The current reference circuit according to claim 8, characterized in that, The first branch current generation module further includes a first PMOS transistor, a third NMOS transistor, a first transistor, a third PMOS transistor, a fourth NMOS transistor, and a second transistor. The sources of the first PMOS transistor and the third PMOS transistor are both connected to the power supply terminal. The gates of the first PMOS transistor and the third PMOS transistor are connected. The drain of the first PMOS transistor is connected to the drain of the third NMOS transistor. The drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the fourth NMOS transistor is connected to the gate of the fourth NMOS transistor. The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor. The source of the third NMOS transistor is connected to the collector of the first transistor. The first adjustable resistor is connected between the emitter of the first transistor and the ground terminal. The source of the fourth NMOS transistor is connected to the collector of the second transistor. The emitter of the second transistor is connected to the ground terminal. The base of the first transistor and the base of the second transistor are connected.

10. The current reference circuit according to claim 9, characterized in that, The second branch current generation module further includes a fourth PMOS transistor, a fifth NMOS transistor, and a second transistor. The source of the fourth PMOS transistor is connected to the power supply terminal, the gate and drain of the fourth PMOS transistor are connected, the drain of the fourth PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the gate of the fourth NMOS transistor, the source of the fifth NMOS transistor is connected to the base of the second transistor, and the second adjustable resistor is connected between the source of the fifth NMOS transistor and the ground terminal.

11. The current reference circuit according to claim 10, characterized in that, The current synthesis module includes a fifth PMOS transistor and a sixth PMOS transistor. The sources of the fifth PMOS transistor and the sixth PMOS transistor are both connected to the power supply terminal. The gate of the fifth PMOS transistor is connected to the gate of the first PMOS transistor. The gate of the sixth PMOS transistor is connected to the gate of the fourth PMOS transistor. The drains of the fifth PMOS transistor and the drains of the sixth PMOS transistor are connected to each other for outputting the reference current.

12. The current reference circuit according to claim 8, characterized in that, The first adjustable resistor includes a first resistor and a plurality of first optional resistors connected in series with the first resistor, and each of the first optional resistors is connected in parallel with a first control switch; The second adjustable resistor includes a second resistor and a plurality of second optional resistors connected in series with the second resistor, and each of the second optional resistors is connected in parallel with a second control switch.

13. The current reference circuit according to claim 8, characterized in that, The second branch current generation module of the current reference module is equipped with a transmission gate switch.

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