signal detection circuit

Abstract

A signal detection circuit (400) includes a signal input terminal (402), a rectifier circuit (404), a comparator circuit (406); a current source (408), and a comparator output terminal (412). The rectifier circuit (404) is coupled to the signal input terminal (402) and configured to receive an input signal and generate a rectified signal based on the input signal. The comparator circuit (406) is coupled to the rectifier circuit (404) and configured to receive a common mode signal and generate a difference current based on a difference of the common mode signal and the rectified signal. The current source (408) is coupled to the comparator circuit (406) and configured to generate a reference current. The comparator output terminal (412) is configured to provide an output signal based on a difference of the reference current and the difference current.

Description

Background Technology

[0001] To reduce power consumption, some electronic systems de-energize various subsystems when they are not needed. Such systems monitor operating conditions to determine whether a particular subsystem needs and should be powered on. For example, the communication subsystem can be powered off when no communication is received for a predetermined time. Simultaneously with the communication subsystem powered off, the system monitors the communication medium for indications of attempted communication, and if an attempt is detected, powers the communication subsystem back on. Summary of the Invention

[0002] This document discloses a signal detection circuit with reduced complexity and power consumption (e.g., less than 25 microamps). In one example, a signal detection circuit includes a signal input terminal, a common-mode input terminal, a comparator output terminal, a signal input transistor, a resistor, a capacitor, a common-mode input transistor, a current mirror circuit, and a current source. The signal input transistor includes a first terminal coupled to the signal input terminal and a second terminal coupled to a reference voltage source. The resistor includes a first terminal coupled to a third terminal of the signal input transistor. The capacitor includes a first terminal coupled to the first terminal of the resistor and a second terminal coupled to the reference voltage source. The common-mode input transistor includes a first terminal coupled to the common-mode input terminal and a second terminal coupled to the reference voltage source. The current mirror circuit includes a first transistor and a second transistor. The first transistor includes a first terminal coupled to the second terminal of the resistor and a second terminal coupled to the third terminal of the first transistor. The second transistor includes a first terminal coupled to the third terminal of the common-mode input transistor and a second terminal coupled to the second terminal of the first transistor. The current source includes a transistor. The transistor of the current source includes a first terminal coupled to a power rail, and a third terminal coupled to the third terminal of the second transistor of the current mirror circuit and a second terminal coupled to the comparator output terminal.

[0003] In another example, a signal detection circuit includes a signal input terminal, a rectifier circuit, a comparator circuit, a current source, and a comparator output terminal. The rectifier circuit is coupled to the signal input terminal and configured to receive an input signal and generate a rectified signal based on the input signal. The comparator circuit is coupled to the rectifier circuit and configured to receive a common-mode signal and generate a differential current based on the difference between the common-mode signal and the rectified signal. The current source is coupled to the comparator circuit and configured to generate a reference current. The comparator output terminal is configured to provide an output signal indicating that a signal has been detected at the signal input terminal based on the difference between the reference current and the differential current.

[0004] In a further example, a communication circuit includes a wake-up circuit configured to monitor a communication medium for a signal. The wake-up circuit includes a signal detection circuit. The signal detection circuit includes a signal input terminal, a common-mode input terminal, a comparator output terminal, a signal input transistor, a resistor, a capacitor, a common-mode input transistor, a first current mirror circuit, a second current mirror circuit, and a current source. The signal input transistor includes a first terminal coupled to the signal input terminal and a second terminal coupled to a reference voltage source. The resistor includes a first terminal coupled to a third terminal of the signal input transistor. The capacitor includes a first terminal coupled to the first terminal of the resistor and a second terminal coupled to the reference voltage source. The common-mode input transistor includes a first terminal coupled to the common-mode input terminal and a second terminal coupled to the reference voltage source. The first current mirror circuit includes a first transistor and a second transistor. The first transistor includes a first terminal coupled to the second terminal of the resistor and a second terminal coupled to the third terminal of the first transistor. The second transistor includes a first terminal coupled to the third terminal of the common-mode input transistor and a second terminal coupled to the second terminal of the first transistor. The second current mirror circuit includes both the first transistor and the second transistor. The first transistor of the second current mirror circuit includes a first terminal coupled to a second terminal of the first transistor of the first current mirror circuit, and a second terminal coupled to a third terminal of the first transistor of the second current mirror circuit. The second transistor of the second current mirror circuit includes a first terminal coupled to a third terminal of the second transistor of the first current mirror circuit, and a second terminal coupled to a second terminal of the second transistor of the first current mirror circuit. The current source includes a transistor. The transistor of the current source includes a first terminal coupled to a power rail, and a second terminal coupled to a third terminal of the second transistor of the second current mirror circuit and a comparator output terminal. Attached Figure Description

[0005] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1 A block diagram of a system including a signal detection circuit according to this specification is shown;

[0007] Figure 2 A block diagram of a communication circuit including a signal detection circuit according to this specification is shown;

[0008] Figure 3 It shows the result of Figure 2 The signals generated by the operation of the communication circuit;

[0009] Figure 4 A schematic diagram of an example single-ended signal detection circuit according to this specification is shown;

[0010] Figure 5A schematic diagram of another example single-ended signal detection circuit according to this specification is shown;

[0011] Figure 6 A schematic diagram of an example rectifier circuit used in a signal detection circuit with differential input signals, according to this specification, is shown; and

[0012] Figure 7 and Figure 8 The signal in the signal detection circuit according to this specification is shown. Detailed Implementation

[0013] In this specification, the terms "coupled" or "connected" refer to an indirect or direct wired or wireless connection. Therefore, if a first device is coupled to a second device, the connection can be either a direct connection or an indirect connection via other devices and connections. Furthermore, in this specification, the statement "based on" means "at least partially based on". Therefore, if X is based on Y, then X can be a function of Y and any number of other factors.

[0014] In communication circuits, when the circuit requiring communication is de-energized, a signal detection circuit monitors the communication medium to identify the communication signal. In response to the signal detection circuit detecting the communication signal, the circuit requiring communication (such as a receiver circuit) is energized. Some signal detection circuits use large, complex comparator circuits to identify the communication signal. Such comparators may consume excessive power and are unsuitable for low-power signal detection circuits.

[0015] The signal detection circuit disclosed herein is characterized by reduced power consumption and reduced circuit area for use in low-power applications. The signal detection circuit uses a simple single-ended, single-stage current-domain comparator that provides high gain and low offset with very low power consumption. The differential implementation of the signal detection circuit provides twice the gain of other architectures.

[0016] Figure 1 A block diagram of a system 100 including signal detection circuitry according to this specification is shown. System 100 includes a transmitter circuitry 102 and a receiver circuitry 104 communicating via a medium 103. In some embodiments of system 100, the medium 103 is a coaxial or twisted-pair cable. Transmitter circuitry 102 includes a forward channel transmitter 106, a reverse channel receiver 108, and signal detection circuitry 110. Forward channel transmitter 106, reverse channel receiver 108, and signal detection circuitry 110 are coupled to the medium 103 and a control circuitry system 112. Receiver circuitry 104 includes a forward channel receiver 114, a reverse channel transmitter 116, and signal detection circuitry 118. Forward channel receiver 114, reverse channel transmitter 116, and signal detection circuitry 118 are coupled to the medium 103 and a control circuitry system 120.

[0017] To reduce power consumption in transmitter circuit 102, portions of the forward channel transmitter 106, reverse channel receiver 108, control circuitry 112, and other circuitry of transmitter circuit 102 can be de-energized, while signal detection circuitry 110 remains powered to monitor medium 103 for reverse channel transmission. When signal detection circuitry 110 detects reverse channel transmission (e.g., a transition on medium 103), it signals control circuitry 112, which in turn powers on reverse channel receiver 108, or both reverse channel receiver 108 and forward channel transmitter 106, to communicate with receiver circuitry 104.

[0018] Similarly, to reduce power consumption in receiver circuitry 104, portions of the forward channel receiver 114, reverse channel transmitter 116, control circuitry 120, and other circuitry of receiver circuitry 104 can be de-energized, while signal detection circuitry 118 remains powered to monitor the forward channel transmission medium 103. When signal detection circuitry 118 detects forward channel transmission (e.g., a transition on medium 103), it signals control circuitry 118, which in turn powers on forward channel receiver 114, or both forward channel receiver 114 and reverse channel transmitter 116, to communicate with transmitter circuitry 102.

[0019] Figure 2 A communication circuit 200 is shown, which includes a portion of a transmitter circuit 102. The transmitter circuit 102 is coupled to a controller 202 and voltage regulators 204, 206, and 208. The controller 202 activates and deactivates an output signal 210 to cause the transmitter circuit 102 to enter and exit a low-power state. Regulators 204, 206, and 208 provide power for the operation of the transmitter circuit 102. When in a low-power state, regulator 204 provides power for the operation of a wake-up circuit 201. Regulators 206 and 208 provide power for the operation of other circuitry within the transmitter circuit 102 and are disabled when the transmitter circuit 102 is in a low-power state.

[0020] The wake-up circuit 201 includes a signal detection circuit 110 that monitors the medium 103 and activates an output signal 210 when a signal is detected on the medium 103. Activation of the output signal 210 sets a latch 212, the output of which enables regulators 206 and 208 and notifies the controller 202 that communication needs to be enabled. The controller 202 deactivates the output signal 210, allowing the signal detection circuit 110 to exit a low-power state. When the transmitter circuit 102 operates in a normal power state (i.e., a non-low-power state), the latch 212 remains set while data exists on the medium 103. When there is no transmission on the medium 103, the pulse generator circuit 214 generates a pulse to reset the latch 212, thereby disabling regulators 206 and 208 and notifying the controller 202 that the transmitter circuit 102 can be placed in a low-power state to reduce power consumption.

[0021] Figure 3 The signal generated by the operation of communication circuit 200 is shown. At 302, regulator 204 is powered to provide voltage 216 for powering signal detection circuit 110. Regulators 206 and 208 are disabled. At 306, a transmission is present on medium 103. Signal detection circuit 110 detects the transmission and switches output signal 210 to set latch 212 and activate signal 226. In response to the activation of signal 226, regulators 206 and 208 are enabled.

[0022] At 308, the transition on medium 103 stops and the valid_data_n signal 224 is deactivated, causing pulse generator circuit 214 to generate pulse 222 that resets latch 212 and deactivates signal 226. Deactivation of signal 226 disables regulators 206 and 208 and notifies controller 202 of no communication, thereby allowing controller 202 to return transmitter circuit 102 to a low-power state.

[0023] Figure 4A schematic diagram of an example signal detection circuit 400 according to this specification is shown. The signal detection circuit is an embodiment of signal detection circuit 110 or signal detection circuit 118. The signal detection circuit 400 includes a signal input terminal 402 for detecting a single-ended signal, a rectifier circuit 404, a comparator circuit 406, a current source 408, a current source 410, a comparator output terminal 412, an inverter 414, and a current mirror circuit 422. The rectifier circuit 404 is coupled to the signal input terminal 402. The rectifier circuit 404 receives an input signal and generates a rectified signal based on the received input signal. The rectifier circuit 404 includes a signal input transistor 416, a capacitor 418, and a resistor 420. The signal input transistor 416 receives the input signal provided at the signal input terminal 402. The gate terminal 416G of the signal input transistor 416 is coupled to the signal input terminal 402. The drain terminal 416D of the signal input transistor 416 is coupled to a reference voltage source 436, such as ground. The source terminal 416S of the signal input transistor 416 is coupled to terminal 418A of capacitor 418 and terminal 420A of resistor 420. Terminal 418B of capacitor 418 is coupled to a reference voltage source. A signal at signal input terminal 402 turns on signal input transistor 416, causing capacitor 418 to discharge. Therefore, the voltage across capacitor 418 is a function of the signal at signal input terminal 402.

[0024] Current source 410 provides current to charge capacitor 418 via current mirror circuit 422. Current source 410 includes transistor 411. The source terminal 411S of transistor 411 is coupled to power rail 434. The drain terminal 411D of transistor 411 is coupled to the drain terminal 424D of transistor 424. Current mirror circuit 422 includes transistor 424 and transistor 426. Transistor 424 is diode-connected. The source terminal 424S of transistor 424 is coupled to terminal 420B of resistor 420. The drain terminal 424D of transistor 424 is coupled to current source 410 and gate terminal 424G of transistor 424. 424G of transistor 424 is coupled to gate terminal 426G of transistor 426 and to terminal 432A of capacitor 432. Terminal 432B of capacitor 432 is coupled to a reference voltage source. The comparator circuit 406 is coupled to the rectifier circuit 404 via the current mirror circuit 422. The current flowing in the rectifier circuit 404 is reflected in the comparator circuit 406 via the current mirror circuit 422.

[0025] Comparator circuit 406 includes common-mode input transistor 428 and resistor 430. Resistor 430 is omitted in some embodiments of comparator circuit 406. Comparator circuit 406 receives a common-mode signal, generates a difference voltage based on the difference between the common-mode voltage and the rectified signal provided by rectifier circuit 404, and generates a difference current based on the difference voltage. The gate terminal 428G of common-mode input transistor 428 is coupled to common-mode input terminal 431. The voltage at common-mode input terminal 431 is the average value of the input signal voltage at signal input terminal 402. The drain terminal 428D of common-mode input transistor 428 is coupled to a reference voltage source. The source terminal 428S of common-mode input transistor 428 is coupled to the source terminal 426S of transistor 426 via resistor 430. The source terminal 428S of common-mode input transistor 428 is coupled to terminal 430A of resistor 430. Terminal 430B of resistor 430 is coupled to source terminal 426S of transistor 426.

[0026] Current source 408 provides a reference current to comparator circuit 406 via transistor 426 of current mirror circuit 422. Current source 408 includes transistor 409. The source terminal 409S of transistor 409 is coupled to power rail 434. The drain terminal 409D of transistor 409 is coupled to the drain terminal 426D of transistor 426 and comparator output terminal 412. The current at comparator output terminal 412 is the difference between the reference current and the differential current generated in comparator circuit 406. Inverter 414 (inverter 414A, the input terminal of inverter 414) is coupled to comparator output terminal 412. The voltage at comparator output terminal 412 is a function of the difference between the common-mode voltage and the reference voltage. As the difference increases, the voltage at comparator output terminal 412 exceeds the threshold of inverter 414, and the output of inverter 414 is pulled to ground, indicating that a signal has been detected at signal input terminal 402.

[0027] Figure 5A schematic diagram of an example signal detection circuit 500 according to this specification is shown. The signal detection circuit 500 is similar to the signal detection circuit 400 and includes a cascaded current mirror circuit 502. The cascaded current mirror circuit 502 improves the performance of the signal detection circuit 500 in terms of process, voltage, and temperature to reduce the variation in the switching point (e.g., to one-third or less of that of the signal detection circuit 400). The cascaded current mirror circuit 502 includes transistors 504 and 506. Transistor 504 is diode-connected. The source terminal 504S of transistor 504 is coupled to the drain terminal 424D of transistor 424. The drain terminal 504D of transistor 504 is coupled to a current source 410 and the gate terminal 504G of transistor 504. The 504G of transistor 504 is coupled to the gate terminal 506G of transistor 506. The source terminal 506S of transistor 506 is coupled to the drain terminal 426D of transistor 426. The drain terminal 506D of transistor 506 is coupled to current source 408 and comparator output terminal 412. The current flowing through rectifier circuit 404 is reflected in comparator circuit 406 via cascaded current mirror circuit 502.

[0028] The signal detection circuit 500 is shown with resistor 430 omitted, which further reduces the variation of the switching point with voltage, process, and temperature. Some implementations of the signal detection circuit 500 include resistor 430.

[0029] Figure 6 A schematic diagram of an example rectifier circuit 600 for use in a signal detection circuit having differential input signals, according to this specification, is shown. Rectifier circuit 600 is adapted to replace rectifier circuit 404 in signal detection circuit 400 or signal detection circuit 500. Rectifier circuit 600 includes signal input terminal 402, signal input terminal 403, signal input transistor 604, capacitor 606, capacitor 608, resistor 610, resistor 612, and capacitor 418. Signal input transistor 602 and signal input transistor 604 receive the positive and negative signals of the differential input signals, respectively.

[0030] The gate terminal 602G of signal input transistor 602 is coupled to signal input terminal 402. The drain terminal 602D of signal input transistor 602 is coupled to a reference voltage source. The source terminal 602S of signal input transistor 602 is coupled to terminal 612A of resistor 612. Terminal 612B of resistor 612 is coupled to capacitor 418. The gate terminal 604G of signal input transistor 604 is coupled to signal input terminal 403. The drain terminal 604D of signal input transistor 604 is coupled to a reference voltage source. The source terminal 604S of signal input transistor 604 is coupled to terminal 610A of resistor 610. Terminal 610B of resistor 610 is coupled to capacitor 418.

[0031] Capacitors 606 and 608 are cross-coupled relative to signal input transistors 602 and 604. Terminal 606A of capacitor 606 is coupled to the source terminal 602S of signal input transistor 602, and terminal 606B of capacitor 606 is coupled to signal input terminal 403. Terminal 608A of capacitor 608 is coupled to the source terminal 604S of signal input transistor 604, and terminal 608B of capacitor 608 is coupled to signal input terminal 402. In some embodiments of rectifier circuit 600, the capacitance of capacitors 606 and 608 is at least twice the gate-source capacitance of signal input transistor 602 or signal input transistor 604. The inclusion of capacitors 606 and 608 increases the gain of rectifier circuit 600 by at least double relative to signal detection circuit 400 or signal detection circuit 500.

[0032] Figure 7 and Figure 8 The signal in the signal detection circuit according to this specification is shown. Figure 7 The operation of an embodiment of the signal detection circuit 400 detecting an input signal 702 at signal input terminal 402 at 1.5 gigabits per second is illustrated. The voltage 704 generated by the rectifier circuit 404 (i.e., the voltage across capacitor 432) decreases as energy of the input signal 702 accumulates. In response to the decreasing voltage 704, the comparator output voltage 706 (the voltage at comparator output terminal 412) increases, and the inverter 414 changes state at 708 to indicate that the input signal 702 has been detected. Some embodiments of the signal detection circuit 400 include an inverter with hysteresis coupled to the inverter 414, which changes state at 710 in response to the transition at 708.

[0033] Figure 8The operation of an embodiment of the signal detection circuit 400 detecting an input signal 802 at signal input terminal 402 is illustrated. The voltage 804 generated by the rectifier circuit 404 (i.e., the voltage across capacitor 432) decreases as energy of the input signal 802 accumulates. In response to the decreasing voltage 802, the comparator output voltage 806 (the voltage at comparator output terminal 412) increases, and the inverter 414 changes state at 808 to indicate that the input signal 802 has been detected. Some embodiments of the signal detection circuit 400 include an inverter with hysteresis coupled to the inverter 414, which changes state at 810 in response to the transition at 808.

[0034] Within the scope of the claims, modifications to the described embodiments are possible, and other embodiments are also possible.

Claims

1. A signal detection circuit, comprising: Signal input terminals; Common-mode input terminal; Comparator output terminals; The signal input transistor includes: A first terminal, which is coupled to the signal input terminal; and The second terminal is coupled to a reference voltage source; A resistor, which includes a first terminal coupled to a third terminal of the signal input transistor; Capacitors, including: A first terminal, which is coupled to the first terminal of the resistor; and The second terminal is coupled to the reference voltage source; Common-mode input transistor, comprising: A first terminal, which is coupled to the common-mode input terminal; and The second terminal is coupled to the reference voltage source; A current mirror circuit includes: The first transistor includes: A first terminal, which is coupled to a second terminal of the resistor; and The second terminal is coupled to the third terminal of the first transistor; and The second transistor includes: The first terminal is coupled to the third terminal of the common-mode input transistor; and The second terminal is coupled to the second terminal of the first transistor; and Current source, comprising: Transistor, comprising: The first terminal, which is coupled to the power rail; and The second terminal is coupled to the third terminal of the second transistor in the current mirror circuit and the comparator output terminal.

2. The signal detection circuit according to claim 1, wherein: The current mirror circuit is a first current mirror circuit; and The signal detection circuit further includes: The second current mirror circuit includes: The first transistor includes: The first terminal, coupled to the third terminal of the first transistor in the first current mirror circuit; and The second terminal is coupled to the third terminal of the first transistor in the second current mirror circuit; and The second transistor includes: The first terminal is coupled to the third terminal of the second transistor of the first current mirror circuit; The second terminal is coupled to the second terminal of the first transistor in the second current mirror circuit; and The third terminal is coupled to the comparator output terminal.

3. The signal detection circuit according to claim 1, wherein: The capacitor is a first capacitor; and The signal detection circuit further includes: The second capacitor includes: A first terminal, coupled to the second terminal of the first transistor in the current mirror circuit; and The second terminal is coupled to the reference voltage source.

4. The signal detection circuit according to claim 1, further comprising an inverter, the inverter including an input terminal coupled to the output terminal of the comparator.

5. The signal detection circuit according to claim 1, wherein: The resistor is the first resistor; and The signal detection circuit further includes: The second resistor includes: A first terminal, coupled to the third terminal of the common-mode input transistor; and The second terminal is coupled to the first terminal of the second transistor of the current mirror circuit.

6. The signal detection circuit according to claim 1, wherein: The signal input transistor is a first signal input transistor; The resistor is the first resistor; The signal input terminal is the first signal input terminal; and The signal detection circuit further includes: Second signal input terminal; The second signal input transistor includes: A first terminal, which is coupled to the second signal input terminal; and The second terminal is coupled to the reference voltage source; and The second resistor includes: The first terminal is coupled to the third terminal of the second signal input transistor; and The second terminal is coupled to the first terminal of the capacitor.

7. The signal detection circuit according to claim 6, further comprising: The second capacitor includes: A first terminal, which is coupled to the first signal input terminal; and The second terminal, coupled to the third terminal of the second signal input transistor; and The third capacitor includes: A first terminal, which is coupled to the second signal input terminal; and The second terminal is coupled to the third terminal of the first signal input transistor.

8. The signal detection circuit according to claim 1, wherein: The current source is a first current source; and The signal detection circuit further includes: The second current source includes: Transistor, comprising: A first terminal, which is coupled to the power rail; and The second terminal is coupled to the third terminal of the first transistor in the current mirror circuit.

9. A signal detection circuit, comprising: Signal input terminals; A rectifier circuit, coupled to the signal input terminal, is configured as follows: Receive input signals; as well as A rectified signal is generated based on the input signal; A comparator circuit, coupled to the rectifier circuit, is configured as follows: Receive common-mode signals; as well as A differential current is generated based on the difference between the common-mode signal and the rectified signal; A current source, coupled to the comparator circuit, is configured to generate a reference current; as well as The comparator output terminal is configured to provide an output signal based on the difference between the reference current and the differential current.

10. The signal detection circuit of claim 9, wherein the comparator circuit is configured to generate a voltage difference between the common-mode signal and the rectified signal.

11. The signal detection circuit of claim 9, further comprising a current mirror circuit configured to provide current to the comparator circuit based on the rectified signal.

12. The signal detection circuit according to claim 9, wherein the rectifier circuit comprises: A signal input transistor, which is coupled to the signal input terminal and configured to receive the input signal; A capacitor coupled to the signal input transistor; as well as A resistor coupled to the signal input transistor.

13. The signal detection circuit of claim 12, further comprising a first current mirror circuit coupled to the resistor and configured to provide a first current to the comparator circuit based on the rectified signal.

14. The signal detection circuit of claim 13, further comprising a second current mirror circuit coupled to the first current mirror circuit and configured to provide a second current to the comparator circuit based on the rectified signal.

15. The signal detection circuit according to claim 12, wherein: The signal input terminal is the first signal input terminal; The signal input transistor is a first signal input transistor; The resistor is the first resistor; The input signal is the first input signal; and The rectifier circuit further includes: Second signal input terminal; A second signal input transistor, coupled to the second signal input terminal and configured to receive a second input signal; and A second resistor is coupled to the second signal input transistor and the capacitor.

16. The signal detection circuit according to claim 15, wherein: The capacitor is a first capacitor; and The signal detection circuit further includes: A second capacitor is coupled to the first signal input terminal and the second signal input transistor; as well as A third capacitor is coupled to the second signal input terminal and the first signal input transistor.

17. A communication circuit, comprising: A wake-up circuit, configured to monitor a signal communication medium, includes: The signal detection circuit includes: Signal input terminals; Common-mode input terminal; Comparator output terminals; The signal input transistor includes: A first terminal, which is coupled to the signal input terminal; and The second terminal is coupled to a reference voltage source; A resistor, which includes a first terminal coupled to a third terminal of the signal input transistor; Capacitors, including: A first terminal, which is coupled to the first terminal of the resistor; and The second terminal is coupled to the reference voltage source; Common-mode input transistor, comprising: A first terminal, which is coupled to the common-mode input terminal; and The second terminal is coupled to the reference voltage source; The first current mirror circuit includes: The first transistor includes: A first terminal, which is coupled to a second terminal of the resistor; and The second terminal is coupled to the third terminal of the first transistor; and The second transistor includes: The first terminal is coupled to the third terminal of the common-mode input transistor; and The second terminal is coupled to the second terminal of the first transistor; The second current mirror circuit includes: The first transistor includes: A first terminal, which is coupled to the second terminal of the first transistor of the first current mirror circuit; and The second terminal is coupled to the third terminal of the first transistor in the second current mirror circuit; and The second transistor includes: The first terminal, coupled to the third terminal of the second transistor in the first current mirror circuit; and The second terminal is coupled to the second terminal of the first transistor in the second current mirror circuit; and Current source, comprising: Transistor, comprising: The first terminal, which is coupled to the power rail; and The second terminal is coupled to the third terminal of the second transistor in the second current mirror circuit and the comparator output terminal.

18. The communication circuit according to claim 17, wherein: The signal input transistor is a first signal input transistor; The resistor is the first resistor; The signal input terminal is the first signal input terminal; and The signal detection circuit further includes: Second signal input terminal; The second signal input transistor includes: A first terminal, which is coupled to the second signal input terminal; and The second terminal is coupled to the reference voltage source; and The second resistor includes: The first terminal is coupled to the third terminal of the second signal input transistor; and The second terminal is coupled to the first terminal of the capacitor.

19. The communication circuit according to claim 18, wherein: The capacitor is a first capacitor; and The signal detection circuit further includes: The second capacitor includes: A first terminal, which is coupled to the first signal input terminal; and The second terminal, coupled to the third terminal of the second signal input transistor; and The third capacitor includes: A first terminal, which is coupled to the second signal input terminal; and The second terminal is coupled to the third terminal of the first signal input transistor.

20. The communication circuit according to claim 17, wherein: The current source is a first current source; and The signal detection circuit further includes: The second current source includes: Transistor, comprising: A first terminal, which is coupled to the power rail; and The second terminal is coupled to the third terminal of the first transistor in the second current mirror circuit.

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