Phase change memory array fault test circuit

Abstract

The invention relates to the technical field of phase change memory testing, in particular to a phase change memory array fault testing circuit which comprises a storage unit read-write circuit, a double-path current real-time monitoring circuit and a parallel reference read detection circuit. Wherein the storage unit read-write circuit is connected with the 1T1R phase change storage unit, the double-path current real-time monitoring circuit is connected with a bit line path and a source line path, synchronous sampling and dynamic comparison are carried out on bit internal line current and source internal line current in the write-in operation period, and corresponding judgment signals are output; and the parallel reference reading detection circuit is connected with the output end of the double-path current real-time monitoring circuit, copies the detected current to a plurality of branches and compares the detected current with the multi-stage reference current in parallel. According to the phase change memory array fault test circuit provided by the invention, online current monitoring and rapid logic judgment can be realized in an array level test process, and the capability of detecting resistance type defects such as short circuit, bridging and open circuit and composite anomalies caused by the resistance type defects is improved.

Description

Technical Field

[0001] This invention relates to the field of phase change memory testing technology, specifically a phase change memory array fault testing circuit. Background Technology

[0002] As technology nodes approach the atomic scale, the miniaturization of integrated circuits faces unprecedented challenges. Emerging applications are placing increasing demands on high performance, low power consumption, and high integration, putting immense pressure on device technology and computer architecture. Simultaneously, issues such as device reliability, leakage current, and cost have become critical technical bottlenecks that urgently need to be addressed. Furthermore, limitations in memory, power management, and instruction-level parallelism have also restricted the development of the von Neumann architecture to some extent. Against this backdrop, phase-change memory (PCRAM), a non-volatile storage technology based on the reversible transition of phase-change materials between amorphous and crystalline states, has become a strong candidate to replace traditional CMOS memory. This is mainly due to its excellent CMOS process compatibility, fast switching speed, low standby power consumption, and high-density scalability.

[0003] However, with the continuous shrinking of PCRAM device size and the increasing scale of arrays, the detection capability of traditional static fault test circuits at the nanoscale for heat-sensitive defects and transient faults is gradually limited, easily leading to heat accumulation and increased energy consumption, making it difficult to meet the requirements of efficient, low-overhead array-level testing. Research shows that PCRAM not only experiences static and dynamic faults found in conventional memories, but also some unique, special faults. PCRAM operation relies on changes in heat to store information; therefore, the design and implementation of its memory cells must ensure effective isolation between cells. Furthermore, under different operating conditions, the voltage must be maintained within design limits to ensure normal device operation and reliable data retention. Failure to meet these requirements may lead to various PCRAM-specific faults. Traditional testing techniques cannot accurately distinguish the five states of PCRAM, resulting in many faults not being detected in a timely manner. Therefore, to improve fault detection coverage, it is necessary to develop novel test circuits and algorithms specifically for PCRAM. Summary of the Invention

[0004] The purpose of this invention is to provide a phase-change memory array fault test circuit to solve the problems mentioned in the background art.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] A phase-change memory array fault test circuit includes: a memory array read / write circuit 1, a dual-path current real-time monitoring circuit 2, and a parallel reference read detection circuit 3;

[0007] The storage array read / write circuit 1 includes a first storage array read / write circuit 11, a second storage array read / write circuit 12, a first dual-path current real-time monitoring circuit 13, a second dual-path current real-time monitoring circuit 14, and a first parallel reference read detection circuit 15.

[0008] The first storage array read / write circuit 11 includes a first tri-state gate 111, a second tri-state gate 112, a first NMOS 113, a first phase-change memory 114, a second NMOS 115, and a second phase-change memory 116;

[0009] The second storage array read / write circuit 12 has the same structure as the first storage array read / write circuit 11;

[0010] The first dual-path current real-time monitoring circuit 13 and the second dual-path current real-time monitoring circuit 14 have the same structure as the dual-path current real-time monitoring circuit 2.

[0011] The first parallel reference read detection circuit 15 has the same structure as the parallel reference read detection circuit 3.

[0012] Preferably, the first memory array read / write circuit 11 includes: a first tri-state gate 111, a second tri-state gate 112, a first NMOS 113, a first phase-change memory 114, a second NMOS 115, and a second phase-change memory 116;

[0013] The enable terminal of the first tri-state gate 111 is connected to the write enable signal EN. write The input terminal of the first tri-state gate 111 is connected to the input signal IN. BL The output terminal of the first tri-state gate 111 is connected to the source of the first NMOS 113, the source of the second NMOS 115, and the upper input terminal of the dual-path current real-time monitoring circuit 2, respectively.

[0014] The enable terminal of the second tri-state gate 112 is connected to the write enable signal EN. write The input terminal of the second tri-state gate 112 is connected to the input signal IN. SL The output terminal of the second tri-state gate 112 is connected to the negative terminal of the first phase change memory 114, the negative terminal of the second phase change memory 116, and the lower input terminal of the dual-path current real-time monitoring circuit 2.

[0015] The gate of the first NMOS 113 is connected to the input signal WL0, the source is connected to the output terminal of the first tri-state gate 111 and the upper input terminal of the dual-path current real-time monitoring circuit 2, and the drain is connected to the positive terminal of the first phase-change memory 114.

[0016] The positive terminal of the first phase-change memory 114 is connected to the drain of the first NMOS 113, and the negative terminal is connected to the output terminal of the second tri-state gate 112 and the lower input terminal of the dual-path current real-time monitoring circuit 2.

[0017] The gate of the second NMOS 115 is connected to the input signal WL1, the source is connected to the output terminal of the first tri-state gate 111 and the upper input terminal of the dual-path current real-time monitoring circuit 2, and the drain is connected to the positive terminal of the second phase-change memory 116.

[0018] The positive terminal of the second phase-change memory 116 is connected to the drain of the second NMOS 115, and the negative terminal is connected to the output terminal of the second tri-state gate 112 and the lower input terminal of the dual-path current real-time monitoring circuit 2.

[0019] Preferably, the dual-path current real-time monitoring circuit 2 includes: a first PMOS 21, a second PMOS 22, a third PMOS 23, a third NMOS 24, a fourth NMOS 25, a fifth NMOS 26, a first inverter 27, and a second inverter 28;

[0020] The source of the first PMOS 21 is connected to the power supply voltage Vdc, the gate of the first PMOS 21 is connected to the gate of the second PMOS 22, and the drain of the first PMOS 21 is connected to the upper output terminal of the memory cell read / write circuit 1.

[0021] The source of the second PMOS 22 is connected to the power supply voltage Vdc, the gate of the second PMOS 22 is connected to the gate of the first PMOS 21 and connected to the upper output terminal of the memory cell read / write circuit 1, and the drain of the second PMOS 22 is connected to the drain of the fourth NMOS 25 and the input terminal of the first inverter (27).

[0022] The source of the third PMOS 23 is connected to the power supply voltage Vdc, the gate of the third PMOS 23 is connected to the upper output terminal of the memory cell read / write circuit 1, and the drain of the third PMOS 23 is connected to the drain of the fifth NMOS 26 and the input terminal of the second inverter 28.

[0023] The source of the second NMOS 24 is connected to ground potential GND, the gate of the third NMOS 24 is connected to the gate of the fourth NMOS 25, and the drain of the third NMOS 24 is connected to the lower output terminal of the memory cell read / write circuit 1.

[0024] The source of the fourth NMOS 25 is connected to ground potential GND, the gate of the fourth NMOS 25 is connected to the gate of the third NMOS 24 and connected to the lower output terminal of the memory cell read / write circuit 1, and the drain of the fourth NMOS 25 is connected to the drain of the second PMOS 22 and the input terminal of the first inverter 27.

[0025] The source of the fifth NMOS 26 is connected to ground potential GND, the gate of the fifth NMOS 26 is connected to the lower output terminal of the memory cell read / write circuit 1, and the drain of the fifth NMOS 26 is connected to the drain of the third PMOS 23 and the input terminal of the second inverter 28.

[0026] The input terminal of the first inverter 27 is connected to the drain of the second PMOS 22 and the drain of the fourth NMOS 25;

[0027] The input terminal of the second inverter 28 is connected to the drain of the third PMOS 23 and the drain of the fifth NMOS 26.

[0028] Preferably, the parallel reference readout detection circuit 3 includes: a sixth NMOS 31, a fourth PMOS 32, a fifth PMOS 33, a seventh NMOS 34, and an inverter circuit 35;

[0029] The source of the fifth NMOS 31 is connected to ground potential GND, and the gate of the sixth NMOS 31 is connected to the read enable signal EN. read The drain of the sixth NMOS 31 is connected to the drain of the fourth PMOS 32, the gate of the fourth PMOS 32, and the gate of the fifth PMOS 33.

[0030] The source of the fourth PMOS 32 is connected to the power supply voltage Vdc, the gate of the fourth PMOS 32 is connected to the drain of the sixth NMOS 31, and the drain of the fourth PMOS 32 is connected to the drain of the sixth NMOS 31.

[0031] The source of the fifth PMOS 33 is connected to the power supply voltage Vdc, the gate of the fifth PMOS 33 is connected to the drain of the sixth NMOS 31, and the drain of the fifth PMOS 33 is connected to the drain of the seventh NMOS 34.

[0032] The source of the seventh NMOS 34 is connected to ground potential GND, the gate of the seventh NMOS 34 is connected to the output terminal of the dual-path current real-time monitoring circuit 2, and the drain of the seventh NMOS 34 is connected to the drain of the fifth PMOS 33 and the input terminal of the inverter circuit 35.

[0033] The input terminal of the inverter circuit 35 is connected to the drain of the fifth PMOS 33 and the drain of the seventh NMOS 34.

[0034] Preferably, this invention proposes a March-PCRAM fault testing algorithm. This algorithm can not only detect common faults such as static single-cell faults, static double-cell faults, dynamic single-cell faults, and dynamic double-cell faults, but also effectively detect special faults of PCRAM.

[0035] The specific process of the March-PCRAM algorithm is as follows:

[0036] {M0↑↓(w0;M1↑(r) ref0 w1 r ref1 M2↓(w1 r) ref1 w0 r ref0 ) k M3↓(r ref0 w1 r ref1 M4↑↓(r) ref1 )};

[0037] Where M0-M4 are the execution steps of the algorithm, ↑ indicates address access in ascending order, ↓ indicates address access in descending order, and ↑↓ indicates address access in either ascending or descending order. w0 indicates writing logical 0 data to the selected memory cell, w1 indicates writing logical 1 data to the selected cell; r0 indicates reading data from the selected cell with a desired value of 0, r1 indicates reading with a desired value of 1; r ref0 and r ref1 For a special read operation used to detect special faults in PCRAM, parameter k specifies the number of iterations for element M2.

[0038] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0039] (1) By using parallel current monitoring of the bit line path and the source line path, and using a mixed-signal structure of current mirror proportional replication and CMOS inverter decision, the current difference is directly mapped to the logic output, so that the key current information during the writing period can be acquired in real time and quickly compared and decided.

[0040] (2) By using a parallel reference reading detection circuit to achieve multi-reference parallel comparison, the critical state of a single decision can be verified twice and the resistance state range can be refined, thereby improving the ability to distinguish between multiple resistance states and intermediate states, shortening the test time and improving the test efficiency.

[0041] (3) The circuit can be verified by model injection and test sequence. It can be shown that the circuit still has stable fault detection under different temperature conditions and different defect intensities, thus providing a circuit implementation scheme with low overhead, easy integration and stronger detection capability for the reliability test of high-density PCRAM array. Attached Figure Description

[0042] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0043] Figure 1 This is an overall structural diagram of the test circuit of the present invention;

[0044] Figure 2 This is the principle of the dual current real-time monitoring circuit of the present invention; wherein, (a) is I BL with I SL Write the current circuit diagram; (b) is the diagram of the four state divisions; (c) is the diagram of the current change during the 1w0 state transition;

[0045] Figure 3 This is a flowchart of the March-PCRAM test algorithm of this invention;

[0046] Figure 4 This is a simulation result diagram of the fault injection of the March-PCRAM test algorithm of this invention;

[0047] Figure 5 This is a diagram showing the injection location of the fault resistor in the RD model of this invention;

[0048] Figure 6 This is the Verilog-A model of the PCRAM of this invention;

[0049] Figure 7 This is a schematic diagram of the injection of fault resistors in the DO model of this invention. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] Please see Figures 1-7 The present invention provides the following technical solution:

[0052] Example 1: Figure 1 The overall structure diagram of the test circuit of the present invention is given, including:

[0053] Storage array read / write circuit 1, dual-path current real-time monitoring circuit 2, and parallel reference read detection circuit 3;

[0054] Preferably, the storage array read-write circuit 1 includes:

[0055] The circuit consists of a first storage array read / write circuit 11, a second storage array read / write circuit 12, a first dual-path current real-time monitoring circuit 13, a second dual-path current real-time monitoring circuit 14, and a first parallel reference read / detection circuit 15.

[0056] The first storage array read / write circuit 11 includes a first tri-state gate 111, a second tri-state gate 112, a first NMOS 113, a first phase-change memory 114, a second NMOS 115, and a second phase-change memory 116;

[0057] The enable terminal of the first tri-state gate 111 is connected to the write enable signal EN. write The input terminal of the first tri-state gate 111 is connected to the input signal IN. BL The output terminal of the first tri-state gate 111 is connected to the source of the first NMOS 113, the source of the second NMOS 115, and the upper input terminal of the dual-path current real-time monitoring circuit 2, respectively.

[0058] The enable terminal of the second tri-state gate 112 is connected to the write enable signal EN. write The input terminal of the second tri-state gate 112 is connected to the input signal IN. SL The output terminal of the second tri-state gate 112 is connected to the negative terminal of the first phase change memory 114, the negative terminal of the second phase change memory 116, and the lower input terminal of the dual-path current real-time monitoring circuit 2.

[0059] The gate of the first NMOS 113 is connected to the input signal WL0, the source is connected to the output terminal of the first tri-state gate 111 and the upper input terminal of the dual-path current real-time monitoring circuit 2, and the drain is connected to the positive terminal of the first phase-change memory 114.

[0060] The positive terminal of the first phase-change memory 114 is connected to the drain of the first NMOS 113, and the negative terminal is connected to the output terminal of the second tri-state gate 112 and the lower input terminal of the dual-path current real-time monitoring circuit 2.

[0061] The gate of the second NMOS 115 is connected to the input signal WL1, the source is connected to the output terminal of the first tri-state gate 111 and the upper input terminal of the dual-path current real-time monitoring circuit 2, and the drain is connected to the positive terminal of the second phase-change memory 116.

[0062] The positive terminal of the second phase-change memory 116 is connected to the drain of the second NMOS 115, and the negative terminal is connected to the output terminal of the second tri-state gate 112 and the lower input terminal of the dual-path current real-time monitoring circuit 2.

[0063] Preferably, the second storage array read / write circuit 12 has the same structure as the first storage array read / write circuit 11;

[0064] The first dual-path current real-time monitoring circuit 13 and the second dual-path current real-time monitoring circuit 14 have the same structure as the dual-path current real-time monitoring circuit 2.

[0065] The first parallel reference read detection circuit 15 has the same structure as the parallel reference read detection circuit 3.

[0066] Preferably, the PCRAM memory cell read / write drive circuit performs data access functions by applying voltage to the memory element during PCRAM read / write operations. The specific operation involves controlling the voltage level of the memory cell to achieve data writing and reading; its operating voltage parameters are shown in Table 1.

[0067]

[0068] Table 1 PCRAM cell read / write operations

[0069] During a READ operation, an appropriate read voltage is applied to the bit line (BL) of the addressed cell while the transfer transistor is turned on by biasing its gate terminal. The low voltage on the BL is used to provide the required read current and ensure that the data stored in the addressed cell is not unintentionally altered.

[0070] The SET operation is used to write a logic "1" to an addressed cell. This process is achieved by applying a high voltage to the BL and simultaneously biasing the word line (WL) to turn on the transfer transistor. A forced high current flows through the memory cell, heating the material to a range above the glass transition temperature but below the melting point of the GST material, thus causing the material to transform into the crystalline phase. For unaddressed cells, the BL, source line (SL), and WL are all grounded to suppress their programming.

[0071] The RESET operation is used to write a logic "0" to the cell. This is achieved by applying a high current to the germanium-antimony-tellurium (GST) alloy layer of the selected cell, heating the material to a temperature above its melting point, and then rapidly cooling it to form an amorphous state. This operation is accomplished by applying a high voltage to BL and simultaneously applying an appropriate voltage to the gate terminal to turn on the transfer transistor. For unaddressed cells, BL, SL, and WL are also kept grounded to avoid interference.

[0072] Preferably, the dual-path current real-time monitoring circuit 2 (DFT Stage 1) includes:

[0073] First PMOS 21, Second PMOS 22, Third PMOS 23, Third NMOS 24, Fourth NMOS 25, Fifth NMOS 26, First Inverter 27, Second Inverter 28;

[0074] The source of the first PMOS 21 is connected to the power supply voltage Vdc, the gate of the first PMOS 21 is connected to the gate of the second PMOS 22, and the drain of the first PMOS 21 is connected to the upper output terminal of the memory cell read / write circuit 1.

[0075] The source of the second PMOS 22 is connected to the power supply voltage Vdc, the gate of the second PMOS 22 is connected to the gate of the first PMOS 21 and connected to the upper output terminal of the memory cell read / write circuit 1, and the drain of the second PMOS 22 is connected to the drain of the fourth NMOS 25 and the input terminal of the first inverter (27).

[0076] The source of the third PMOS 23 is connected to the power supply voltage Vdc, the gate of the third PMOS 23 is connected to the upper output terminal of the memory cell read / write circuit 1, and the drain of the third PMOS 23 is connected to the drain of the fifth NMOS 26 and the input terminal of the second inverter 28.

[0077] The source of the second NMOS 24 is connected to ground potential GND, the gate of the third NMOS 24 is connected to the gate of the fourth NMOS 25, and the drain of the third NMOS 24 is connected to the lower output terminal of the memory cell read / write circuit 1.

[0078] The source of the fourth NMOS 25 is connected to ground potential GND, the gate of the fourth NMOS 25 is connected to the gate of the third NMOS 24 and connected to the lower output terminal of the memory cell read / write circuit 1, and the drain of the fourth NMOS 25 is connected to the drain of the second PMOS 22 and the input terminal of the first inverter 27.

[0079] The source of the fifth NMOS 26 is connected to ground potential GND, the gate of the fifth NMOS 26 is connected to the lower output terminal of the memory cell read / write circuit 1, and the drain of the fifth NMOS 26 is connected to the drain of the third PMOS 23 and the input terminal of the second inverter 28.

[0080] The input terminal of the first inverter 27 is connected to the drain of the second PMOS 22 and the drain of the fourth NMOS 25;

[0081] The input terminal of the second inverter 28 is connected to the drain of the third PMOS 23 and the drain of the fifth NMOS 26.

[0082] Preferably, such as Figure 2 As shown, the dual-path current real-time monitoring circuit employs dual-path dynamic current comparison technology to monitor and analyze two parallel current paths in real time during write operations. The core implementation of dual-path dynamic current comparison relies on the coordinated operation of the current mirror structure and the inverter decision circuit. During write operations, the current flowing through the bit line path and the source line path in the memory cell is introduced into two parallel monitoring branches, respectively. The current is proportionally replicated and amplified by the current mirror, and then the inverter circuit completes the voltage-based and logic-based decision of the current difference.

[0083] The current mirror structure is used to proportionally replicate and transfer the current generated by the memory cell during the writing process. This structure consists of size-controllable MOS transistors, where the gates of the reference transistor and the replica transistor are connected and their sources are at the same potential, thus ensuring that they have the same gate-source bias conditions. The DFT represents the write current difference (|IF) of a defect-free cell. BL -I SL |) A margin is set, which is based on the width-to-length ratio (W / L) of the MOSFET design using the current mirror replication principle. By adjusting the size ratio of the output and input transistors, the current is replicated proportionally, increasing IL. BL and I SL Copy to the DFT circuit to ensure that when I BL Approaching I within a certain range SL At this point, the output of the DFT scheme is stable. In the saturation region, the MOSFET current formula is:

[0084] ;

[0085] Where μ is the carrier mobility, and C ox For the gate oxide capacitance per unit area, V th Let λ be the threshold voltage and λ be the channel length modulation coefficient. For example, the first PMOS (21) and the second PMOS (22) are a set of current mirror structures. When the channel length modulation effect is ignored (λ≈0) and V DS At the same time, the output current I M22 With input current I M21 The ratio is:

[0086] ;

[0087] This means that by adjusting the width-to-length ratio of the output transistor to the input transistor to r, the output current is made to be r times the input current. This ratio was chosen considering the variations in Vdc voltage and temperature, as well as the randomness of the PCRAM. Performing 10,000 Monte Carlo (MC) tests with r=1.2 showed that the output accuracy was greater than 90%.

[0088] The CMOS inverter employs a complementary PMOS and NMOS structure with a power supply voltage of 1.5 V and a ground potential of 0 V. Its input is connected to a comparator node output by a current mirror, used to convert the analog voltage change at this node into a full-swing digital inverted signal. When the input node voltage is below the inverter's toggle threshold, the PMOS transistor is turned on while the NMOS transistor is turned off, pulling the output node up to the power supply voltage and outputting a high level. When the input node voltage is above the toggle threshold, the PMOS transistor is turned off while the NMOS transistor is turned on, pulling the output node down to ground and outputting a low level.

[0089] exist Figure 2 In (a), during the SET operation, the current for writing to the driver flows into the PCRAM cell through BL and then flows out of the cell through SL.

[0090] exist Figure 2 In (b), based on the magnitude of the current, four different cases can be distinguished: in a defect-free circuit, I BL Should be with I SL The currents are identical and all within specifications (Case ①). However, defects such as short circuits or bridging faults can cause one current (Case ②, ③) or both currents (Case ④) to exceed normal limits. The DFT system defines a current difference margin (|I0) for defect-free cells. BL - I SL This margin is determined by the current mirroring factor and the aspect ratio (W / L) of the MOSFET. By adjusting the size ratio of the output transistor to the input transistor, the current can be replicated proportionally, I. BL and I SL All of them are mirrored into the circuit.

[0091] exist Figure 2 In (c), the state transitions during 1w0 operation under Rbr SL-int short-circuit fault conditions are shown. The current I across the 1T1R cell during write-0 operation is also shown. BL and I SL As shown in the figure, when a small defect resistor is injected (Case ④), a significant current imbalance occurs: I BL The threshold margin is exceeded, but the current flowing through the PCRAM is negligible, causing I... SLThe value exceeds the allowable range. At this point, the cell cannot complete the switching and remains in the initial logic '1' state. As the fault resistance increases, the short-circuit current gradually decreases, and the PCRAM's I... SL The value then increases. In this case (Case ②), I SL It remains above the specification value, while ISL reaches the correct value. As the fault resistance continues to increase, its effect gradually becomes negligible, I... BL with I SL They will eventually converge to the correct value (Case ①).

[0092] The dual-path current real-time monitoring circuit Stage1 will monitor the current I. BL and r*I BL I SL and r∗I SL A mirroring process is performed, where r is the width-to-length ratio of the output transistor to the input transistor. By adjusting the value of r, the output current can be made to be r times the input current. The output state (Y1Y0) depends on the current difference. When I... BL Approaching I SL And within the specified range (1 / r∗I) SL BL <r∗I SL When (Y1Y0) is selected, the output (Y1Y0) will be set to "01". If I BL >r∗I SL If I, the output will be "00"; if I BL <1 / r∗I SL If the output is "11", then the output will be "11". Since an output of "01" may indicate a fault-free or critical state, a second verification is required.

[0093] Preferably, the parallel reference readout detection circuit 3 (DFT Stage 2) includes:

[0094] Sixth NMOS 31, Fourth PMOS 32, Fifth PMOS 33, Seventh NMOS 34, Inverter circuit 35;

[0095] The source of the fifth NMOS 31 is connected to ground potential GND, and the gate of the sixth NMOS 31 is connected to the read enable signal EN. read The drain of the sixth NMOS 31 is connected to the drain of the fourth PMOS 32, the gate of the fourth PMOS 32, and the gate of the fifth PMOS 33.

[0096] The source of the fourth PMOS 32 is connected to the power supply voltage Vdc, the gate of the fourth PMOS 32 is connected to the drain of the sixth NMOS 31, and the drain of the fourth PMOS 32 is connected to the drain of the sixth NMOS 31. ​

[0097] The source of the fifth PMOS 33 is connected to the power supply voltage Vdc, the gate of the fifth PMOS 33 is connected to the drain of the sixth NMOS 31, and the drain of the fifth PMOS 33 is connected to the drain of the seventh NMOS 34.

[0098] The source of the seventh NMOS 34 is connected to ground potential GND, the gate of the seventh NMOS 34 is connected to the output terminal of the dual-path current real-time monitoring circuit 2, and the drain of the seventh NMOS 34 is connected to the drain of the fifth PMOS 33 and the input terminal of the inverter circuit 35.

[0099] The input terminal of the inverter circuit 35 is connected to the drain of the fifth PMOS 33 and the drain of the seventh NMOS 34.

[0100] Preferably, the parallel reference readout detection circuit is a PRR DFT circuit, which performs additional verification. The current mirror circuit copies the ISL to four branches, with the reference current I... ref0 -I ref3 Compare the data. During the 1w0 operation, the effective range (I) ref0 SL ref1 This will cause the inverter X3X2X1X0 to output '0001', while other logic combinations correspond to different resistor states.

[0101] Reference current I ref Generated by the NMOS transistor within the PRR DFT circuit. When the read / write circuit is operating, the voltage across the PCRAM is the input signal V. read In logic 0 state, the resistance of the PCRAM is R. HRS In logic 1 state, its resistance is R. LRS The operating resistance states of PCRAM are refined into five types, and the upper boundary resistance values ​​and definition formulas of these resistance states are listed in Table 2 below:

[0102]

[0103] Table 2 Upper Boundary Resistance Values ​​and Definition Formulas for PCRAM Resistive State Division

[0104] Based on the upper boundary resistance value of the PCRAM resistive state, the reference current I generated by the four NMOS transistors in the PRR DFT circuit can be calculated respectively. ref0 I ref1 I ref2 I ref3 The calculation formula is:

[0105] ; ​​

[0106] Similarly, we can obtain I ref1 =V read1 / R ref1 I ref2 =V read2 / R ref2 I ref3 =V read3 / R ref3 .

[0107] Will I ref0 I ref1 I ref2 I ref3 Substituting these values ​​into the formula for calculating the width-to-length ratio (W / L) of an NMOS transistor, the width-to-length ratio of each NMOS transistor in the PRRDFT circuit can be calculated: ;

[0108] Among them, V th It is the threshold voltage of the NMOS transistor, V gs The voltage between the gate and source is µ. n It is electron mobility, C ox This represents the gate oxide capacitance per unit area. This calculation process ensures that the reference current generated by each NMOS transistor precisely matches the state of the PCRAM, enabling accurate fault detection.

[0109] Example 2: March-PCRAM Algorithm:

[0110] like Figure 3 The diagram shows the flowchart of the March-PCRAM testing algorithm. This algorithm can detect not only common faults such as static single-cell faults, static double-cell faults, dynamic single-cell faults, and dynamic double-cell faults, but also special faults of PCRAM. The specific flow of the March-PCRAM algorithm is as follows:

[0111] {M0↑↓(w0;M1↑(r) ref0 w1 r ref1 M2↓(w1 r) ref1 w0 r ref0 ) k M3↓(r ref0 w1 r ref1 M4↑↓(r) ref1 )}.

[0112] Where M0-M4 are the execution steps of the algorithm, ↑ indicates address access in ascending order, ↓ indicates address access in descending order, and ↑↓ indicates address access in either ascending or descending order. w0 indicates writing logical 0 data to the selected memory cell, w1 indicates writing logical 1 data to the selected cell; r0 indicates reading data from the selected cell with a desired value of 0, r1 indicates reading with a desired value of 1; r ref0 and r ref1 For a special read operation used to detect special faults in PCRAM, parameter k specifies the number of iterations for element M2.

[0113] Table 3 summarizes the comparison of fault detection coverage between the March-PCRAM algorithm and previously developed algorithms. As shown in Table 3, the March-PCRAM testing algorithm effectively covers static single-cell faults, static double-cell faults, dynamic single-cell faults, dynamic double-cell faults, and special faults of PCRAM. Using the March-PCRAM testing algorithm, a fault coverage rate of 91.53% for PCRAM was achieved, a significant improvement compared to other testing algorithms, demonstrating higher fault detection capability and coverage.

[0114]

[0115] Table 3 Fault coverage of the March-PCRAM algorithm and previously developed algorithms

[0116] Example 3: Fault Injection:

[0117] Figure 5 This paper illustrates all potential fault locations in a 1T1R PCRAM cell structure, including resistor arrangements to simulate short-circuit, bridging, and open-circuit faults that could adversely affect device functionality. Based on the RD model, a total of 17 different defects were injected into a single PCRAM cell. Only one resistor was injected at a designated fault location each time, with its resistance varying to characterize the severity of the different defects.

[0118] a) The actual cause of the short circuit fault:

[0119] A short-circuit fault refers to an abnormally low-resistance conductive path forming between two nodes that should maintain high-resistance isolation. In the RD model, this is usually represented by a small-value resistor connected in parallel or directly. In the actual PCRAM manufacturing and operation process, short-circuit faults are mainly caused by the following reasons:

[0120] Lithography and etching process defects: In advanced processes, the spacing between word lines (WL), bit lines (BL), and source lines (SL) is constantly decreasing. If lithography misalignment, etching residue, or sidewall damage is not properly controlled, local short circuits can easily occur between adjacent metal lines or contact holes. For example, short circuit defects such as WL and VDD, or BL and GND, often originate from metal residue or over-etching.

[0121] Metal interconnect or via filling defects: During the filling process of metal interconnect layers or vias, if there is excessive metal deposition, void collapse or uneven chemical mechanical polishing (CMP), metal bridges may form between nodes that should not be connected, resulting in low-resistance short circuits.

[0122] Thermal diffusion effect caused by high-temperature writing: PCRAM requires a large current to generate Joule heat during SET / RESET operations, and the local temperature can rise to hundreds of degrees Celsius instantaneously. Repeated thermal cycling may cause metal migration, electrode diffusion, or insulation degradation, thereby creating abnormal conduction paths between internal nodes and power terminals.

[0123] Material aging and electromigration effects: Under long-term working conditions, electromigration may cause metal atoms to move in a directional manner under the action of an electric field, gradually forming low-resistance channels, eventually leading to local short circuits.

[0124] b) The actual cause of bridging failure:

[0125] A bridging fault refers to the formation of an unexpected parallel resistive path between two originally independent signal nodes. Its conductivity is typically weaker than a complete short circuit. In the RD model, it is equivalent to connecting the two nodes with a medium-value resistor. The main causes of bridging faults in actual PCRAM include:

[0126] Insufficient spacing between adjacent metal lines or contact structures: As array density increases, the physical spacing between adjacent WL, BL, SL, or internal nodes continuously decreases. Manufacturing deviations or local process variations may result in insufficient insulation thickness, forming parasitic conductive paths, which manifest as bridging resistance.

[0127] Lateral diffusion of phase change materials or electrodes: Under high-temperature operating conditions, GST materials or electrode metals may undergo lateral diffusion, especially near internal nodes (int), resulting in weak conductive paths between WL-int, BL-int, or SL-int.

[0128] Contamination and impurity introduction: If ionic contamination, particulate residues or impurity doping occur during the manufacturing process, non-ideal conductive channels may be formed between adjacent nodes, resulting in bridging behavior.

[0129] Thermal stress-induced insulation layer cracks: PCRAM repeatedly undergoes high and low temperature cycles, and thermal stress may generate microcracks in the dielectric layer, causing leakage paths between adjacent signal lines, manifesting as bridging faults. Bridging faults often exhibit strong temperature dependence; their equivalent resistance and fault observability differ significantly under low or high temperature conditions. This is one of the important reasons for introducing temperature control testing in this work.

[0130] c) The actual cause of an open fault:

[0131] An open-circuit fault refers to a situation where a current path that should have formed a stable conducting current path is partially or completely blocked. In the RD model, this is usually represented by a large-value series resistor. In PCRAM cells, open-circuit faults are mainly caused by the following factors:

[0132] Poor contact or via: In a 1T1R structure, if the contact hole between the transistor and the PCRAM cell is not fully filled, or if there are voids or interface contamination, the contact resistance will increase significantly, and may even form an almost open circuit state.

[0133] Metal line breakage or narrowing: During the manufacturing process, excessive etching or stress concentration may cause local narrowing or even breakage of the metal line, especially on the source line (SL) or bit line (BL) path, which can easily lead to open circuit defects.

[0134] Phase change material degradation and interface failure: After multiple SET / RESET cycles, GST materials may experience structural degradation or deterioration of the electrode-phase change material interface, resulting in a reduction in effective conduction area and a significant increase in resistance.

[0135] Electromigration-induced void formation: Under high current density conditions, electromigration may form voids in metal interconnects, gradually weakening conductivity and eventually leading to open circuit failure.

[0136] Defect-oriented (DO) model fault injection:

[0137] In the DO model, fault injection is achieved through device-aware testing methods, i.e., adjusting specific electrical parameters in the Verilog-A model; such as... Figure 6 As shown, the model comprises three modules: a PCMR module, a decision module, and a storage module. Table 4 shows that the fault behavior of PCRAM under low temperature, room temperature, and high temperature conditions is simulated by adjusting electrical parameters. The adjustment methods are as follows: Figure 7 As shown.

[0138]

[0139] Table 4. Settings at three different temperatures

[0140] To reproduce the phase transition kinetics and thermoelectric effect, it is necessary to solve the coupled equations of the electrothermal model and the phase transition kinetics model, including the current continuity equation, the heat conduction equation, and the rate equation, the expressions of which are shown in equations (1)-(3):

[0141] (1)

[0142] (2)

[0143] (3)

[0144] Where ρ, Cp, and k represent the density, heat capacity, and thermal conductivity of each material layer, respectively; E and T represent the internal electric field and temperature, respectively. Ac, n and E c These represent the volume fraction of crystallization, the pre-factor, the reaction order, and the height of the crystallization barrier, respectively; k B is the Boltzmann constant. The electrical conductivity of GST during crystallization is defined by formulas (4)-(6):

[0145] (4)

[0146] (5)

[0147] (6)

[0148] in, am and cryst E represents the conductivity of GST in its amorphous and crystalline states, respectively. am E0 represents the potential barrier energy that needs to be overcome during the amorphization process; E0 represents the threshold electric field. 0cryst and 0amor All are constants. The thermal conductivity of GST follows the Wiedermann-Franz law, as shown in equation (7):

[0149] (7)

[0150] Among them, K GST Where K is the thermal conductivity, and K0 is the constant for the phonon-mediated contribution. GST TL stands for the standard Wiedermann-Frantz law, and L is the Lorentz number.

[0151] Preferably, this invention studies the thermal model of PCRAM, significantly improving testing efficiency through coordinated optimization of circuits and algorithms. In terms of modeling, a dual-model simulation platform for defect-oriented and resistance-defect faults was constructed, revealing the temperature dependence and dynamic thermal response mechanism of PCRAM resistance parameters. Experimental results show that adjusting the temperature conditions during PCRAM fault testing can effectively reduce the fault trigger threshold for weak defects. In circuit design, online diagnosis of composite faults in dynamic bit line / source line monitoring was implemented, improving fault detection sensitivity. At the algorithm level, a March-PCRAM testing strategy was proposed, combining temperature gradient control (-40℃~100℃) to optimize fault excitation, shortening detection time, and covering 14 fault types at 17 locations, increasing fault coverage to 91.53%, demonstrating significant advantages compared to traditional methods.

[0152] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A phase-change memory array fault test circuit, characterized in that: The test circuit includes: a storage array read / write circuit (1), a dual-path current real-time monitoring circuit (2), and a parallel reference read / detection circuit (3). The storage array read / write circuit (1) includes a first storage array read / write circuit (11), a second storage array read / write circuit (12), a first dual-path current real-time monitoring circuit (13), a second dual-path current real-time monitoring circuit (14), and a first parallel reference read detection circuit (15). The first storage array read / write circuit (11) includes a first tri-state gate (111), a second tri-state gate (112), a first NMOS (113), a first phase-change memory (114), a second NMOS (115), and a second phase-change memory (116). The second storage array read / write circuit (12) has the same structure as the first storage array read / write circuit (11); The first dual-path current real-time monitoring circuit (13), the second dual-path current real-time monitoring circuit (14) have the same structure as the dual-path current real-time monitoring circuit (2); The first parallel reference read detection circuit (15) has the same structure as the parallel reference read detection circuit (3).

2. The phase-change memory array fault test circuit as described in claim 1, characterized in that, The first storage array read / write circuit (11) includes: a first tri-state gate (111), a second tri-state gate (112), a first NMOS (113), a first phase-change memory (114), a second NMOS (115), and a second phase-change memory (116). The enable terminal of the first tri-state gate (111) is connected to the write enable signal EN. write The input terminal of the first tri-state gate (111) is connected to the input signal IN. BL The output of the first tri-state gate (111) is connected to the source of the first NMOS (113), the source of the second NMOS (115), and the upper input of the dual-path current real-time monitoring circuit (2), respectively. The enable terminal of the second tri-state gate (112) is connected to the write enable signal EN. write The input terminal of the second tri-state gate (112) is connected to the input signal IN. SL The output terminal of the second tri-state gate (112) is connected to the negative terminal of the first phase change memory (114), the negative terminal of the second phase change memory (116), and the lower input terminal of the dual-path current real-time monitoring circuit (2). The gate of the first NMOS (113) is connected to the input signal WL0, the source is connected to the output terminal of the first tri-state gate (111) and the upper input terminal of the dual-path current real-time monitoring circuit (2), and the drain is connected to the positive terminal of the first phase-change memory (114). The positive terminal of the first phase-change memory (114) is connected to the drain of the first NMOS (113), and the negative terminal is connected to the output terminal of the second tri-state gate (112) and the lower input terminal of the dual-path current real-time monitoring circuit (2). The gate of the second NMOS (115) is connected to the input signal WL1, the source is connected to the output terminal of the first tri-state gate (111) and the upper input terminal of the dual-path current real-time monitoring circuit (2), and the drain is connected to the positive terminal of the second phase change memory (116). The positive terminal of the second phase-change memory (116) is connected to the drain of the second NMOS (115), and the negative terminal is connected to the output terminal of the second tri-state gate (112) and the lower input terminal of the dual-path current real-time monitoring circuit (2).

3. The phase-change memory array fault test circuit as described in claim 1, characterized in that, The dual-path current real-time monitoring circuit (2) includes: a first PMOS (21), a second PMOS (22), a third PMOS (23), a third NMOS (24), a fourth NMOS (25), a fifth NMOS (26), a first inverter (27), and a second inverter (28). The source of the first PMOS (21) is connected to the power supply voltage Vdc, the gate of the first PMOS (21) is connected to the gate of the second PMOS (22), and the drain of the first PMOS (21) is connected to the upper output terminal of the memory cell read / write circuit (1). The source of the second PMOS (22) is connected to the power supply voltage Vdc, the gate of the second PMOS (22) is connected to the gate of the first PMOS (21) and connected to the upper output terminal of the memory cell read / write circuit (1), and the drain of the second PMOS (22) is connected to the drain of the fourth NMOS (25) and the input terminal of the first inverter (27). The source of the third PMOS (23) is connected to the power supply voltage Vdc, the gate of the third PMOS (23) is connected to the upper output terminal of the memory cell read / write circuit (1), and the drain of the third PMOS (23) is connected to the drain of the fifth NMOS (26) and the input terminal of the second inverter (28). The source of the second NMOS (24) is connected to ground potential GND, the gate of the third NMOS (24) is connected to the gate of the fourth NMOS (25), and the drain of the third NMOS (24) is connected to the lower output terminal of the memory cell read / write circuit (1). The source of the fourth NMOS (25) is connected to ground potential GND, the gate of the fourth NMOS (25) is connected to the gate of the third NMOS (24) and connected to the lower output terminal of the memory cell read / write circuit (1), and the drain of the fourth NMOS (25) is connected to the drain of the second PMOS (22) and the input terminal of the first inverter (27). The source of the fifth NMOS (26) is connected to ground potential GND, the gate of the fifth NMOS (26) is connected to the lower output terminal of the memory cell read / write circuit (1), and the drain of the fifth NMOS (26) is connected to the drain of the third PMOS (23) and the input terminal of the second inverter (28). The input terminal of the first inverter (27) is connected to the drain of the second PMOS (22) and the drain of the fourth NMOS (25); The input terminal of the second inverter (28) is connected to the drain of the third PMOS (23) and the drain of the fifth NMOS (26).

4. The phase-change memory array fault test circuit as described in claim 1, characterized in that, The parallel reference readout detection circuit (3) includes: a sixth NMOS (31), a fourth PMOS (32), a fifth PMOS (33), a seventh NMOS (34), and an inverter circuit (35). The source of the fifth NMOS (31) is connected to ground potential GND, and the gate of the sixth NMOS (31) is connected to the read enable signal EN. read The drain of the sixth NMOS (31) is connected to the drain of the fourth PMOS (32), the gate of the fourth PMOS (32), and the gate of the fifth PMOS (33); The source of the fourth PMOS (32) is connected to the power supply voltage Vdc, the gate of the fourth PMOS (32) is connected to the drain of the sixth NMOS (31), and the drain of the fourth PMOS (32) is connected to the drain of the sixth NMOS (31). The source of the fifth PMOS (33) is connected to the power supply voltage Vdc, the gate of the fifth PMOS (33) is connected to the drain of the sixth NMOS (31), and the drain of the fifth PMOS (33) is connected to the drain of the seventh NMOS (34). The source of the seventh NMOS (34) is connected to ground potential GND, the gate of the seventh NMOS (34) is connected to the output terminal of the dual-path current real-time monitoring circuit (2), and the drain of the seventh NMOS (34) is connected to the drain of the fifth PMOS (33) and the input terminal of the inverter circuit (35). The input terminal of the inverter circuit (35) is connected to the drain of the fifth PMOS (33) and the drain of the seventh NMOS (34).

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