Phase change memory array fault test circuit

By designing a phase-change memory array fault test circuit and a March-PCRAM fault test algorithm, the problem of insufficient detection capability of traditional test circuits at the nanoscale is solved, realizing efficient and low-overhead fault detection of PCRAM devices, and improving detection coverage and test efficiency.

CN122090910APending Publication Date: 2026-05-26NANJING UNIV OF POSTS & TELECOMM +1
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Patent Information

Application Number
CN202610196413.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-02-11
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

Traditional static fault test circuits are insufficient in detecting thermally sensitive defects and transient faults in PCRAM devices at the nanoscale, making it difficult to meet the requirements of efficient and low-overhead array-level testing. Furthermore, they cannot accurately distinguish the five states of PCRAM, resulting in many faults not being detected in a timely manner.

Method used

A phase-change memory array fault test circuit was designed, including a memory array read/write circuit, a dual-path current real-time monitoring circuit, and a parallel reference read detection circuit. Combined with the March-PCRAM fault test algorithm, the circuit achieves accurate detection of static and dynamic faults in PCRAM through dual-path current monitoring and parallel reference read detection.

Benefits of technology

It achieves efficient and low-overhead fault detection for PCRAM devices, improves fault detection coverage, accurately distinguishes between multi-resistance states and intermediate states, shortens test time, and improves test efficiency and reliability.

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Abstract

The invention relates to the technical field of phase change memory testing, in particular to a phase change memory array fault testing circuit which comprises a storage unit read-write circuit, a double-path current real-time monitoring circuit and a parallel reference read detection circuit. Wherein the storage unit read-write circuit is connected with the 1T1R phase change storage unit, the double-path current real-time monitoring circuit is connected with a bit line path and a source line path, synchronous sampling and dynamic comparison are carried out on bit internal line current and source internal line current in the write-in operation period, and corresponding judgment signals are output; and the parallel reference reading detection circuit is connected with the output end of the double-path current real-time monitoring circuit, copies the detected current to a plurality of branches and compares the detected current with the multi-stage reference current in parallel. According to the phase change memory array fault test circuit provided by the invention, online current monitoring and rapid logic judgment can be realized in an array level test process, and the capability of detecting resistance type defects such as short circuit, bridging and open circuit and composite anomalies caused by the resistance type defects is improved.
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