Semiconductor test structure and method of testing the same

Abstract

The application discloses a semiconductor testing structure and a testing method thereof. The application forms a polysilicon connecting structure on an active region, forms a side wall around the polysilicon connecting structure, and through corresponding metal interconnection structure and testing pad, the polysilicon connecting structure can simultaneously detect the residual of metal silicide on the side wall, the continuity problem of the polysilicon and the forming quality problem of the metal silicide. Since the polysilicon connecting structure is located on the active region, the metal silicide residual on the side wall around the polysilicon connecting structure can be detected simultaneously. Since the polysilicon connecting structure has a larger covering area, the process is more sensitive, and the problems in the process can be better captured.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor test structure and test method for detecting metal silicide residues and polysilicon continuity. Background Technology

[0002] In semiconductor manufacturing, metal silicide formation is widely used to reduce contact resistance. The formation process involves depositing a metal (nickel, titanium, cobalt, etc.) on the wafer surface, followed by rapid thermal annealing. Under appropriate process parameters, the metal reacts only with monocrystalline silicon and polycrystalline silicon, not with silicides such as silicon dioxide or silicon nitride. Therefore, metal silicides are only formed on the exposed monocrystalline silicon substrate and the surface of the polycrystalline silicon gate, and not on the sidewalls (spacers). However, under inappropriate process parameters, metal silicides may accumulate on the sidewalls. After thermal annealing, a metal removal process is performed to remove unreacted excess metal. At this stage, some metal or metal silicide residue may remain on the sidewalls and cannot be completely removed. If metal or metal silicide residue remains on the sidewalls, it can cause a short circuit between the gate and the active region, affecting the circuit. However, there are currently very few technologies available for detecting residual metal silicides on sidewalls.

[0003] Figure 1 This is a cross-sectional view of the test structure for residual metal silicides in the prior art. (Example:) Figure 1 As shown, the test structure includes: an active region (AA) 11 formed on a substrate (Sub) 10, a gate structure 12 formed on the active region 11, a sidewall (spacer) 13 formed on the sidewall of the gate structure 12, and a metal silicide 14 formed on the surfaces of the active region 11 and the gate structure 12. The metal silicide 14 is connected to the corresponding pads PAD 11 to PAD 13 via metal lines 19. The gate structure 12 includes a polysilicon gate 121 and a gate oxide layer 122 located between the polysilicon gate 121 and the active region 11. In the field of semiconductor technology, the region on a wafer where an active device is fabricated is called the active region.

[0004] Specifically, the metal silicide formed on the surface of the active region 11 is connected to the pads PAD12-PAD13 through the metal lines 19, and the metal silicide 14 formed on the surface of the gate structure 12 is connected to the pad PAD11 through the metal line 19. During testing, if the current value between the pad PAD11 and the pad PAD12 is greater than 0 when a voltage is applied between the two pads, it indicates that there is metal silicide residue on the sidewall 13 on the left side of the gate structure 12 (the left and right directions are defined according to the user's front view drawing). At this time, the metal silicide on the surface of the gate structure 12, the metal silicide residue on the left sidewall 13, and the metal silicide on the surface of the active region 11 form a current path, so that the current value between the two pads is greater than 0. By applying a voltage between the pad PAD11 and the pad PAD13, if the current value between the two pads is greater than 0, it indicates that there is metal silicide residue on the sidewall 13 on the right side of the gate structure 12. Conversely, if the current value between the two pads involved in the test is equal to 0, it indicates that there is no metal silicide residue on the sidewall between the two pads.

[0005] Figure 2 is a top view of a prior art metal silicide residue test structure. The metal silicide residue test structure includes a gate structure 12, a metal silicide 14 formed on the surface of the gate structure 12, a metal silicide formed on the surface of the active region 11, a metal line 19, and a pad PAD11-PAD13. Figure 2 As can be seen, in fact, the left, right, front, and back (the left, right, front, and back directions are defined according to the user's front view drawing) of the gate structure 12 all have sidewalls 13, and metal silicide residue may exist on the sidewalls of these parts. However, the prior art metal silicide residue test structure as shown in Figure 1 can only detect whether there is metal silicide residue on the left and right sidewalls of the gate structure 12, and cannot detect whether there is metal silicide residue on the front and back sidewalls. In addition, the prior art metal silicide residue test structure is not sensitive to the process, and cannot effectively capture problems in the process. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a semiconductor test structure and a test method thereof, which can effectively detect whether there is metal silicide residue on the sidewalls around the gate, and can also detect the polysilicon continuity of the gate.

[0007] To solve the above problems, an embodiment of the present application provides a semiconductor test structure, comprising: a substrate; an active region formed on the substrate; a polysilicon connection structure formed on the active region, the polysilicon connection structure comprising a plurality of polysilicon structures extending along a first direction and spaced along a second direction, and two adjacent polysilicon structures along the second direction being connected by a polysilicon interconnection; a side wall formed on the active region and covering all sidewalls of the polysilicon connection structure; a metal silicide layer, the metal silicide layer comprising a first metal silicide covering the active region and a second metal silicide covering the polysilicon connection structure; a metal interconnection structure group, the metal interconnection structure group comprising a first metal interconnection structure connected to the first metal silicide and a second metal interconnection structure connected to the second metal silicide; and a test pad group, the test pad group comprising a first pad connected to the first metal interconnection structure and a second pad connected to the second metal interconnection structure.

[0008] In some embodiments, the metal interconnection structure group further comprises a third metal interconnection structure, the second metal interconnection structure being connected to the second metal silicide covering the first polysilicon structure of the head of the polysilicon connection structure or an extension of the first polysilicon structure, and the third metal interconnection structure being connected to the second metal silicide covering the last polysilicon structure of the tail of the polysilicon connection structure or an extension of the last polysilicon structure; the test pad group further comprises a third pad connected to the third metal interconnection structure; and wherein by applying a test voltage on the second pad, a first current on the first pad is detected to determine whether there is metal silicide residue on the side wall, and a third current on the third pad is detected to detect the polysilicon continuity of the polysilicon connection structure and the formation quality of the metal silicide layer.

[0009] To solve the above problems, an embodiment of the present application further provides a testing method of a semiconductor testing structure, comprising: providing a semiconductor testing structure, the semiconductor testing structure comprising: a substrate, an active region, a polysilicon connection structure, a side wall, a metal silicide layer, a metal interconnection structure group and a testing pad group; the active region is formed on the substrate, the polysilicon connection structure is formed on the active region, the polysilicon connection structure comprises a plurality of polysilicon structures extending along a first direction and spaced along a second direction, in the second direction, two adjacent polysilicon structures are connected by a polysilicon interconnection, the side wall is formed on the active region and covers all the side walls of the polysilicon connection structure, the metal silicide layer comprises a first metal silicide covering the active region and a second metal silicide covering the polysilicon connection structure, the metal interconnection structure group comprises a first metal interconnection structure connected with the first metal silicide and a second metal interconnection structure connected with the second metal silicide, and the testing pad group comprises a first pad connected with the first metal interconnection structure and a second pad connected with the second metal interconnection structure; applying a testing voltage on the second pad; detecting a first current on the first pad, if the first current is greater than 0, it is determined that there is metal silicide residue on the side wall.

[0010] In some embodiments, when the metal interconnection structure group further comprises a third metal interconnection structure, the second metal interconnection structure is connected with the second metal silicide covering the polysilicon structure at the head of the polysilicon connection structure, and the third metal interconnection structure is connected with the second metal silicide covering the polysilicon structure at the tail of the polysilicon connection structure; the testing pad group further comprises a third pad connected with the third metal interconnection structure; the method further comprises: detecting a third current on the third pad, if the third current is equal to 0, it is determined that the polysilicon continuity of the polysilicon connection structure is damaged, and if the third current is out of a preset current value range, it is determined that the forming quality of the metal silicide layer has a problem.

[0011] The above technical solution can simultaneously detect the metal silicide residue on the side wall, the polysilicon continuity problem and the forming quality problem of the metal silicide by forming the polysilicon connection structure on the active region and the side wall around the polysilicon connection structure, and through the corresponding metal interconnection structure and testing pad. Since the polysilicon connection structure is entirely located on the active region, the metal silicide residue on the side wall around the polysilicon connection structure can be simultaneously detected. At the same time, since the polysilicon connection structure has a larger coverage area, it is more sensitive to the process, and problems occurring in the process can be better captured. BRIEF DESCRIPTION OF DRAWINGS

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a cross-sectional view of the test structure for metal silicide residues in the prior art;

[0014] Figure 2 This is a top view schematic diagram of the existing metal silicide residue testing structure;

[0015] Figure 3 This is a top view schematic diagram of a semiconductor test structure provided in an embodiment of the present invention;

[0016] Figure 4 This is a cross-sectional view of a semiconductor test structure provided in an embodiment of the present invention;

[0017] Figure 5 This is a top view schematic diagram of a semiconductor test structure provided in another embodiment of the present invention;

[0018] Figure 6 This is a schematic diagram illustrating the steps of a test method for a semiconductor test structure provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Please refer to the following: Figures 3-4 ,in, Figure 3 This is a top view schematic diagram of a semiconductor test structure provided in an embodiment of the present invention. Figure 4 This is a cross-sectional view of a semiconductor test structure provided in an embodiment of the present invention. For ease of illustration, Figure 3 The metal silicide layer is not shown. For ease of explanation, in the following embodiments, the first direction is the X-axis direction in the Cartesian coordinate system, the second direction is the Y-axis direction in the Cartesian coordinate system, and the third direction is the Z-axis direction in the Cartesian coordinate system.

[0021] like Figures 3-4 As shown, the semiconductor test structure described in this embodiment includes: a substrate 30, an active region 31, a polysilicon interconnect structure 32, a sidewall 33, a metal silicide layer 34, a metal interconnect structure group 35, and a test pad group 36.

[0022] Specifically, the active region 31 is formed on the substrate 30. The substrate 30 can include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like; the substrate 30 can also be a laminated structure, such as a silicon / germanium silicon laminated structure, and the like. In this embodiment, the substrate 30 is taken as a silicon substrate for example. In this embodiment, the substrate 30 is provided with a shallow trench isolation (STI) structure 309, and the active region 31 is defined between two adjacent shallow trench isolation structures 309 to isolate the active region 31 from other devices. The shallow trench isolation structure 309 includes, but is not limited to, an oxide isolation structure or a composite isolation structure of an oxide layer and a nitride. In this embodiment, the active region 31 is a single-crystal silicon active region. Because the single-crystal silicon on the active region 31 is exposed, it will react with metal (any one of nickel, titanium, cobalt, and the like) to form a large piece of metal silicide.

[0023] Specifically, the polysilicon connection structure 32 is formed on the active region 31, and the polysilicon connection structure 32 includes a plurality of polysilicon structures 321 extending along a first direction X and spaced apart along a second direction Y, and adjacent two polysilicon structures 321 along the second direction Y are interconnected by a polysilicon 329. In this embodiment, the first direction X is perpendicular to the second direction Y, and in other embodiments, the first direction X can also have an included angle with the second direction Y. In this embodiment, adjacent two polysilicon structures 321 along the second direction Y are interconnected by a polysilicon 329 at a same end. The test structure provided in this embodiment is that the polysilicon connection structure 32 is entirely located on the active region 31, so that the metal silicide residues on the side walls around the polysilicon connection structure 32 can be detected at the same time. At the same time, because the polysilicon connection structure 32 has a larger coverage area, it is more sensitive to the process, and can better capture problems occurring in the process.

[0024] In the embodiment, the polysilicon connection structure 32 is a continuous serpentine polysilicon connection structure. Specifically, in the second direction Y, the head of a current polysilicon structure 321 is connected to the tail of a previous polysilicon structure 321 through polysilicon 329, and the tail of the current polysilicon structure 321 is connected to the tail of a next polysilicon structure 321 through polysilicon 329, so that all the polysilicon structures 321 form a continuous serpentine polysilicon connection structure. The total length of the serpentine polysilicon connection structure in the figure is only for illustration. Since the polysilicon connection structure 32 is exposed, it will react with metal (any one of nickel, titanium, cobalt, etc.) to form metal silicide. Since the polysilicon connection structure 32 is a continuous serpentine polysilicon connection structure, the coverage area is larger, and therefore it is more sensitive to the process, and can better capture problems occurring in the process.

[0025] In the embodiment, the width W of the polysilicon structure 321 and the spacing S between two adjacent polysilicon structures 321 adopt the minimum value in the design rule (Design Rule), so that the formed polysilicon connection structure 32 can be used for effective testing of whether there is metal silicide residue on the side wall and the continuity of the polysilicon.

[0026] In the embodiment, the polysilicon structure 321 includes a polysilicon layer 3211 and an oxide layer 3212 between the polysilicon layer 321 and the active region 31. Specifically, the oxide layer 3212 can be grown on the surface of the substrate 30, and the polysilicon is deposited to form the polysilicon structure 321 by using processes such as photolithography, etching, and ion implantation.

[0027] In some embodiments, the substrate 30 includes a test area 301 and a device area (not shown), the semiconductor test structure is formed on the test area 301 of the substrate 30, and the gate structure is formed on the device area, which is prepared by the same preparation process as the polysilicon connection structure. That is, the polysilicon connection structure simulates the gate structure for effective testing of whether there is metal silicide residue on the side wall.

[0028] Specifically, the side wall 33 is formed on the active region 31 and covers all the side walls of the polysilicon connection structure 32. That is, the polysilicon connection structure 32 is provided with a side wall around it, so as to fully simulate the actual gate structure (such as Figure 2As shown, the side wall 13 exists on the left, right, front and back of the actual gate structure 12. In this embodiment, the material of the side wall 13 can be silicon nitride (SiN). Under proper process parameters, the metal will not react with silicide such as silicon nitride, and thus no metal silicide will be generated on the side wall. By testing whether there is metal silicide residue on the side wall, it can be detected whether the process parameters are proper, so as to optimize the preparation process of the actual gate structure.

[0029] Specifically, the metal silicide layer 34 includes a first metal silicide 341 covering the active region 31, and a second metal silicide 342 covering the polysilicon connection structure 32. That is, the exposed single crystal silicon on the active region 31 will react with the metal (any one of nickel, titanium, cobalt, etc.) to generate a large piece of metal silicide, and the exposed polysilicon of the polysilicon connection structure 32 will also react with the metal (any one of nickel, titanium, cobalt, etc.) to generate metal silicide.

[0030] Specifically, the metal interconnection structure group 35 includes a first metal interconnection structure 351 connected with the first metal silicide 341, and a second metal interconnection structure 352 connected with the second metal silicide 342. Specifically, each metal interconnection structure of the metal interconnection structure group 35 can be prepared by opening a via hole on the insulating medium layer 37 covering the active region 31 and the polysilicon connection structure 32, the via hole corresponding to the active region 31 and the polysilicon connection structure 32, and filling the metal in the via hole to form a contact plug. Through each metal interconnection structure, the active region or the polysilicon can be in contact with the corresponding pad of the test pad group. The metal filled in the contact plug can be tungsten, copper, aluminum or molybdenum. That is, the material of the metal interconnection structure group 35 can be tungsten, copper, aluminum or molybdenum. The metal interconnection structure is a commonly used connection structure in the preparation of existing semiconductor devices, which will not be described in detail here, and the preparation method thereof can be known by referring to the corresponding content.

[0031] Specifically, the test pad set 36 includes a first pad 361 connected to the first metal interconnection structure 351, and a second pad 362 connected to the second metal interconnection structure 352. The pads can be metal (e.g., aluminum) sheets. The pads of the test pad set 36 can be formed by patterning the same metal layer formed on the insulating dielectric layer 37. During testing, a test voltage is applied to the second pad 362, and a first current on the first pad 361 is detected. If the first current measured on the first pad 361 is greater than 0, then there is metal silicide residue on any of the sidewalls of the polysilicon connection structure 32. In this case, the metal silicide on the polysilicon connection structure 32, the metal silicide residue on the sidewalls 33, and the metal silicide on the active region 31 form a current path. If the first current measured on the first pad 361 is equal to 0, then there is no metal silicide residue on the sidewalls 33 in each direction of the polysilicon connection structure 32.

[0032] In the embodiment, the metal interconnection structure group 35 further comprises a third metal interconnection structure 353, and the test pad group 36 further comprises a third pad 363. The second metal interconnection structure 352 is connected to the second metal silicide 342 covering the polysilicon structure 321 at the head of the polysilicon connection structure 32, and the third metal interconnection structure 353 is connected to the second metal silicide 342 covering the polysilicon structure 321 at the tail of the polysilicon connection structure 32; the third pad 363 is connected to the third metal interconnection structure 353. By arranging the metal interconnection structure and the corresponding pad on the second metal silicide 342 covering the polysilicon structure 321 at the head and tail of the polysilicon connection structure 32, the polysilicon continuity of the polysilicon connection structure 32 can be tested, i.e. whether the polysilicon continuity is damaged or not; and the formation quality of the metal silicide layer 34 can be tested. During the test, a test voltage is applied on the second pad 362, and the third current on the third pad 363 is detected; if the third current on the third pad 363 is equal to 0, it is determined that the polysilicon continuity of the polysilicon connection structure 32 is damaged, for example, the polysilicon etching process is problematic, and the polysilicon continuity is damaged; if the third current on the third pad 363 is not equal to 0, it is determined that the polysilicon continuity of the polysilicon connection structure is not damaged. In addition, the third current on the third pad 363 should have a certain range, i.e. the resistance value of the polysilicon connection structure 32 should have a certain range (for example, a preset current value range); if the current value of the third current exceeds the preset current value range, it is proved that the formation quality of the metal silicide is problematic, and the resistance requirement is not met. That is, the test structure provided in the embodiment can simultaneously test the residue of the metal silicide on the sidewall, the polysilicon continuity problem and the formation quality problem of the metal silicide.

[0033] Preferably, in the embodiment, the metal interconnection structure group 35 comprises two first metal interconnection structures 351, which are distributed on both sides of the polysilicon connection structure 32 along the first direction X; and the two first metal interconnection structures 351 are simultaneously connected to the first pad 361. The design of the multi-metal interconnection structure can reduce the contact resistance and ensure the connection stability.

[0034] Preferably, in the embodiment, the first metal interconnection structure 351 comprises a plurality of first contact plugs 3511, each of which is connected to the first metal silicide 341 covering the active region 31 on both sides of the polysilicon connection structure 32 along the second direction Y and between two adjacent polysilicon structures 321. The design of multiple contact plugs can reduce contact resistance and ensure connection stability, avoiding the case of single contact plug disconnection.

[0035] Preferably, in the embodiment, the second metal interconnection structure 352 comprises a plurality of second contact plugs 3521, each of which is connected to the second metal silicide 342 covering the polysilicon structure 321 at the head.

[0036] Preferably, in the embodiment, the third metal interconnection structure 353 comprises a plurality of third contact plugs 3531, each of which is connected to the second metal silicide 342 covering the polysilicon structure 321 at the tail.

[0037] Please refer to Figure 5 , which is a top view of a semiconductor test structure provided by another embodiment of the present application. In the embodiment, Figure 3 The difference between the embodiments shown in the figures is that, in the embodiment, the polysilicon structure 321 at the head of the polysilicon connection structure 32 extends outwardly with a first extension 591, and the polysilicon structure 321 at the tail extends outwardly with a second extension 592, both of which are polysilicon; the second metal interconnection structure 352 is connected to the second metal silicide 342 covering the first extension 591, and the third metal interconnection structure 353 is connected to the second metal silicide 342 covering the second extension 592. The second pad 362 is still connected to the second metal interconnection structure 352, and the third pad 363 is still connected to the third metal interconnection structure 353.

[0038] As an optional embodiment, when the metal interconnection structure group 35 comprises two first metal interconnection structures 351 distributed on both sides of the polysilicon connection structure 32 along the first direction X, the first metal interconnection structures 351 on both sides can be connected to the first pad 361.

[0039] Based on the same inventive concept, the present application further provides a testing method of the semiconductor testing structure, which can be used to test the residue of metal silicide on the side wall, the polysilicon continuity problem and the formation quality problem of the metal silicide. The testing method can use the semiconductor testing structure of the above-mentioned embodiments of the present application.

[0040] Please refer to Figure 6 which is a step schematic diagram of the testing method of the semiconductor testing structure provided by an embodiment of the present application. As shown in Figure 6 , in the embodiment, the method comprises the following steps: S1, providing a semiconductor testing structure of the present application; S2, applying a testing voltage on the second pad; and S3, detecting the first current on the first pad, if the first current is greater than 0, it is determined that there is metal silicide residue on the side wall.

[0041] In some embodiments, when the metal interconnection structure group 35 further comprises a third metal interconnection structure 353, the second metal interconnection structure 352 is connected with the second metal silicide 342 covering the polysilicon structure 321 at the head of the polysilicon connection structure 32, the third metal interconnection structure 353 is connected with the second metal silicide 342 covering the polysilicon structure 321 at the tail of the polysilicon connection structure 32, and the testing pad group 36 further comprises a third pad 363 connected with the third metal interconnection structure 353; the method further comprises: S4, detecting the third current on the third pad, if the third current is equal to 0, it is determined that the polysilicon continuity of the polysilicon connection structure is damaged, and if the third current is out of the preset current value range, it is determined that the formation quality problem of the metal silicide layer occurs.

[0042] The semiconductor testing structure and its working mode can refer to the corresponding description of the semiconductor testing structure shown in Figures 3-5 , which will not be described here in detail.

[0043] According to the above, it can be seen that the semiconductor testing structure and its testing method provided by the embodiment can simultaneously detect the residue of metal silicide on the side wall, the polysilicon continuity problem and the formation quality problem of the metal silicide by forming the polysilicon connection structure on the active area and forming the side wall around the polysilicon connection structure, and through the corresponding metal interconnection structure and testing pad. Since the polysilicon connection structure is entirely located on the active area, the metal silicide residue on the side wall around the polysilicon connection structure can be simultaneously detected. At the same time, since the polysilicon connection structure has a larger coverage area, it is more sensitive to the process, and can better capture the problems occurring in the process.

[0044] It should be noted that the terms "comprise" and "have" and their conjugates, as used in the specification and claims of the present application, are intended to encompass the presence of stated features, structures, components, elements, or objects, but do not preclude the presence or addition of one or more other features, structures, components, elements, or objects. The terms "first," "second," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another, unless otherwise indicated by context. The use of the terms "a" and "an" and "the" and "said" and "at least one" and "one or more" to refer to an element or object also is taken to cover "one or more" unless otherwise indicated by context. The term "based on" can be taken to mean "based at least in part on," that is, not necessarily based exclusively on the matter following the term. In addition, the embodiments and features discussed above can be combined with each other, as much as is physically possible. Furthermore, in the following description of various embodiments, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without these specific details. In other instances, well-known components or methods are not described in detail in order to avoid obscuring aspects of the present application.

[0045] The above description is merely illustrative of the preferred embodiments of the present application and various modifications and changes can be suggested by those skilled in the art without departing from the spirit and scope of the present application.

Claims

1. A semiconductor test structure, characterized by, The application comprises: a substrate; an active region formed on the substrate; a polysilicon connection structure formed on the active region, the polysilicon connection structure comprising a plurality of polysilicon structures extending along a first direction and spaced along a second direction, and adjacent two of the polysilicon structures being connected by a polysilicon interconnection in the second direction, wherein the first direction and the second direction are both parallel to a surface of the active region facing away from the substrate, and the first direction is perpendicular to the second direction or has an included angle with the second direction; a sidewall formed on the active region and covering all sidewalls of the polysilicon connection structure; a metal silicide layer comprising a first metal silicide covering the active region and a second metal silicide covering the polysilicon connection structure; a metal interconnection structure group comprising a first metal interconnection structure connected with the first metal silicide and a second metal interconnection structure connected with the second metal silicide; and a test pad group comprising a first pad connected with the first metal interconnection structure and a second pad connected with the second metal interconnection structure.

2. The semiconductor test structure of claim 1, wherein, The polysilicon connection structure is a continuous serpentine polysilicon connection structure.

3. The semiconductor test structure of claim 1, wherein, The polysilicon structure comprises a polysilicon layer and an oxide layer between the polysilicon layer and the active region.

4. The semiconductor test structure of claim 1, wherein, The metal interconnection structure group further comprises a third metal interconnection structure connected with the second metal silicide covering the polysilicon structure at a head of the polysilicon connection structure or an extension of the polysilicon structure, and a fourth metal interconnection structure connected with the second metal silicide covering the polysilicon structure at a tail of the polysilicon connection structure or an extension of the polysilicon structure; the test pad group further comprises a third pad connected with the third metal interconnection structure and a fourth pad connected with the fourth metal interconnection structure; and by applying a test voltage on the second pad, a first current on the first pad is detected to determine whether there is metal silicide residue on the sidewall, and a third current on the third pad is detected to detect polysilicon continuity of the polysilicon connection structure and formation quality of the metal silicide layer.

5. The semiconductor test structure of claim 4, wherein, The second metal interconnection structure comprises a plurality of second contact plugs, each of which is connected to the second metal silicide covering the polysilicon structure at the head; and the third metal interconnection structure comprises a plurality of third contact plugs, each of which is connected to the second metal silicide covering the polysilicon structure at the tail.

6. The semiconductor test structure of claim 1, wherein, The first metal interconnection structure comprises a plurality of first contact plugs, each of which is connected to the first metal silicide covering the active region between two adjacent polysilicon structures and the first metal silicide covering both sides of the polysilicon connection structure along the second direction.

7. The semiconductor test structure of claim 1, wherein, The metal interconnection structure group comprises two first metal interconnection structures, which are distributed on both sides of the polysilicon connection structure along the first direction and are connected to the first pad simultaneously.

8. The semiconductor test structure of claim 1, wherein, The substrate comprises a testing area and a device area, the semiconductor testing structure is formed on the testing area of the substrate, the gate structure is formed on the device area, the gate structure and the polysilicon connection structure are prepared by using the same preparation process, and the width of the polysilicon structure and the interval between two adjacent polysilicon structures adopt the minimum value in the design rule.

9. A method of testing a semiconductor test structure, characterized by, The semiconductor testing structure comprises: A semiconductor testing structure is provided, which adopts the semiconductor testing structure according to any one of claims 1-8; A testing voltage is applied to the second pad; The first current on the first pad is detected, and if the first current is greater than 0, it is determined that there is metal silicide residue on the side wall.

10. The method of claim 9, wherein, When the metal interconnection structure group further comprises a third metal interconnection structure, the second metal interconnection structure is connected to the second metal silicide covering the polysilicon structure at the head of the polysilicon connection structure, and the third metal interconnection structure is connected to the second metal silicide covering the polysilicon structure at the tail of the polysilicon connection structure; when the testing pad group further comprises a third pad connected to the third metal interconnection structure; the method further comprises: detecting the third current on the third pad, if the third current is equal to 0, it is determined that the polysilicon continuity of the polysilicon connection structure is damaged, and if the third current is out of the preset current value range, it is determined that the formation quality of the metal silicide layer has a problem.

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