A Clock Phase Synchronization Method Based on Xilinx FPGA

Abstract

The present invention discloses a clock phase synchronization method based on Xilinx FPGA. First, a serial communication link is established between distributed nodes through the GT high-speed serial transceiver in the Xilinx FPGA. Then, one of the nodes is used as the sending node and the other as the receiving node, and test data is continuously transmitted between the nodes. The clock phase difference between TX_USRCLK and RX_USRCLK is measured through the GT high-speed serial transceiver. Then, the DDMTD technology is used to measure the clock phase difference between the local system clock and TX_USRCLK in the sending node, and the clock phase difference between the local system clock and RX_USRCLK in the receiving node. Finally, according to the measured phase difference information above, the local system clock is adjusted to phase synchronization through the hybrid clock management module.

Description

Technical Field

[0001] The present invention belongs to the technical field of clock phase synchronization. More specifically, it relates to a clock phase synchronization method based on Xilinx FPGA. Background Art

[0002] With the further development of distributed systems, there are higher requirements for the real-time performance and reliability of data communication links in engineering applications. High-precision clock synchronization enables each node in the data communication link to operate according to a determined time, and the synchronization accuracy of the clock phase directly affects the clock operation accuracy between nodes.

[0003] The phase synchronization method is mainly divided into two parts: phase difference measurement and phase adjustment. Common phase difference measurements mainly use analog circuits, such as high-precision TDCs. In the phase difference measurement at the nanosecond level, the design difficulty and cost of analog circuits are both relatively high; for phase adjustment, a phase-locked loop chip is often used for fine phase adjustment, which requires additional analog circuits. Therefore, if the clock phase synchronization method can be digitalized without adding additional analog circuits, the design difficulty and cost can be greatly reduced.

[0004] Xilinx FPGA supports the use of four GT (Gigabit Transceiver) high-speed serial transceivers based on SERDES (Serializer / Deserializer) technology for high-speed serial communication application scenarios. Its basic structure is divided into a PMA (Physical Medium Attachment sublayer) analog circuit and a PCS (Physical Coding Sublayer) digital logic part, including data clock recovery, serial-to-parallel conversion, encoders (8b / 10b, 64b / 66b, 128b / 130b), phase adjustment FIFO, and polarity control, etc., to achieve high-speed serial communication transceiver functions. For the receiving part of GT, each time power is applied to establish a communication link, due to the uncertainty of the connection establishment time, the recovered clock will generate a random phase relative to the transmitted clock, and by manually aligning the data through the RXSLIDE interface of GT, this random phase can be measured. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a clock phase synchronization method based on Xilinx FPGA, which uses digital double-mixer phase discrimination to measure the clock phase difference between two communication nodes, and then adjusts the system clock phase through a hybrid clock manager module, thereby achieving clock phase synchronization.

[0006] To achieve the above invention purpose, a clock phase synchronization method based on Xilinx FPGA of the present invention is characterized by including the following steps:

[0007] (1) In a distributed system, connect two communication nodes that require local system clock phase synchronization through the GT high-speed serial transceivers of their respective Xilinx FPGAs;

[0008] (2) Designate one communication node as the sending node and the other as the receiving node;

[0009] (3) Input a reference clock to the GT high-speed serial transceivers in the sending node and the receiving node. The frequency of the reference clock is the same as that of the local system clock, so that the GT high-speed serial transceiver in the sending node outputs a transmission clock TX_USRCLK with the same frequency as the local system clock, and the GT high-speed serial transceiver in the receiving node outputs a reception clock RX_USRCLK with the same frequency as the local system clock;

[0010] (4) Set the data alignment mode of the two GT high-speed serial transceivers to manual alignment mode;

[0011] (5) The Xilinx FPGA of the sending node continuously sends a fixed test data to the Xilinx FPGA of the receiving node;

[0012] (6) In the receiving node, the RXSLIDE interface of the GT high-speed serial transceiver shifts the received data until the received data is consistent with the fixed test data. Record the number of shifts N at this time, and then calculate the phase difference T between the transmission clock TX_USRCLK and the reception clock RX_USRCLK 0 :

[0013]

[0014] where v linerate represents the line rate;

[0015] (7) In the sending node, test the phase difference T between the transmission clock TX_USRCLK and the local system clock through a digital double-mixer phase discriminator module 1 ;

[0016] (7.1) Generate a sampling clock CLKC through a hybrid clock management module. The relationship between the frequency of the sampling clock and the frequency of the local system clock is:

[0017]

[0018] where f CLKC is the frequency of the sampling clock, and f CLKA is the frequency of the local system clock;

[0019] (7.2) Use the local system clock as the input of D flip-flop 1, and the sampling clock CLKC as the clock of D flip-flop 1, so as to obtain the output signal Q1 of D flip-flop 1; use the transmission clock TX_USRCLK as the input of D flip-flop 2, and the sampling clock CLKC as the clock of D flip-flop 2, so as to obtain the output signal Q2 of D flip-flop 2;

[0020] (7.3) Detect the time difference ΔT between the rising edges of Q1 and Q2 through a counter. Start counting when the rising edge of Q1 is detected, and end counting when the rising edge of Q2 is detected to obtain the count value N of the counter 0 , and then calculate the phase difference T between the local system clock and the transmission clock TX_USRCLK 1 ;

[0021]

[0022] where T counter represents the working clock period of the counter;

[0023] (8) In the receiving node, the digital double mixing phase discriminator module tests the phase difference T between the received clock RX_USRCLK and the local system clock according to step (7) 2 ;

[0024] (9) Clock phase synchronization;

[0025] (9.1) In the transmitting node, the local system clock is adjusted in phase through the hybrid clock management module according to the phase difference T 1 to make the phase of the local system clock synchronized with the transmission clock TX_USRCLK;

[0026] (9.1.1) Set the input signals of the hybrid clock management module on three input ports: the clock signal PSCLK, the enable signal PSEN, and the adjustment direction signal PSINCDEC; one output signal is denoted as PSDONE;

[0027] (9.1.2) Set the adjustment direction signal PSINCDEC to a low level, keep the enable signal PSEN for one PSCLK clock cycle, and at this time the phase of the local system clock will move one step T VCO / 56, T VCO is the period of the voltage-controlled oscillator VCO of the hybrid clock management module, and wait for the output signal PSINCDEC of the hybrid clock management module to be at a high level to complete a phase adjustment;

[0028] (9.1.3) Repeat step (9.1.2) N 1 times,

[0029] (9.2) In the receiving node, the local system clock adjusts the phase of the module through hybrid clock management according to the phase differences T 0 and T 2 so that the phase of the local system clock is synchronized with the phase of the transmission clock TX_USRCLK;

[0030] (9.2.1) Calculate the number of times N 2 ;

[0031]

[0032] (9.2.2) Set the hybrid clock management module according to step (9.1.1), and then repeat N 2 times according to step (9.1.2);

[0033] At this point, the local system clocks of both the receiving node and the sending node are synchronized with the phase of the transmission clock TX_USRCLK, thus completing the phase synchronization of the local clocks of the two communication nodes.

[0034] The object of the present invention is achieved as follows:

[0035] The clock phase synchronization method based on Xilinx FPGA of the present invention first establishes a serial communication link between distributed nodes through the GT high-speed serial transceiver in the Xilinx FPGA, then takes one of the nodes as the sending node and the other as the receiving node, continuously transmits test data between the nodes, measures the clock phase difference between TX_USRCLK and RX_USRCLK through the GT high-speed serial transceiver, then uses the DDMTD technology to measure the clock phase difference between the local system clock and TX_USRCLK in the sending node, measures the clock phase difference between the local system clock and RX_USRCLK in the receiving node, and finally adjusts the local system clock to phase synchronization according to the measured phase difference information through the hybrid clock management module.

[0036] Meanwhile, the clock phase synchronization method based on Xilinx FPGA of the present invention also has the following beneficial effects:

[0037] (1) The clock phase synchronization method of the present invention, when used in combination with PTP clock synchronization protocols such as IEEE 1588, can improve the clock synchronization accuracy from the original nanosecond level to the sub-nanosecond level, improving the clock synchronization accuracy;

[0038] (2) The present invention is fully digitally implemented. The measurement of the phase difference uses the DDMTD technology, which is more flexible than the method of using a TDC to measure the phase difference, reducing the cost and design difficulty. The phase adjustment is implemented using the MMCM module in the Xilinx FPGA, which has better stability and performance compared to an external phase-locked loop chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a flowchart of the clock phase synchronization method based on Xilinx FPGA of the present invention;

[0040] Figure 2 is a data timing diagram of the manual alignment method;

[0041] Figure 3 is a block diagram of the DDMTD phase difference measurement;

[0042] Figure 4 is a timing diagram of the input and output signals of the hybrid clock management module;

[0043] Figure 5 is a block diagram of the clock phase synchronization system structure;

[0044] Figure 6 is a synchronization accuracy test diagram. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] The following describes the specific embodiments of the present invention with reference to the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be particularly noted that in the following description, when the detailed description of known functions and designs may obscure the main content of the present invention, these descriptions will be omitted here.

[0046] Embodiment

[0047] Figure 1 is a flowchart of the clock phase synchronization method based on Xilinx FPGA of the present invention.

[0048] In this embodiment, as Figure 1 shown, a clock phase synchronization method based on Xilinx FPGA of the present invention includes the following steps:

[0049] S1. In a distributed system, each communication node is equipped with a Xilinx FPGA. The Xilinx FPGA is built-in with a GT high-speed serial transceiver. When two communication nodes that need local system clock phase synchronization can connect the GT high-speed serial transceivers through a connection medium (such as an optical fiber);

[0050] S2. One communication node is used as the sending node, and the other communication node is used as the receiving node;

[0051] S3. Input the reference clock for the GT high-speed serial transceivers in the sending node and the receiving node. The frequency of the reference clock is the same as that of the local system clock, so that the GT high-speed serial transceiver in the sending node outputs a transmission clock TX_USRCLK with the same frequency as the local system clock, and the GT high-speed serial transceiver in the receiving node outputs a reception clock RX_USRCLK with the same frequency as the local system clock;

[0052] S4. Set the data alignment mode of the two GT high-speed serial transceivers to the manual alignment mode;

[0053] S5. The Xilinx FPGA in the sending node continuously sends a fixed test data 0xBCBCBCBC01020304 to the Xilinx FPGA in the receiving node;

[0054] S6. Due to the influence of the random phase of the recovered clock in the receiving node, the received data is not consistent with the fixed test data. Therefore, in the receiving node, the RXSLIDE interface of the GT high-speed serial transceiver shifts the received data until the received data is consistent with the fixed test data. Record the number of shifts N at this time, and then calculate the phase difference T between the transmission clock TX_USRCLK and the reception clock RX_USRCLK 0 :

[0055]

[0056] where v linerate represents the line rate;

[0057] In this embodiment, as Figure 2 shown, every time the RXSLIDE signal is pulled high, it lasts for at least two clock cycles at a time. At this time, the recovered data is shifted once. When the recovered data is the fixed test data, record the number of times the RXSLIDE signal is pulled high at this time. Each time represents the duration of 1-bit serial data for the phase difference.

[0058] S7. In the sending node, test the phase difference T between the transmission clock TX_USRCLK and the local system clock through the digital double-mixer phase detector module 1 ;

[0059] S7.1. Generate a sampling clock CLKC through the hybrid clock management module. The relationship between the frequency of the sampling clock and the frequency of the local system clock is:

[0060]

[0061] where f CLKC is the frequency of the sampling clock, f CLKAis the frequency of the local system clock, and the value of N is taken as 100;

[0062] S7.2. As shown in Figure 3 , the local system clock is used as the input of D flip-flop 1, and the sampling clock CLKC is used as the clock of D flip-flop 1, so as to obtain the output signal Q1 of D flip-flop 1; the transmission clock TX_USRCLK is used as the input of D flip-flop 2, and the sampling clock CLKC is used as the clock of D flip-flop 2, so as to obtain the output signal Q2 of D flip-flop 2;

[0063] S7.3. Detect the time difference ΔT between the rising edges of Q1 and Q2 through a counter. Start counting when the rising edge of Q1 is detected, and end counting when the rising edge of Q2 is detected to obtain the count value N of the counter 0 , and then calculate the phase difference T between the local system clock and the transmission clock TX_USRCLK 1 ;

[0064]

[0065] where T counter represents the working clock period of the counter;

[0066] S8. In the receiving node, the digital double-mixer phase discriminator module tests the phase difference T between the received clock RX_USRCLK and the local system clock according to step S7 2 ;

[0067] S9. Clock phase synchronization;

[0068] S9.1. In the transmitting node, the local system clock adjusts the phase through the hybrid clock management module according to the phase difference T 1 so that the phase of the local system clock is synchronized with the phase of the transmission clock TX_USRCLK;

[0069] S9.1.1. Set the input signals of the hybrid clock management module on three input ports: the clock signal PSCLK, the enable signal PSEN, and the adjustment direction signal PSINCDEC; one output signal is denoted as PSDONE;

[0070] S9.1.2. Set the adjustment direction signal PSINCDEC to a low level, and keep the enable signal PSEN for one PSCLK clock cycle. As shown in Figure 4 , every time PSEN is pulled high for one cycle, at this time the phase of the local system clock will move one step T VCO / 56, T VCO is the period of the voltage-controlled oscillator VCO of the hybrid clock management module. Wait for the output signal PSINCDEC of the hybrid clock management module to be at a high level to complete one phase adjustment;

[0071] S9.1.3. Repeat step S9.1.2 N 1 times

[0072] S9.2. In the receiving node, the local system clock adjusts the phase of the module through hybrid clock management according to the phase differences T 0 and T 2 so that the phase of the local system clock is synchronized with the phase of the transmission clock TX_USRCLK;

[0073] S9.2.1. Calculate the number of times N 2 ;

[0074]

[0075] S9.2.2. Set the hybrid clock management module according to step S9.1.1, and then repeat N 2 times according to step S9.1.2;

[0076] So far, the local system clocks of the receiving node and the sending node are both synchronized with the phase of the transmission clock TX_USRCLK, so that the local clocks of the two communication nodes complete phase synchronization.

[0077] In this embodiment, the system block diagram of the system synchronization clock phase difference adjustment is as Figure 5 shown. In the communication node that continuously sends fixed test data, the phase difference between the reference clock to be synchronized and the transmission clock of the GT serial transceiver is measured by the DDMTD phase difference measurement module. The MMCM module adjusts the reference clock according to this phase difference until it is synchronized with the transmission clock phase, and uses the output clock as the system synchronization clock. In the receiving end of the fixed test data, the MMCM module adjusts the reference clock to be in the same phase as the receiving clock according to the phase difference measurement result of the DDMTD module. Since there is a phase difference with random phase between the receiving clock and the transmission clock, the MMCM module further adjusts the reference clock to be synchronized with the transmission clock phase according to the measurement result of the random phase, and then outputs a synchronization clock that is synchronized with the system clock phase of the sending end.

[0078] Between communication nodes with a system clock frequency of 156.25 MHz, use the method proposed by the present invention to complete the phase synchronization of the system clock, output the local system clocks of the two nodes, connect them to the same high-bandwidth oscilloscope for phase difference measurement, and the synchronization accuracy test is as Figure 6 shown. The phase difference between the rising edges of the two node clocks is 800 ps.

[0079] Although the above description of the illustrative embodiments of the present invention has been given for the convenience of those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concept of the present invention are within the scope of protection.

Claims

1. A clock phase synchronization method based on Xilinx FPGA, characterized in that, it includes the following steps: (1). In a distributed system, connect two communication nodes that require local system clock phase synchronization through the GT high-speed serial transceivers of the Xilinx FPGAs they each carry; (2). Designate one communication node as the sending node and the other communication node as the receiving node; (3). Input a reference clock to the GT high-speed serial transceivers in the sending node and the receiving node. The frequency of the reference clock is the same as the frequency of the local system clock, so that the GT high-speed serial transceiver in the sending node outputs a transmission clock TX_USRCLK with the same frequency as the local system clock, and the GT high-speed serial transceiver in the receiving node outputs a reception clock RX_USRCLK with the same frequency as the local system clock; (4). Set the data alignment method of the two GT high-speed serial transceivers to the manual alignment method; (5). The Xilinx FPGA of the sending node continuously sends a fixed test data to the Xilinx FPGA of the receiving node; (6) In the receiving node, the RXSLIDE interface of the GT high-speed serial transceiver shifts the received data until the received data is consistent with the fixed test data, records the number of shifts N at this time, and then calculates the phase difference T between the transmit clock TX_USRCLK and the receive clock RX_USRCLK 0 : Among them, v linerate represents the line rate; (7) In the sending node, the phase difference T between the sending clock TX_USRCLK and the local system clock is tested by the digital double mixing phase discriminator module 1 ; (7.1). Generate a sampling clock CLKC through a mixed clock management module. The relationship between the frequency of the sampling clock and the frequency of the local system clock is: where f CLKC is the frequency of the sampling clock, and f CLKA is the frequency of the local system clock; (7.2). Use the local system clock as the input of D flip-flop 1, and the sampling clock CLKC as the clock of D flip-flop 1, so as to obtain the output signal Q1 of D flip-flop 1; Use the transmission clock TX_USRCLK as the input of D flip-flop 2, and the sampling clock CLKC as the clock of D flip-flop 2, so as to obtain the output signal Q2 of D flip-flop 2; (7.3) Detect the time difference ΔT between the rising edges of Q1 and Q2 through a counter. Start counting when the rising edge of Q1 is detected, and end counting when the rising edge of Q2 is detected to obtain the count value N of the counter. 0 Then calculate the phase difference T between the local system clock and the transmission clock TX_USRCLK. 1 ; Among them, T counter represents the working clock cycle of the counter; (8) In the receiving node, the digital double-mixer phase detector module measures the phase difference T between the received clock RX_USRCLK and the local system clock according to step (7). 2 ; (9). Clock phase synchronization; (9.1) In the sending node, the local system clock adjusts its phase according to the phase difference T 1 through the hybrid clock management module to synchronize the phase of the local system clock with the sending clock TX_USRCLK; (9.1.1). Set the input signals of the mixed clock management module on three input ports: the clock signal PSCLK, the enable signal PSEN, and the adjustment direction signal PSINCDEC; One output signal is denoted as PSDONE; (9.1.2) Setting the adjustment direction signal PSINCDEC to a low level will keep the enable signal PSEN for one PSCLK clock cycle. At this time, the phase of the local system clock will shift by one step T VCO / 56, where T VCO is the period of the voltage-controlled oscillator VCO of the hybrid clock management module. Wait for the output signal PSDONE of the hybrid clock management module to be high to complete a phase adjustment; (9.1.3), repeat step (9.1.2) N 1 times, (9.2) In the receiving node, the local system clock adjusts the phase of the module through hybrid clock management according to the phase differences T 0 and T 2 so that the phase of the local system clock is synchronized with the phase of the transmission clock TX_USRCLK; (9.2.1), Number of calculations N 2 ; (9.2.2) Set the hybrid clock management module according to step (9.1.1), and then repeat N 2 times according to step (9.1.2); Thus, the local system clocks of the receiving node and the sending node are both phase-synchronized with the transmission clock TX_USRCLK, so that the local clocks of the two communication nodes complete phase synchronization.

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