Low-power data interaction method applied to gateway device and gateway device

Abstract

The present application provides a low-power data interaction method and gateway device for use in a gateway device. The low-power data interaction method includes: if a data packet is received from a network management platform and sent to a terminal, storing the data packet and returning a response message to the network management platform indicating that the terminal has received the data packet; based on the time of the last heartbeat signal received from the terminal and the heartbeat cycle between the terminal and the terminal, determining the next heartbeat time point at which the heartbeat signal sent by the terminal is received next; and if the heartbeat signal sent by the terminal is received at the next heartbeat time point, sending the data packet to the terminal. This can reduce the misjudgment rate of the network management platform of the Internet of Things.

Description

Technical Field

[0001] The present invention relates to the technical field of Internet of Things, and in particular to a low-power data interaction method applied to a gateway device and the gateway device. Background Art

[0002] As an application device at the IoT technology transmission layer, the underlying logic of an IoT gateway is to connect various sensor devices and electrical signals to the gateway via wired interfaces (I2C, USB, RS232, Ethernet, etc.) or wireless interfaces (Wi-Fi, Bluetooth, ZigBee, OpenThread, etc.). This allows for data and information collection, which is then converted into useful information through the gateway's core components and uploaded to the internet. The gateway can also integrate with the intelligent processing layer to achieve automatic device control. Currently, some IoT network management platforms have a high rate of misjudgment. Summary of the Invention

[0003] The present application provides a low-power data interaction method and a gateway device applied to a gateway device, which can reduce the misjudgment rate of the network management platform of the Internet of Things.

[0004] The present application provides a low-power data interaction method applied to a gateway device, wherein the low-power data interaction method is applied to the gateway device and includes:

[0005] If a data packet sent by the network management platform to the terminal is received, the data packet is stored, and a response message indicating that the terminal has received the data packet is returned to the network management platform;

[0006] Determining a next heartbeat time point at which a heartbeat signal sent by the terminal is received next time based on the time at which the heartbeat signal sent by the terminal was last received and the heartbeat cycle between the terminal and the terminal; and

[0007] If a heartbeat signal sent by the terminal is received at the next heartbeat time point, the data packet is sent to the terminal.

[0008] Furthermore, after storing the data packet, the low-power data interaction method further includes:

[0009] If the heartbeat signal sent by the terminal is not received at the next heartbeat time point, it is determined that the terminal is abnormal, and a message indicating that the terminal is abnormal is sent to the network management platform.

[0010] Furthermore, after determining that the terminal is abnormal, the data packet is discarded.

[0011] Furthermore, the gateway device includes a first communication chip and a second communication chip based on a first communication protocol, and the computing capability of the first communication chip is greater than the computing capability of the second communication chip;

[0012] The sending the data packet to the terminal includes:

[0013] The first communication chip decapsulates the data packet based on other layers except the physical layer and the MAC control sublayer in the first communication protocol stack to obtain a data frame, and sends the data frame to the second communication chip;

[0014] The second communication chip decapsulates the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and sends the decapsulated signal to the terminal.

[0015] Furthermore, decapsulating the data packet to obtain a data frame, and sending the data frame to the second communication chip includes:

[0016] The first communication chip encapsulates the data frame based on an inter-chip communication protocol, and sends the encapsulated data frame to the second communication chip;

[0017] The decapsulating the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack includes:

[0018] The second communication chip decapsulates the received data frame based on the inter-chip communication protocol, and decapsulates the decapsulated data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack.

[0019] Furthermore, the inter-chip communication protocol includes the spinel protocol.

[0020] Furthermore, the gateway device is an Internet of Things gateway device; and / or

[0021] The first communication protocol is an IP-based wireless network protocol.

[0022] Furthermore, the first communication protocol is the OpenThread protocol.

[0023] The present application provides a gateway device, comprising a first communication chip and a second communication chip based on a first communication protocol, wherein the computing capability of the first communication chip is greater than the computing capability of the second communication chip, wherein:

[0024] The first communication chip is used to store the data packet sent to the terminal by the network management platform if it receives the data packet, and return a response message to the network management platform indicating that the terminal has received the data packet; and based on the time when the heartbeat signal sent by the terminal was last received and the heartbeat cycle between the terminal, determine the next heartbeat time point when the heartbeat signal sent by the terminal is received next time; and at the next heartbeat time point, when the heartbeat signal sent by the terminal is received, send the data packet to the terminal through the second communication chip.

[0025] Furthermore, the first communication chip is specifically configured to decapsulate the data packet based on other layers in the first communication protocol stack except the physical layer and the MAC control sublayer to obtain a data frame, and send the data frame to the second communication chip;

[0026] The second communication chip is specifically configured to decapsulate the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and send the decapsulated signal to the terminal.

[0027] In some embodiments of the present application, after receiving the data packet sent by the network management platform to the terminal, the gateway device will store the data packet and return a response message to the network management platform indicating that the terminal has received the data packet. In this way, the network management platform can receive the response message in time after sending the data packet to the terminal, thereby reducing the probability that the network management platform will misjudge the terminal as abnormal due to failure to receive the response message in time; on the other hand, the gateway device stores the data packet and sends the data packet to the terminal after receiving the heartbeat signal sent by the terminal, so that the terminal does not need to remain awake, which is beneficial to reducing the power consumption of the terminal connected to the gateway device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a circuit block diagram of a gateway circuit provided by an embodiment of the present application;

[0029] Figure 2 yes Figure 1 A circuit diagram of a power supply circuit included in the gateway circuit;

[0030] Figure 3 is a schematic diagram of a gateway device provided by an embodiment of the present application;

[0031] Figure 4 is a flow chart of a communication method provided by an embodiment of the present application;

[0032] Figure 5 This is a software architecture block diagram of a gateway device provided by an embodiment of the present application;

[0033] Figure 6 is a flow chart of a communication method provided by an embodiment of the present application;

[0034] Figure 7 This is a flowchart of a low-power data interaction method provided by an embodiment of the present application;

[0035] Figure 8 It is a schematic diagram of the structure of a gateway device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0036] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with one or more embodiments of this specification. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of one or more embodiments of this specification, as detailed in the appended claims.

[0037] It should be noted that in other embodiments, the steps of the corresponding method are not necessarily performed in the order shown and described in this specification. In some other embodiments, the method may include more or fewer steps than those described in this specification. In addition, a single step described in this specification may be broken down into multiple steps for description in other embodiments, and multiple steps described in this specification may be combined into a single step for description in other embodiments.

[0038] Figure 1 1 is a circuit block diagram of a gateway circuit 100 provided in one embodiment of the present application.

[0039] See also Figure 1The gateway circuit 100 includes a communication circuit 13, a first communication chip 11, and a second communication chip 12. The communication circuit 13 includes a first communication circuit 130 for information exchange with the target network, and a second communication circuit 134 for information exchange with the terminal. The first communication chip 11 includes a first port UART1 and a first processing unit 110 connected to the first port UART1. The first processing unit 110 is connected to the first communication circuit 130. The second communication chip 12 includes a second port UART2 and a second processing unit 120 connected to the second port UART2. The second processing unit 120 is connected to the second communication circuit 134. The first port UART1 is connected to the second port UART2. The computing power of the first processing unit 110 is greater than that of the second processing unit 120, that is, the computing power of the first communication chip 11 is greater than that of the second communication chip 12. The signal received by the second communication circuit 134 from the terminal is processed by the second processing unit 120 and the first processing unit 110, and then sent to the target network through the first communication circuit 130.

[0040] In some embodiments, the target network may be the Internet.

[0041] In some embodiments, the first processing unit 110 and the second processing unit 120 include resources such as a CPU and memory, enabling the compilation of an embedded operating system within the first processing unit 110 and the second processing unit 120, and further enabling the integration of a communication protocol stack within the embedded operating system. For details, please refer to the subsequent related description and are not further elaborated here.

[0042] In some embodiments, the second communication chip 12 is a chip based on the first communication protocol. Specifically, the first communication protocol may be an IP-based wireless network protocol. In this embodiment, the first communication protocol is the OpenThread protocol. The second communication chip 12 can establish a wireless connection with terminals on the OpenThread network and exchange information with these terminals.

[0043] In some embodiments, the first port UART1 and the second port UART2 are serial interfaces. The first communication chip 11 and the first communication chip 12 communicate based on the inter-chip communication protocol. Specifically, the inter-chip communication protocol includes the Spinel protocol. The signal received by the second communication circuit 134 from the terminal is partially processed by the second operation processing unit 120. The second communication chip 12 sends the signal processed by the second operation processing unit 120 to the first communication chip 11 based on the Spinel protocol, and the first operation processing unit 110 further processes the signal and then sends it to the target network through the first communication circuit 130. Among them, the first operation processing unit 110 and the second operation processing unit 120 process the signal based on the integrated communication protocol stack. For details, please refer to the subsequent related description, which will not be repeated here.

[0044] In some embodiments of the present application, the gateway circuit 100 includes two communication chips, both of which include an operation processing unit, and the computing power of the first communication chip 11 is greater than the computing power of the second communication chip 12. This allows the second communication circuit 134 to receive a signal from the terminal without the need for the second communication chip 12 to complete all processing of the signal. The second communication chip 12 can complete part of the processing of the signal and then send it to the first communication chip 11 with better computing power for further processing, thereby improving the performance of the gateway circuit 100, such as throughput performance and the number of connectable terminals.

[0045] In some embodiments, the first communication circuit 130 includes multiple different communication sub-circuits 131, 132, and 133, and the multiple different communication sub-circuits 131, 132, and 133 are respectively connected to the first operation processing unit 110. The signal received from the terminal by the second communication circuit 134 is processed by the second operation processing unit 120 and the first operation processing unit 110, and then sent to the target network through one of the communication sub-circuits 131, 132, and 133.

[0046] In some embodiments, the communication subcircuits 131, 132, 133 include at least one of a WiFi communication subcircuit 131, a 4G communication subcircuit 132, and an Ethernet communication subcircuit 133. In this embodiment, the communication subcircuits 131, 132, 133 include a WiFi communication subcircuit 131, a 4G communication subcircuit 132, and an Ethernet communication subcircuit 133.

[0047] In some embodiments, the first communication chip 11 includes an IPEX interface, and the WiFi communication subcircuit 131 includes a WiFi radio frequency circuit 1311 and a WiFi antenna 1312. The WiFi radio frequency circuit 1311 is built into the first communication chip 11 and connected to the first processing unit 110. The WiFi antenna 1312 is disposed outside the first communication chip 11, and the WiFi radio frequency circuit 1311 and the WiFi antenna 1312 are connected via the IPEX interface. Signals output by the first processing unit 110 can be transmitted to the target network via the WiFi radio frequency circuit 1311 and the WiFi antenna 1312.

[0048] In some embodiments, the first communication chip 11 includes a USB interface, and the 4G communication sub-circuit 132 is disposed outside the first communication chip 11 and includes a 4G antenna 1322 and a 4G radio frequency circuit 1321. The 4G antenna 1322 is connected to the 4G radio frequency circuit 1321, and the 4G radio frequency circuit 1321 is connected to the first processing unit 110 via the USB interface. The signal output by the first processing unit 110 can be sent to the target network via the 4G radio frequency circuit 1321 and the 4G antenna 1322.

[0049] In some embodiments, the first communication chip 11 includes a WAN interface and a LAN interface. The Ethernet communication subcircuit 133 is built into the first communication chip 11 and is connected to the WAN interface, the LAN interface, and the first processing unit 110, respectively. The WAN interface is used to connect to a target network, such as the Internet. Signals output by the first processing unit 110 can be sent to the target network via the Ethernet communication subcircuit 133 and the WAN interface.

[0050] In some embodiments, the second communication circuit 134 includes an OpenThread antenna 1342 and an OpenThread radio frequency circuit 1341. The OpenThread antenna 1342 is disposed outside the second communication chip 12, and the OpenThread radio frequency circuit 1341 is built into the second communication chip 12. The OpenThread antenna 1342 is connected to the OpenThread radio frequency circuit 1341, and the OpenThread radio frequency circuit 1341 is connected to the second processing unit 120. The second communication chip 12 can receive terminal signals of the OpenThread network through the OpenThread antenna 1342 and the OpenThread radio frequency circuit 1341.

[0051] In some embodiments, the WiFi radio frequency circuit 1311 , the 4G radio frequency circuit 1321 , and the OpenThread radio frequency circuit 1341 include baseband circuits and radio frequency circuits for processing wireless signals.

[0052] In some embodiments, the first communication chip 11 is an MTK system-on-chip, and the second communication chip 12 is an nRF system-on-chip. In the subsequent description of this application, the MTK system-on-chip and the nRF system-on-chip are used as examples for illustration.

[0053] In some embodiments, the gateway circuit 100 includes a power supply circuit 17 , which is respectively connected to the communication circuit 13 , the first communication chip 11 , and the second communication chip 12 for supplying power to the communication circuit 13 , the first communication chip 11 , and the second communication chip 12 .

[0054] Figure 2 yes Figure 1 1 is a circuit diagram of the power supply circuit 17 included in the gateway circuit 100.

[0055] The power supply circuit 17 includes a power input terminal 1701, a power output terminal 1702, a switching circuit 171, a voltage regulating circuit 172 and a power supply terminal 1724. The switching circuit 171 is connected between the power input terminal 1701 and the power output terminal 1702, and the voltage regulating circuit 172 is connected between the power output terminal 1702 and the power supply terminal 1724. The power input terminal 1701 is used to connect the power supply, and the switching circuit 171 is used to control the on and off between the power input terminal 1701 and the power output terminal 1702. When the power input terminal 1701 and the power output terminal 1702 are connected, the voltage regulating circuit 172 converts the voltage output by the power supply into a power supply voltage to power the communication circuit 13, the first communication chip 11 and the second communication chip 12.

[0056] Furthermore, the switch circuit 171 includes a controller 1711, a transistor switch Q1, a triode switch Q2, a control switch S1, a voltage terminal 1703, a first diode D1, a second diode D2, a first voltage-dividing resistor R5, a second voltage-dividing resistor R6, a third voltage-dividing resistor R2, a fourth voltage-dividing resistor R1, and a fifth voltage-dividing resistor R4, wherein:

[0057] The source and drain of the transistor switch Q1 are connected between the power input terminal 1701 and the power output terminal 1702. The gate of the transistor switch Q1 is grounded through the control switch S1 and the transistor switch Q2 respectively. The anode of the first diode D1 is connected to the power input terminal 1701 and the gate of the transistor switch Q1. The cathode of the first diode D1 is grounded through the control switch S1. The voltage terminal 1703 is connected to the power supply terminal 1724. The first voltage divider resistor R5 and the second voltage divider resistor R6 are connected in series between the voltage terminal 1703 and the ground. 5 is connected between the voltage terminal 1703 and the second voltage-dividing resistor R6. The anode of the second diode D2 is connected between the voltage terminal 1703 and the first voltage-dividing resistor R5. The cathode of the second diode D2 is grounded via the control switch S1. The controller 1711 includes a control input terminal POWER_KEY_IN and a control output terminal POWER_ON. The control input terminal POWER_KEY_IN is connected between the first voltage-dividing resistor R5 and the second voltage-dividing resistor R6. The control output terminal POWER_ON is connected to the base of the transistor switch Q2. The third voltage-dividing resistor R2 and the fourth voltage-dividing resistor R1 are connected in series between the power input terminal 1701 and ground. The anode of the first diode D1 and the gate of the transistor switch Q1 are connected between the third voltage-dividing resistor R2 and the fourth voltage-dividing resistor R1. The fifth voltage-dividing resistor R4 is connected in series between the voltage terminal 1703 and the first voltage-dividing resistor R5. The anode of the second diode D2 is connected between the first voltage-dividing resistor R5 and the fifth voltage-dividing resistor R4.

[0058] In this embodiment, the voltage regulation circuit 172 includes a first voltage regulation circuit 1721, a second voltage regulation circuit 1722, and a third voltage regulation circuit 1723. The voltage input from the power input terminal 1701 is 12V. The first voltage regulation circuit 1721 is connected to the power output terminal 1702, and the second voltage regulation circuit 1722 and the third voltage regulation circuit 1723 are respectively connected to the output terminal of the first voltage regulation circuit 1721. When the power input terminal 1701 and the power output terminal 1702 are connected, the first voltage regulation circuit 1721 converts the 12V voltage to 5V; the second voltage regulation circuit 1722 converts the 5V voltage to 3.3V and outputs it through the corresponding power supply terminal 1724; and the third voltage regulation circuit 1723 converts the 5V voltage to 3.6V and outputs it through the corresponding power supply terminal 1724. In this way, power is supplied to the communication circuit 13, the first communication chip 11, and the second communication chip 12, which have different power supply requirements.

[0059] Here, the working principle of the power supply circuit 17 is described by taking the voltage terminal 1703 connected to the power supply terminal 1724 of the second voltage regulating circuit 1722 as an example. Assume that the transistor switch Q1 is a P-type transistor and the transistor Q2 is an NPN-type transistor.

[0060] Pressing and holding control switch S1 for a few seconds turns on first diode D1 and off second diode D2. The gate of transistor switch Q1 is grounded via first diode D1, and the gate voltage of transistor switch Q1 is low. Transistor switch Q1 is turned on, and the voltage output from power supply output terminal 1702 is 12V. First voltage regulator circuit 1721 converts the 12V voltage to 5V, and second voltage regulator circuit 1722 converts the 5V voltage to 3.3V. By properly arranging the resistance values ​​of resistors R4, R5, and R6, the 3.3V voltage can be divided by resistors R4, R5, and R6, thereby raising the potential of control input terminal POWER_KEY_IN to a high level. Controller 1711 can be configured to cause control output terminal POWER_ON to output a high level when the potential of control input terminal POWER_KEY_IN is high. This turns on transistor switch Q2. At this time, the control switch S1 is released, and the gate voltage of the transistor switch Q1 is the divided voltage of the resistors R1 and R2. By properly setting the resistance values ​​of the resistors R1 and R2, the gate of the transistor switch Q1 can be kept at a low level, even if the transistor switch Q1 is in the on state. At this time, the communication circuit 13, the first communication chip 11 and the second communication chip 12 in the gateway circuit 100 are powered on and working.

[0061] Press control switch S1 again and hold it for a few seconds. This turns on second diode D2, pulling the potential of control input terminal POWER_KEY_IN low. Controller 1711 can be configured to cause control output terminal POWER_ON to output a low level when the potential of control input terminal POWER_KEY_IN is low. At this point, transistor switch Q2 and transistor switch Q1 are turned off, and communication circuit 13, first communication chip 11, and second communication chip 12 in gateway circuit 100 are powered off and cease operation.

[0062] Figure 3 2 is a schematic diagram of a gateway device 200 provided in accordance with an embodiment of the present application.

[0063] See also Figure 3 , the gateway device 200 includes a gateway circuit 100 .

[0064] In some embodiments, the gateway device 200 is an IoT gateway device. Specifically, the IoT gateway device is an OpenThread protocol-based gateway device. The power supply circuit 17 can provide a hard boot mode for the gateway device 200.

[0065] The working principle of the gateway device 200 is described below.

[0066] Figure 4 This is a flowchart of a communication method provided by an embodiment of the present application. Figure 5This is a software architecture block diagram of the gateway device 200 provided in one embodiment of the present application.

[0067] See also Figure 4 and Figure 5 , the communication method can be applied to the gateway device 200, including step S41 and step S42.

[0068] In step S41 , the second communication chip 12 encapsulates a signal received from the terminal into a data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and sends the data frame to the first communication chip 11 .

[0069] In some embodiments, the first communication protocol stack includes an IP-based wireless network protocol stack. Specifically, the first communication protocol stack may be an OpenThread protocol stack. The following uses the OpenThread protocol stack as an example to illustrate how the physical layer and MAC control sublayer of the first communication protocol stack are integrated into the second communication chip 12.

[0070] In some embodiments, the second communication chip 12 can be a chip with a standard network architecture, such as an nRF system-on-chip. By compiling an IoT operating system in the second communication chip 12, the physical layer and MAC control sublayer in the first communication protocol stack can be integrated into the IoT operating system. Here, integrating the physical layer and MAC control sublayer in the first communication protocol stack into the IoT operating system means that only the physical layer and MAC control sublayer in the first communication protocol stack are selectively integrated into the second communication chip 12, and other layers other than the physical layer and MAC control sublayer are not integrated.

[0071] In some embodiments, the IoT operating system may include a real-time operating system (RTOS). Specifically, the RTOS may include the Zephyr embedded RTOS. The MAC control sublayer in the OpenThread protocol stack and the Nordic nRF IEEE 802.15.4 radio driver (i.e., the physical layer of the OpenThread protocol stack) may be integrated based on the L2 network technology layer of the Zephyr embedded RTOS. In some embodiments, the RX connection of the IEEE 802.15.4 radio driver is established via an interrupt handler. The interrupt handler is registered using Zephyr's mechanism. The registered interrupt handler uses Zephyr's FIFO to pass frames from the IEEE 802.15.4 radio driver. The RX connection of the IEEE 802.15.4 radio driver runs at the highest collaborative priority and waits on this FIFO. When a new frame appears, the thread continues processing. The TX connection of the IEEE 802.15.4 radio driver uses a work queue, which calls the IEEE 802.15.4 radio driver to schedule the transmission and then sends the frame using the RTC IRQ. In this way, the embedded porting (i.e. integration) of OpenThread in the Zephyr embedded real-time operating system is realized. In addition, CMake rules are defined in the porting development to implement the abstract layer interface of OpenThread and verify the hardware port of the second communication chip 12. Figure 5 For example, the software architecture frame Zephyr integration of the second communication chip 12 represents the integrated part of the Zephyr embedded real-time operating system described above running in the second communication chip 12; the software architecture frames OpenthreadController and IEEE 802.15.4PHY respectively represent the MAC control sublayer in the OpenThread protocol stack integrated in the Zephyr embedded real-time operating system and the IEEE 802.15.4 radio driver of Nordic nRF (i.e., the physical layer of the OpenThread protocol stack); the software architecture frame Multiprotocol Severvice layer represents the IEEE802.15.4 multi-protocol service library.

[0072] In some embodiments, the MAC control sublayer in the OpenThread protocol stack and the IEEE 802.15.4 radio driver of Nordic nRF are integrated based on the L2 network technology layer of the Zephyr embedded real-time operating system, so that the terminals of the OpenThread network connected to the gateway device 200 can selectively use the IP protocol stack of Zephyr or directly use the OpenThread API and IPv6 protocol stack.

[0073] In some embodiments, the Zephyr embedded real-time operating system and the MAC control sublayer and physical layer in the OpenThread protocol stack can run on Figure 1 The second processing unit 120 includes hardware resources such as a CPU and storage, and provides hardware support for compiling the Zephyr embedded real-time operating system on the second communication chip 12 and integrating the MAC control sublayer and physical layer in the OpenThread protocol stack.

[0074] Furthermore, in some embodiments, encapsulating the signal received from the terminal into a data frame and sending the data frame to the first communication chip 11 includes:

[0075] The second communication chip 12 encapsulates the data frame based on the inter-chip communication protocol and sends the encapsulated data frame to the first communication chip 11. The inter-chip communication protocol includes the Spinel protocol. That is, the second communication chip 12 encapsulates the data frame based on the Spinel protocol. Figure 5 In the figure, the software architecture of the second communication chip 12 is Spinel, which means that the second communication chip 12 encapsulates the data frame based on the Spinel protocol and then sends the encapsulated data frame to the first communication chip 11 through the serial interface.

[0076] In step S42 , the first communication chip 11 encapsulates the data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sublayer, and sends the encapsulated data packet to the target network.

[0077] In some embodiments, taking the first communication protocol stack as the OpenThread protocol stack and the first communication chip 11 as an MTK chip as an example, other layers of the OpenThread protocol stack except the physical layer and the MAC control sublayer can be compiled based on the embedded operating system (e.g., the OpenWrt operating system) included in the first communication chip 11. Figure 5In the figure, the software architecture frame IEE802.15.4MAC in the first communication chip 11 represents the other layers in the data link layer of the OpenThread protocol stack except the MAC control sublayer; the software architecture frame 6LoWPAN / IPv6 represents the network layer in the OpenThread protocol stack; the software architecture frame UDP represents the transport layer in the OpenThread protocol stack; the software architecture frame CoAP / MLE / DHCPv6 / MeshCop represents the application layer in the OpenThread protocol stack.

[0078] Specifically, the embedded operating system and other layers of the OpenThread protocol stack except the physical layer and MAC control sublayer can run on Figure 1 The first processing unit 110 includes hardware resources such as a CPU and storage, and provides hardware support for running the embedded operating system and other layers in the OpenThread protocol stack except the physical layer and the MAC control sublayer.

[0079] In some embodiments, after the first communication chip 11 receives a data frame sent by the second communication chip 12, it can decapsulate the received data frame based on the inter-chip communication protocol, and encapsulate the decapsulated data frame based on other layers in the first communication protocol stack except the physical layer and the MAC control sublayer. Specifically, in this embodiment, after the first communication chip 11 receives a data frame sent by the second communication chip 12, it can decapsulate the received data frame based on the Spinel communication protocol, and encapsulate the decapsulated data frame based on other layers in the OpenThread protocol stack except the physical layer and the MAC control sublayer, and then send the encapsulated data packet.

[0080] In some embodiments of the present application, the communication method of the present application runs the protocol stack core of the first communication protocol stack (such as the OpenThread protocol stack) on the first communication chip 11 with strong computing power, and only runs the MAC control sublayer and the physical layer on the second communication chip. Based on the strong computing power of the first communication chip 11, the performance of the gateway device 200 can be significantly improved, such as throughput performance and the number of connectable terminals.

[0081] Furthermore, the encapsulated data packet can be sent by the gateway device 200 to a target network, such as the Internet, via one of the WiFi network, the 4G network, and the Ethernet network. The first processing unit 110 of the first communication chip 11 can also compile a WiFi protocol stack ( Figure 5 Wi-Fi stack in ), 4G protocol stack ( Figure 5 4Gstack) and Ethernet protocol stack ( Figure 5 The Ethernet stack in the ISP is used to support WiFi, 4G, and Ethernet network functions.

[0082] Accordingly, the present application also provides a communication method, which can enable the gateway device 200 to automatically select a network connection with the best network performance after encapsulating the data packet to be sent to the target network, and send the data packet to the target network, such as the Internet.

[0083] Figure 6 FIG. 1 is a flow chart of a communication method provided by an embodiment of the present application. The communication method can be applied to the gateway device 200 and includes step S61 and step S63.

[0084] Step S61 : monitoring the network performance of each connected network among the connected networks of the gateway device 200 .

[0085] In some embodiments, the network performance includes at least one of a network transmission rate and a network delay, wherein a faster transmission rate per unit time of the network or a smaller network delay per unit time of the network indicates better network performance of the accessed network.

[0086] In some embodiments, the network performance of each connected network can be monitored through a network load optimizer.

[0087] In some embodiments, the network management tool ifconfig can be used to query the status of each network interface to confirm whether the network interface is available, and the ping command can be used to check the network connectivity of each network interface. If the network interface is available and the network is connected, it can be determined that the gateway device has a physical network path and software communication interface to connect to the target network.

[0088] Step S62, based on the monitored network performance of each connected network, determines the load amount allocated to each connected network, wherein the network performance is positively correlated with the load amount. For example, assuming that the connected networks of the gateway device 200 include Ethernet, WiFi and 4G. Among them, Ethernet has the best network performance, followed by WiFi, and finally 4G. The load amount allocated to each connected network can be set according to actual needs. For example, the load amount of Ethernet is set to 80, the load amount of WiFi is set to 15, and the load amount of 4G is set to 5. The above 80, 15, and 5 (i.e., load amount) represent the percentage of data amount to be sent through each connected network for the data amount to be sent to the target network. For example, assuming there is 100M of data to be sent, 80M is sent through Ethernet, 15M is sent through WiFi, and 5M is sent through 4G.

[0089] Step S63 , allocating the amount of data to be sent through each connected network according to the load of each connected network and the amount of data to be sent to the target network, wherein the connected network with a larger load has a larger amount of data to be sent.

[0090] In some embodiments of the present application, among the networks already connected to the gateway device 200, the amount of data to be sent through each connected network is determined based on the network performance of each connected network and the amount of data to be sent to the target network. A larger amount of data can be sent through a network with better network performance. This increases the network reliability of the gateway device 200.

[0091] In some embodiments, the network performance of each connected network of the gateway device 200 is monitored at predetermined intervals, and the load of each connected network is re-determined each time the network performance of each connected network is monitored. In this way, the load of the connected network of the gateway device 200 can be adjusted in a timely manner according to changes in the network environment of the gateway device 200, further improving network reliability.

[0092] Figure 7 FIG. 1 is a flow chart of a low-power data interaction method provided by an embodiment of the present application. The low-power data interaction method can be applied to the gateway device 200 and includes step S71 and step S73.

[0093] In step S71, if a data packet is received from the network management platform, the data packet is stored and a response message indicating that the terminal has received the data packet is returned to the network management platform. In some embodiments, the network management platform may be an IoT monitoring platform. Specifically, it may be a platform for monitoring and managing terminals on an OpenThread network. The network management platform communicates with the terminal via gateway device 200.

[0094] In some embodiments, the terminal is a low-power terminal that has a sleep cycle. During the sleep cycle, the terminal will disconnect from the gateway device 200 until the terminal wakes up and sends a heartbeat signal to the gateway device 200 to establish a network connection.

[0095] Step S72 determines the next heartbeat time point at which the terminal sends a heartbeat signal based on the time at which the terminal last received the heartbeat signal and the heartbeat cycle between the terminal and the terminal. For example, assuming that the terminal sends a heartbeat signal to the gateway device 200 every 24 hours (i.e., the heartbeat cycle is 24 hours), and the time point at which the terminal heartbeat signal was last received was 8:00 a.m. the previous day, then the time point at which the terminal heartbeat signal is next received should be 8:00 a.m. the following day. This time point is the next heartbeat time point.

[0096] In step S73, if a heartbeat signal is received from the terminal at the next heartbeat time, the data packet is sent to the terminal. In some embodiments, if a heartbeat signal is not received from the terminal at the next heartbeat time, the terminal is determined to be abnormal, and a message indicating the abnormality is sent to the network management platform to facilitate terminal management. Furthermore, in some embodiments, after determining that the terminal is abnormal, the gateway device 200 discards the data packet. This saves storage space.

[0097] In some embodiments of the present application, after receiving the data packet sent by the network management platform to the terminal, the gateway device 200 will store the data packet and return a response message to the network management platform indicating that the terminal has received the data packet. In this way, the network management platform can receive the response message in time after sending the data packet to the terminal, thereby reducing the probability of the network management platform misjudging the terminal as abnormal due to failure to receive the response message in time; on the other hand, the gateway device 200 stores the data packet and sends the data packet to the terminal after receiving the heartbeat signal sent by the terminal, so that the terminal does not need to remain awake, which is beneficial to reducing the power consumption of the terminal connected to the gateway device 200.

[0098] In some embodiments, sending a data packet to a terminal includes:

[0099] The first communication chip decapsulates the data packet based on other layers except the physical layer and the MAC control sublayer in the first communication protocol stack to obtain a data frame, and sends the data frame to the second communication chip.

[0100] The second communication chip decapsulates the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and sends the decapsulated signal to the terminal.

[0101] Decapsulating the data packet to obtain a data frame, and sending the data frame to the second communication chip, including:

[0102] The first communication chip encapsulates the data frame based on the inter-chip communication protocol, and sends the encapsulated data frame to the second communication chip.

[0103] Decapsulating the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, including:

[0104] The second communication chip decapsulates the received data frame based on the inter-chip communication protocol, and decapsulates the decapsulated data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack.

[0105] The above process of sending the data packet to the terminal is the same as the above process of sending the data packet to the terminal. Figure 4 For the opposite process, see Figure 4The relevant description is not repeated here.

[0106] Figure 8 It is a structural diagram of a gateway device 800 provided in one embodiment of the present application.

[0107] In some embodiments, the gateway device 800 includes a first communication chip 81 and a second communication chip 82 based on a first communication protocol, wherein the computing capability of the first communication chip 81 is greater than the computing capability of the second communication chip 82.

[0108] In some embodiments, the second communication chip 82 is configured to encapsulate a signal received from the terminal into a data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and send the data frame to the first communication chip 81. The first communication chip 81 is configured to encapsulate the data frame based on other layers in the first communication protocol stack except the physical layer and the MAC control sublayer, and send the encapsulated data packet.

[0109] In some embodiments, the first communication chip 81 is used to store the data packet sent to the terminal by the network management platform upon receiving the data packet, and return a response message to the network management platform indicating that the terminal has received the data packet; and based on the time of the last heartbeat signal received from the terminal and the heartbeat cycle between the terminal and the terminal, determine the next heartbeat time point for receiving the heartbeat signal sent by the terminal; and at the next heartbeat time point, upon receiving the heartbeat signal sent by the terminal, send the data packet to the terminal through the second communication chip 82. Furthermore, the first communication chip 81 is specifically used to decapsulate the data packet based on other layers in the first communication protocol stack except the physical layer and the MAC control sublayer, to obtain a data frame, and send the data frame to the second communication chip 82; the second communication chip 82 is specifically used to decapsulate the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and send the decapsulated signal to the terminal.

[0110] In some embodiments, the first communication chip 81 is used to monitor the network performance of each connected network in the connected network of the gateway device 800; and determine the load allocated to each connected network based on the monitored network performance of each connected network, wherein the network performance is positively correlated with the load; and allocate the amount of data to be sent through each connected network based on the load of each connected network and the amount of data to be sent to the target network, wherein the larger the load of the connected network, the larger the amount of data to be sent. Further, the first communication chip 81 is specifically used to monitor the network performance of each connected network in the connected network of the gateway device 800 at preset time intervals. And each time the network performance of each connected network is monitored, the load of each connected network is re-determined. Furthermore, the gateway device 800 also includes a second communication chip of the first communication protocol, and the computing power of the first communication chip is greater than the computing power of the second communication chip, wherein: the second communication chip is used to encapsulate the signal received from the terminal into a data frame based on the physical layer and MAC control sublayer in the first communication protocol stack, and send the data frame to the first communication chip; and the first communication chip is also used to encapsulate the data frame based on other layers in the first communication protocol stack except the physical layer and MAC control sublayer to obtain data sent to the target network.

[0111] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

[0112] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

Claims

1. A low-power data interaction method applied to a gateway device, characterized in that: The low-power data interaction method is applied to a gateway device, and the low-power data interaction method includes: If a data packet sent by the network management platform to the terminal is received, the data packet is stored, and a response message indicating that the terminal has received the data packet is returned to the network management platform; Determining a next heartbeat time point at which a heartbeat signal sent by the terminal is received next time based on the time at which the heartbeat signal sent by the terminal was last received and the heartbeat cycle between the terminal and the terminal; and If a heartbeat signal sent by the terminal is received at the next heartbeat time point, the data packet is sent to the terminal; After storing the data packet, if the heartbeat signal sent by the terminal is not received at the next heartbeat time point, it is determined that the terminal is abnormal, and a message indicating the terminal is abnormal is sent to the network management platform.

2. The low-power data interaction method according to claim 1, wherein: After determining that the terminal is abnormal, the data packet is discarded.

3. The low-power data interaction method according to claim 1, wherein: The gateway device includes a first communication chip and a second communication chip based on a first communication protocol, wherein the computing capability of the first communication chip is greater than the computing capability of the second communication chip; The sending the data packet to the terminal includes: The first communication chip decapsulates the data packet based on other layers except the physical layer and the MAC control sublayer in the first communication protocol stack to obtain a data frame, and sends the data frame to the second communication chip; The second communication chip decapsulates the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and sends the decapsulated signal to the terminal.

4. The low-power data interaction method according to claim 3, wherein: The decapsulating the data packet to obtain a data frame, and sending the data frame to the second communication chip, includes: The first communication chip encapsulates the data frame based on an inter-chip communication protocol, and sends the encapsulated data frame to the second communication chip; The decapsulating the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack includes: The second communication chip decapsulates the received data frame based on the inter-chip communication protocol, and decapsulates the decapsulated data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack.

5. The low-power data interaction method according to claim 4, wherein: The inter-chip communication protocol includes the spinel protocol.

6. The low-power data interaction method according to claim 3, wherein: The gateway device is an Internet of Things gateway device.

7. The low-power data interaction method according to claim 3, wherein: The first communication protocol is an IP-based wireless network protocol.

8. The low-power data interaction method according to claim 6 or 7, characterized in that: The first communication protocol is the OpenThread protocol.

9. A gateway device, characterized in that: The gateway device includes a first communication chip and a second communication chip based on a first communication protocol, wherein the computing capability of the first communication chip is greater than the computing capability of the second communication chip, wherein: The first communication chip is used to store the data packet sent to the terminal by the network management platform if it receives the data packet, and return a response message to the network management platform indicating that the terminal has received the data packet; and based on the time when the heartbeat signal sent by the terminal was last received and the heartbeat cycle between the terminal, determine the next heartbeat time point when the heartbeat signal sent by the terminal is received next time; and at the next heartbeat time point, receive the heartbeat signal sent by the terminal, and send the data packet to the terminal through the second communication chip; after storing the data packet, if the heartbeat signal sent by the terminal is not received at the next heartbeat time point, determine that the terminal is abnormal, and send a message indicating that the terminal is abnormal to the network management platform.

10. The gateway device according to claim 9, wherein: The first communication chip is specifically configured to decapsulate the data packet based on other layers except the physical layer and the MAC control sublayer in the first communication protocol stack to obtain a data frame, and send the data frame to the second communication chip; The second communication chip is specifically configured to decapsulate the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and send the decapsulated signal to the terminal.

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