Transaction queue occupancy-based control of memory frequency

Abstract

Techniques and apparatus are described for using a transaction queue length to vary a clock frequency that controls access to a memory (112, 114) of an electronic device (102). The techniques include detecting (502) that a transaction queue threshold has been violated, starting (504) a counter to measure a duration, determining (506) that the transaction queue threshold continues to be violated for the duration, and in response, varying (508) a clock frequency (210, 212) that controls access to the memory (112, 114) of the electronic device (102).

Description

Background Art

[0001] Electronic devices play an indispensable role in manufacturing, communication, healthcare, business, social interaction, and entertainment. For example, electronic devices power server farms that provide cloud-based distributed computing functionality for business and communication. Devices with computing capabilities are also embedded in many different types of modern devices, from medical devices to household appliances and from vehicles to industrial tools. Additionally, one electronic device (smartphone) has virtually become a necessity that consumers carry with them. As electronic devices become more and more prevalent, the power consumed by the electronic devices is increasingly becoming a problem.

[0002] One factor to consider in the power consumption of electronic devices is the power consumed by the integrated circuit (IC) devices of the electronic devices. Generally, the power consumption of IC devices increases as the clock frequency that controls the IC devices increases. In some cases, a relatively high clock frequency may be desirable for one or more IC devices to achieve an improved performance level. However, if the clock frequency remains high when an improved performance level is not needed, power may be wasted. Thus, it can be challenging to balance power efficiency with performance while controlling the clock frequency.

[0003] This background description is provided to present the context of the present invention generally. Unless otherwise indicated herein, the materials described in this section are neither expressly nor implicitly admitted to be prior art to the present disclosure or the appended claims. Summary of the Invention

[0004] Techniques and apparatus for using transaction queue occupancy to change the clock frequency that controls access to a memory of an electronic device are described. The techniques include detecting that a transaction queue threshold has been violated, starting a counter to measure a duration, determining that the transaction queue threshold continues to be violated for the duration, and changing the clock frequency that controls access to the memory in response to the extended violation.

[0005] In some aspects, a method performed by a memory controller is described. The method includes detecting that a transaction queue threshold corresponding to an occupied portion of the length of a transaction queue for a memory is violated. In response to detecting the violation, the method starts a counter based on a clock frequency that controls the rate of access to the memory to measure the duration. The method also includes determining that the transaction queue threshold continues to be violated for the duration, and in response, changing the clock frequency.

[0006] In some other aspects, a method performed by a memory controller is described. The method includes calculating, for a second clock frequency that is lower than a current rate of controlling access to a memory, a number of clock cycles consumed to perform a transaction with the memory. In some cases, the calculated number of clock cycles consumed to perform a transaction with the memory corresponds to an analog occupancy portion of a length of a transaction queue for accessing the memory. The method further includes determining that the analog occupancy portion of the length of the transaction queue will drop below a transaction queue threshold for a duration, and in response, reducing a rate of accessing the memory to the second clock frequency.

[0007] In some other aspects, another method performed by an electronic device is described. The method includes determining, by a first memory controller of a first memory of the electronic device, that a transaction queue threshold has been violated for a duration. The transaction queue threshold corresponds to an occupancy portion of a length of a transaction queue for accessing a second memory. In response, the first memory controller sends a message to a second memory controller of a second memory of the electronic device. The message includes an instruction to cause the second memory controller to change a clock frequency to vary a rate of accessing the second memory.

[0008] Details of one or more implementations are set forth in the accompanying drawings and the following description. Other features and advantages will be apparent from the description, the drawings, and the claims. The Summary is provided to introduce a subject that is further described in the Detailed Description. Therefore, the reader should not regard the Summary as describing essential features nor as limiting the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Apparatuses and techniques for changing a clock frequency that controls access to a memory based on a transaction queue occupancy are described with reference to the following drawings. The same numbers are used throughout the drawings to refer to the same features and components:

[0010] Figure 1 An example environment including an integrated circuit is shown in which a clock frequency that controls access to a memory can be changed based on a transaction queue occupancy.

[0011] Figure 2 Example details of a cache memory transaction queue and a main memory transaction queue are shown in accordance with one or more aspects.

[0012] Figure 3 An example transaction request profile is shown in accordance with one or more aspects.

[0013] Figure 4 A flowchart is shown that illustrates an example heuristic for changing a clock frequency that controls access to a memory based on a transaction queue occupancy in accordance with one or more aspects.

[0014] Figure 5 Illustrates an example method in accordance with one or more aspects.

[0015] Figure 6 Illustrates another example method in accordance with one or more aspects.

[0016] Figure 7 Illustrates another example method in accordance with one or more aspects. Detailed Description

[0017] Overview

[0018] Describes techniques and apparatus for using transaction queue occupancy to vary a clock frequency that controls access to a memory of an electronic device. The techniques include detecting that a transaction queue threshold has been violated, starting a counter to measure a duration, determining that the transaction queue threshold continues to be violated for the duration, and varying the clock frequency that controls access to the memory of the electronic device in response to the extended violation.

[0019] Manufacturers typically consider expected power consumption levels when designing electronic devices. Motivations for reducing power consumption include reducing usage costs and minimizing environmental impact. Additionally, portable electronic devices are powered by batteries that have a limited ability to provide energy before needing to be recharged. Thus, it is possible to use a portable electronic device before it needs to be recharged by reducing power consumption. A lower power consumption rate can also enable the use of a smaller battery to reduce the size of the portable electronic device.

[0020] The primary power-consuming devices of an electronic device are typically integrated circuit (IC) devices. Generally, the power consumption of an IC device can scale with an increase in the clock frequency that controls the IC device (e.g., a clock frequency typically measured in megahertz (MHz) or gigahertz (GHz)). A relatively high clock frequency may be desirable for an IC device to achieve an improved performance level. However, if the clock frequency of an IC device remains high when an improved performance level is not needed, power may be wasted.

[0021] A memory controller can be used to control the clock frequency and rate of memory transactions (or accesses) between a processor IC device and a memory IC device. Heuristics within the memory controller typically rely on counting methods that count the total number of accesses, such as writes to or reads from the memory IC device. If the total number of accesses violates a predefined upper threshold, then the memory controller can increase the clock frequency of the memory IC device. If the total number of memory accesses violates a predefined lower threshold, then the memory controller can decrease the clock frequency of the memory IC device.

[0022] However, heuristics that rely on such counting methods are often flawed. As an example, in some cases, accesses to memory by a processor can be clustered within relatively small time windows. This presents a conflict where the heuristic indicates that a predefined upper limit threshold is not violated, but in reality, an increase in the clock frequency of the memory IC device is desirable to maintain performance. To compensate for this flaw, heuristics using the counting method can artificially lower the predefined upper limit threshold such that the memory controller triggers an increase in the clock frequency more quickly.

[0023] However, by using this compensation method, new flaws may be introduced. For example, in other cases where accesses to memory by a processor can be evenly distributed across a relatively large time window, the artificially lowered upper limit threshold can cause the memory controller to trigger an increase in the clock frequency that is not actually needed. In these other example cases, the unneeded clock frequency may waste power.

[0024] As the complexity of the memory architecture of an electronic device increases, the drawbacks of heuristics that use a counting method to control the clock frequency of memory IC devices in the electronic device composition itself increase. For example, an electronic device can use a memory architecture that depends on a main memory IC device and multiple levels of cache memory IC devices, and each cache memory IC device can include a corresponding memory controller to control the corresponding clock frequency. However, these drawbacks can be overcome by adopting a heuristic that uses factors including the occupancy of a transaction queue as described herein to determine thresholds for increasing and / or decreasing the frequency.

[0025] Example implementations at various levels of detail are discussed below with reference to the associated drawings. Example implementations include: (i) a method of changing the clock frequency based on a transaction queue threshold being violated for a duration, (ii) another method of decreasing the clock frequency based on a simulated occupancy portion of the length of the transaction queue dropping below the transaction queue threshold for a duration, and (iii) another method that includes a first memory controller determining that a transaction queue threshold has been violated for a duration and sending a message to a second memory controller indicating that the second memory controller change the rate of access to a second memory. The following discussion first describes an example operating environment, followed by example heuristic details, followed by example methods, and concludes with various aspects of the related examples.

[0026] Example Environment

[0027] Figure 1An example environment 100 including an integrated circuit is shown, in which the clock frequency for controlling access to memory can be changed based on transaction queue occupancy. As shown, environment 100 includes an electronic device 102. Although shown as a smart phone, electronic device 102 can be a computer, tablet computer, laptop computer, server, wearable device, Internet of Things (IoT) device, entertainment device, security device, etc.

[0028] Electronic device 102 includes an integrated circuit 104. Integrated circuit 104 includes a plurality of different parts or cores. These include at least one processor 106, a first-level cache memory (e.g., L1 cache memory 108), a second-level cache memory (e.g., L2 cache memory 110), a third-level cache memory (e.g., L3 cache memory 112), and a main memory 114. Generally, different memories (e.g., L1 cache memory 108, L2 cache memory 110, L3 cache memory 112, and main memory 114) can operate in one or more memory states using different respective clock frequencies.

[0029] The different memories can be of different types and / or combinations. For example, L1 cache memory 108, L2 cache memory 110, and L3 cache memory 112 can each be a memory type corresponding to static random access memory (SRAM) that is "on-chip" (e.g., sharing the same IC die with processor 106). In contrast, main memory 114 can be a memory type corresponding to dynamic random access memory (DRAM) that is "off-chip" (e.g., on a different IC die from processor 106). Alternatively, the different memories can all share the same IC die with processor 106 (e.g., sharing a system-on-chip (SoC) IC die with processor 106), can be one or more other types of memories (e.g., flash memory), etc.

[0030] In an example implementation, one or more of the different memories can include a controller. For example, main memory 114 can include a main memory controller 116, and L3 cache memory 112 can include an L3 cache memory controller 118. In some cases, main memory controller 116 and L3 cache memory controller 118 can each include logic circuitry for changing the data flow to and from the respective memories. Additionally, main memory controller 116 can be communicatively coupled to L3 cache memory controller 118.

[0031] In some cases, the processor 106 may attempt to access data in different memories in a hierarchical manner (e.g., read data from or write data to a memory to perform a transaction). For example, when executing a program or instruction set, the processor 106 may first attempt to access the target data in the L1 cache memory 108 (corresponding to the physical address or location allocated in the main memory 114). If the data associated with a particular physical address or location is not accommodated in the L1 cache memory 108 (e.g., a miss in the first cache), the system is able to attempt to access the target data a second time, but using the L2 cache memory 110. If the data associated with the allocated physical address or location is not accommodated in the L2 cache memory 110 (e.g., a miss in the second cache), the system is able to attempt to access the target data a third time, but using the L3 cache memory 112. If the data associated with the allocated physical address or location is not accommodated in the L3 cache memory 112 (e.g., a miss in the third cache), the system can then access the target data from the main memory 114 (e.g., access the target data using the physical address or location allocated in the main memory 114).

[0032] Data transactions between the processor 106 and the L1 cache memory 108, L2 cache memory 110, L3 cache memory 112, and main memory 114 may occur at a rate controlled by a clock frequency (e.g., a clock frequency in MHz or GHz). The clock frequency of data transactions between the processor 106 and the memories may vary for each memory.

[0033] Figure 2 An example detail 200 of a cache memory transaction queue and a main memory transaction queue is shown according to one or more aspects. As Figure 2 shown, the L3 cache memory 112 includes an L3 cache memory transaction queue 202 (e.g., Cache_Q) having a length 204 (e.g., a length corresponding to the number of "L+1" entries available in the L3 cache memory transaction queue 202). In some cases, the L3 cache memory transaction queue 202 may be an outgoing transaction queue from which the processor 106 can read data.

[0034] The main memory 114 contains a main memory transaction queue 206 (e.g., Main_Q) having another length 208 (e.g., a length corresponding to the number of "N+1" available entries in the main memory transaction queue 206). In some cases, the main memory transaction queue 206 may be an incoming transaction queue to which the processor 106 can write data.

[0035] Memory transactions between the processor 106 and the L3 cache memory 112 (e.g., memory reads and / or writes corresponding to entries in the L3 cache memory transaction queue 202) can be serviced at a rate responsive to or corresponding to the L3 cache memory clock frequency 210. Memory transactions between the processor 106 and the main memory 114 (e.g., memory reads and / or writes corresponding to entries in the main memory transaction queue 206) can be serviced at a rate responsive to or corresponding to the main memory clock frequency 212.

[0036] Typically, and due to differences in the length of the transaction queues and / or differences in the clock frequencies, transactions between the processor 106 and the respective memories can be completed at different rates. For example, if the length 204 is relatively shorter than the length 208, and if the L3 cache memory clock frequency 210 is relatively higher than the main memory clock frequency 212, the processor 106 can complete memory transactions with the L3 cache memory 112 faster than it can complete different transactions with the main memory 114.

[0037] In some cases, and as will be described in more detail below, the L3 cache memory controller 118 and / or the main memory controller 116 can use heuristics to control the L3 cache memory clock frequency 210 and / or the main memory clock frequency 212. Such heuristics can use the occupied portion 214 of the length 204 of the L3 cache memory transaction queue 202 and / or the occupied portion 216 of the length 208 of the main memory transaction queue 206.

[0038] Figure 3 An example transaction request profile 300 in accordance with one or more aspects is shown. In some cases, the transaction request profile 300 can be associated with Figure 1 and 2 the processor 106 of Figure 1 and 2 the processor 106 uses Figure 1 and 2 the aspects depicted in Figure 1 and 2 to perform transactions with

[0039] The first example transaction request profile 302 shows an example of a relatively low and uniform distribution of memory transaction requests over a predetermined duration. As shown, the transaction request profile 302 indicates that the processor 106 requests a number "X" of transactions (e.g., count = X) with the main memory 114 over a predetermined duration spanning between t0 and t1.

[0040] Due to the uniform distribution, there are no memory transaction misses between the processor 106 and the main memory 114 (e.g., the main memory clock frequency 212 enables the main memory 114 to support memory transactions at a rate compatible with requests from the processor 106). Using a heuristic based on a count-based threshold (e.g., the count threshold for X), the main memory controller 116 will determine not to increase the main memory clock frequency 212 of the first example transaction request profile 302.

[0041] The second example transaction request profile 304 shows an example of a non-uniform distribution of memory transaction requests across the same predetermined duration. Even if the processor 106 requests the same number of transactions (e.g., count = X) with the main memory 114 over the same predetermined time period, the transaction request profile 304 includes "bursts" during which the number of transaction requests is relatively high.

[0042] If the main memory clock frequency 212 is relatively low, the main memory 114 may "stall" during the burst (e.g., be unable to fulfill the requested transactions with the processor 106). However, using a heuristic based on a count-based threshold (e.g., the count threshold for X), the main memory controller 116 will still determine not to increase the main memory clock frequency 212 of the second example transaction request profile 304.

[0043] In some cases, and to avoid stalling that may occur during burst situations, the heuristic in the main memory controller 116 may use a lower count threshold (e.g., count threshold < X). However, this may unnecessarily increase the main memory clock frequency 212 during steady-state conditions and thus waste power.

[0044] The third example transaction request profile 306 shows an example of a relatively high and uniform distribution of memory transaction requests across the same predetermined duration. As shown, the transaction request profile 306 indicates that the processor 106 requests a number of "Y" transactions (e.g., count = Y) with the main memory 114 during the predetermined duration spanning between t0 and t1. Using a heuristic based on a count-based threshold (e.g., the count threshold for Y), the main memory controller 116 will determine to increase the main memory clock frequency 212. However, the increase in the main memory clock frequency 212 will not become apparent until after the predetermined duration has passed. Additionally, the main memory 114 may stall before the expiration of the predetermined duration.

[0045] Typically, an improved heuristic that uses one or more thresholds based on memory transaction queue occupancy (e.g., the occupied portion of the length of the memory transaction queue) can mitigate the disadvantages associated with heuristics that use count-based thresholds. The improved heuristic can proactively increase the clock frequency that controls access to memory before an instance where memory stalls may occur or can proactively decrease the clock frequency that controls access to memory before a situation where power may be wasted, to further improve power efficiency.

[0046] Example Heuristic Details Using Transaction Queue Occupancy

[0047] Figure 4 FIG. 400 is a flow chart illustrating an example heuristic for using transaction queue occupancy to vary the clock frequency that controls access to memory, in accordance with one or more aspects. For simplicity, the following description of FIG. 400 will be in the context of a main memory controller 116 that controls the main memory clock frequency 212 of main memory 114. Figure 1 and 2 Nonetheless, the principles described apply to other memory types and / or levels, such as cache memory and corresponding cache memory controllers that operate in response to a cache memory clock frequency.

[0048] In some cases, the heuristic of FIG. 400 can be initiated during the power-on condition of an electronic device (e.g., Figure 1 electronic device 102). In other cases, the heuristic of FIG. 400 can be initiated in response to a command typed by a user of the electronic device 102 (e.g., via a selectable menu where the user can vary the mode or settings of the electronic device to operate in a particular memory clock frequency mode using specific parameters or categories indicative of memory performance and / or power efficiency).

[0049] At decision 402, the transaction queue state is determined relative to a transaction queue threshold. The transaction queue threshold can correspond to the occupied portion of the length of the transaction queue. Using the main memory transaction queue 206 and main memory controller 116 as an example, the main memory controller 116 can calculate the occupied portion 216 of the length 208. If the calculation indicates that the transaction queue threshold is not violated (e.g., the occupied portion 216 of the length 208 is not greater than 75%), then the main memory controller 116 can reset (e.g., clear) a timer at process 404. In some cases, the timer can be implemented as a circuit that is included as part of the main memory controller 116 and is capable of tracking a duration using the main memory clock frequency 212.

[0050] The main memory controller 116 can continue to monitor the main memory transaction queue 206 at operation 406. At decision 408, the main memory controller 116 can determine that the occupied portion 216 of the length 208 exceeds a transaction queue threshold (e.g., the occupied portion 216 is greater than 75% of the length 208). When it is determined that the transaction queue threshold has been exceeded, the main memory controller 116 can start a timer at operation 410 to monitor the duration as indicated at decision 412.

[0051] Over time, the main memory controller 116 can determine at decision 412 that the transaction queue threshold has been violated for a duration (e.g., as shown, exceeding 75% of the transaction queue threshold for 500 milliseconds (ms)) by iteratively monitoring the occupied portion 216 of the length 208 and comparing the occupied portion 216 with the transaction queue threshold (at decision 402). In response, the main memory controller 116 can increase the main memory clock frequency 212 at operation 414 to increase the rate at which the processor 106 can access the main memory 114 (e.g., by increasing the rate at which the main memory 114 processes memory transaction requests).

[0052] Although the heuristics of the above flowchart 400 apply to a transaction queue threshold that provides an upper limit threshold (e.g., the threshold is violated if exceeded), a variation of the heuristics can apply to a transaction queue threshold that provides a lower limit threshold (e.g., the threshold is violated if the monitored value drops below the threshold). For example, the main memory controller 116 can determine that the occupied portion 216 of the length 208 has dropped below 50% of another threshold for another duration, and in response, reduce the main memory clock frequency 212 to reduce the rate of accessing the main memory 114.

[0053] The heuristics shown by flowchart 400 can also be modified to include simulation. Simulation can be used to "predict" whether a lower frequency is sufficient for the current memory transaction rate. For example, using the main memory clock frequency 212, the main memory controller 116 can calculate the number of clock cycles consumed to execute a memory transaction. The main memory controller 116 can determine that the simulated occupied portion 216 of the length 208 of the main memory transaction queue 206 will or may drop below the threshold based on the calculated number of clock cycles. In response to this determination based on the simulation using the calculated number of clock cycles at a given clock frequency, the main memory controller 116 can reduce the main memory clock frequency 212. In some cases, such simulation can use multiple iterations to gradually reduce the main memory clock frequency 212 using different thresholds.

[0054] In some cases, the heuristics shown by flowchart 400 can be performed by a combination of memory controllers. For example, the main memory controller 116 and the L3 cache memory controller 118 can be communicatively coupled, allowing the operations and decisions of flowchart 400 to be separated or shared between the main memory controller 116 and the L3 cache memory controller 118. The main memory controller 116 or the L3 cache memory controller 118 can control other clock frequencies, for example, by the exchange of messages, instructions, etc.

[0055] Generally, the parameters affecting the heuristics of flowchart 400 can be variables. For example, the transaction queue threshold (whether it is an upper threshold or a lower threshold) can be 50%, 60%, 70%, etc. As another example, the duration can be 100 ms, 500 ms, 1000 ms, etc. In some cases, the user can change or input such parameters into the electronic device 102 through a selectable menu, which can use qualitative terms (such as "memory power saving mode" or "memory high performance mode") to represent different thresholds. In other cases, the manufacturer of the electronic device 102 can load the parameters into the electronic device 102. In other cases, the electronic device 102 can include power monitoring circuitry and logic that change the parameters based on the charge level available to the electronic device (such as stored power).

[0056] Figure 5 An example method 500 according to one or more aspects is shown. In some cases, method 500 can be performed by a memory controller using Figure 1 , Figure 2 and Figure 4 components.

[0057] At operation 502, the memory controller (e.g., the main memory controller 116) can detect that a transaction queue threshold has been violated. The transaction queue threshold can correspond to the occupied portion 216 of the length 208 of the main memory transaction queue 206. In some cases, the violation can correspond to exceeding an upper threshold, while in other cases, the violation can correspond to dropping below a lower threshold.

[0058] At operation 504, and in response to determining that the transaction queue threshold has been violated, the memory controller can start a clock frequency-based counter to measure a duration (e.g., for a given or known clock frequency, the counter can count the number of cycles and calculate the corresponding duration from the counted number of cycles). The clock frequency can correspond to the main memory clock frequency 212 that controls the rate at which the main memory 114 can process memory requests issued by the processor 106.

[0059] At operation 506, the memory controller may determine that a transaction queue threshold continues to be violated for a duration. At 508, and in response to determining that the transaction queue threshold continues to be violated for a duration, the memory controller may change a clock frequency.

[0060] In a case where the transaction queue threshold is an upper threshold and violating the transaction queue threshold for a duration includes exceeding the transaction queue threshold for a duration, changing the clock frequency may include increasing the clock frequency to increase the rate at which the processor can access the memory. In a case where the transaction queue threshold is a lower threshold and violating the transaction queue threshold for a duration includes falling below the transaction queue threshold for a duration, changing the clock frequency may include decreasing the clock frequency to reduce the operating rate of the memory to reduce power usage.

[0061] Although method 500 is described in the context of the main memory controller 116 changing the main memory clock frequency 212, method 500 includes many variations. For example, method 500 may be performed by another memory controller (such as the L3 cache memory controller 118). In such a case, the transaction queue threshold may correspond to the occupied portion 214 of the length 204 of the L3 cache memory transaction queue 202, the clock frequency may correspond to the L3 cache memory clock frequency 210, and the memory may correspond to the L3 cache memory 112. Method 500 may also cover other memories (e.g., the L1 cache memory 108, the L2 cache memory 110, etc.). Additionally, and in some cases, portions of method 500 may be performed by the processor 106.

[0062] Figure 6 Another example method 600 is shown in accordance with one or more aspects. In some cases, method 600 may be performed by a memory controller that uses Figure 1 、 Figure 2 and Figure 4 components.

[0063] At operation 602, a memory controller (e.g., the main memory controller 116) may calculate the number of clock cycles to turn back to execute memory transactions (e.g., read or write entries from the main memory transaction queue 206) for a second clock frequency that is lower than a first clock frequency for the current rate of accessing the memory (e.g., the main memory 114). The calculated number of clock cycles for each memory transaction may be used to simulate the change in size of the occupied portion of the length of the transaction queue for accessing the memory (e.g., simulate how the occupied portion 216 of the length 208 of the main memory transaction queue 206 changes over time in a case where the main memory 114 processes memory transactions at a slower second clock frequency).

[0064] At operation 604, the memory controller may determine that an analog occupied portion of a length (e.g., portion 216 of the length 208 as analog) drops below a transaction queue threshold for a duration. At operation 606, the memory controller may then reduce the rate of accessing the memory from a first clock frequency to a second clock frequency.

[0065] In some cases, determining that an analog occupied portion of a length drops below a transaction queue threshold may include subtracting an offset (e.g., an offset used as a guard band or bias) from the transaction queue threshold. Additionally, in some cases, the memory controller may identify a value of the second clock frequency by using an iterative calculation of multiple other clock frequencies that are lower than the first clock frequency. In such cases, and before identifying the second clock frequency, the memory controller may determine that the multiple other clock frequencies have an analog portion of the length of the transaction queue that is greater than or equal to the transaction queue threshold for a duration.

[0066] Although method 600 is described in the context of the main memory controller 116 changing the main memory clock frequency 212, method 600 includes many variations. For example, method 600 may be performed by another memory controller (such as the L3 cache memory controller 118). In such a case, the transaction queue threshold may correspond to an occupied portion 214 of the length 204 of the L3 cache memory transaction queue 202 (e.g., as analog portion 214), the clock frequency may correspond to the L3 cache memory clock frequency 210, and the memory may correspond to the L3 cache memory 112. Method 600 may also cover other memories (e.g., L1 cache memory 108, L2 cache memory 110, etc.). Additionally, and in some cases, portions of method 600 may be performed by the processor 106.

[0067] Figure 7 Another example method 700 is shown in accordance with one or more aspects. In some cases, method 700 may use Figure 1 、 Figure 2 and Figure 4 elements of which are performed by a memory controller of an electronic device (such as Figure 1 the main memory controller 116 and the L3 cache memory controller 118 of the electronic device 102).

[0068] At operation 702, a first memory controller (e.g., the main memory controller 116) may determine that a transaction queue threshold has been violated for a duration. In such a case, the transaction queue threshold may correspond to an occupied portion of the length of a memory transaction queue (e.g., the occupied portion 214 of the length 204 of the L3 cache memory transaction queue 202).

[0069] In response, at operation 704, the first memory controller may send a message to the second memory controller (e.g., the L3 cache memory controller 118). The message may include an instruction to direct (e.g., cause) the second memory controller to change the clock frequency to vary the rate of accessing the second memory (e.g., the L3 cache memory 112).

[0070] Although described in the context of operations between the main memory controller 116 and the L3 cache memory controller 118, method 700 includes many variations. As a first example variation, method 700 may include operations performed by the L3 cache memory controller 118 and another cache memory controller (e.g., the controller of the L1 cache memory 108 or the L2 cache memory 110). As a second example variation, the L3 cache memory controller 118 may use the input from the main memory controller 116 as an additional input for controlling the rate of accessing the L3 cache memory 112 (e.g., whether the L3 cache memory controller 118 controls the L3 cache memory clock frequency 210 based on the occupied portion 214 of the length 204 of the L3 cache memory transaction queue 202, or whether the L3 cache memory controller 118 uses another technique to control the L3 cache memory clock frequency 210). As a third example variation, portions of method 700 may be performed by the processor 106.

[0071] The foregoing discussion describes methods related to using transaction queue occupancy to change the clock frequency that controls access to the memory of an electronic device. Aspects of these methods may be implemented in hardware (e.g., fixed logic circuitry), firmware, software, or any combination thereof. As an example, one or more of the operations described in methods 500, 600, or 700 may be performed by a computing system having one or more processors and a computer-readable medium (CRM). In such a case, the CRM may include fixed or hard-coded circuitry, finite state machines, programming logic, etc., that execute one or more operations.

[0072] In addition, these techniques may use Figure 1 、 Figure 2 and Figure 4 one or more of the entities or components shown in, which may be further separated, combined, etc. Thus, these illustrate some of the many possible systems or apparatuses that can employ the described techniques. The entities and components of these figures generally represent all or part of software, firmware, hardware, devices, or networks, or combinations thereof.

[0073] Additional examples

[0074] Example 1: A method performed by a memory controller, the method comprising: detecting that a transaction queue threshold is violated, the transaction queue threshold corresponding to an occupied portion of the length of a transaction queue for accessing a memory; in response to the detection, starting a counter to measure a duration, the counter based on a clock frequency that controls a rate of accessing the memory; determining that the transaction queue threshold continues to be violated for the duration; and in response to the determination, changing the clock frequency.

[0075] Example 2: The method according to Example 1, wherein: the transaction queue threshold is an upper threshold; violating the transaction queue threshold for a duration includes exceeding the transaction queue threshold for the duration; and changing the clock frequency increases the clock frequency to increase a rate of accessing the memory.

[0076] Example 3: The method according to Example 1, wherein: the transaction queue threshold includes a lower threshold; violating the transaction queue threshold for a duration includes dropping below the transaction queue threshold for the duration; and changing the clock frequency decreases the clock frequency to decrease a rate of accessing the memory.

[0077] Example 4: The method according to any one of Examples 1 to 3, wherein the memory includes a main memory, and the main memory includes a dynamic random access memory.

[0078] Example 5: The method according to any one of Examples 1 to 3, wherein the memory includes a cache memory, and the cache memory includes a static random access memory.

[0079] Example 6: The method according to any one of Examples 1 to 5, wherein the memory shares a system-on-chip integrated circuit die with a processor.

[0080] Example 7: A method performed by a memory controller, the method comprising: calculating, for a second clock frequency that is lower than a first clock frequency that currently controls a rate of accessing a memory, a number of clock cycles consumed by performing transactions with the memory, the calculated number of clock cycles consumed by performing transactions with the memory corresponding to an analog occupied portion of the length of a transaction queue for accessing the memory; based on the calculated number of clock cycles, determining that the analog occupied portion of the length of the transaction queue will drop below a transaction queue threshold for a duration; and in response to the determination, reducing the rate of accessing the memory to the second clock frequency.

[0081] Example 8: The method according to Example 7, wherein determining that the analog occupied portion of the length of the transaction queue will drop below the transaction queue threshold for the duration includes subtracting an offset from the transaction queue threshold.

[0082] Example 9: The method as described in Example 7, wherein determining includes the memory controller determining the second clock frequency through iterative calculation using a plurality of other clock frequencies lower than the first clock frequency, and the plurality of other clock frequencies are determined to have an analog occupancy portion of the length of the transaction queue that is greater than or equal to the transaction queue threshold reaching the duration.

[0083] Example 10: The method as described in any one of Examples 7 to 9, wherein the memory includes a main memory, and the main memory includes a dynamic random access memory.

[0084] Example 11: The method as described in any one of Examples 7 to 9, wherein the memory includes a cache memory, and the cache memory includes a static random access memory.

[0085] Example 12: The method as described in any one of Examples 7 to 9, wherein the memory shares a system-on-chip integrated circuit die with a processor.

[0086] Example 13: A method performed by an electronic device, the method including: determining by a first memory controller of a first memory of the electronic device that a transaction queue threshold has been violated for a duration, the transaction queue threshold corresponding to an occupancy portion of the length of a transaction queue for accessing a second memory of the electronic device; and in response to the determination, sending, by the first memory controller, a message to a second memory controller of the electronic device, the message including an instruction indicating that the second memory controller change a clock frequency to vary a rate of accessing the second memory.

[0087] Example 14: The method as described in Example 13, wherein the transaction queue threshold or the duration includes a variable input by a user of the electronic device.

[0088] Example 15: The method as described in Example 13 or Example 14, wherein the transaction queue is an outgoing transaction queue.

[0089] Example 16: The method as described in any one of Examples 13 to 15, wherein the first memory includes a cache memory and the second memory includes a main memory.

[0090] Example 17: The method as described in any one of Examples 13 to 15, wherein the first memory includes a cache memory and the second memory includes another cache memory.

[0091] Example 18: The method as described in any one of Examples 13 to 17, wherein the first memory and the second memory share a system-on-chip integrated circuit die with a processor.

[0092] Example 19: The method according to any one of Examples 13 to 18, wherein: the transaction queue threshold is an upper threshold; violating the transaction queue threshold for a duration includes exceeding the transaction queue threshold for a duration; and changing the clock frequency increases the clock frequency to increase the rate of accessing the second memory.

[0093] Example 20: The method according to any one of Examples 13 to 18, wherein: the transaction queue threshold is a lower threshold; violating the transaction queue threshold for a duration includes dropping below the transaction queue threshold for a duration; and changing the clock frequency decreases the clock frequency to decrease the rate of accessing the second memory.

[0094] Example 21: A computer-readable storage medium comprising computer-executable instructions that, when executed by a computer, will cause the computer to perform the method according to any one of the preceding examples.

[0095] Example 22: A computer system comprising: one or more processors; and a computer-readable storage medium according to Example 21.

[0096] Although implementations and apparatus for using transaction queue occupancy to change the clock frequency controlling access to the memory of an electronic device have been described, the subject matter of the appended claims need not be limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example implementations for using transaction queue occupancy to change the clock frequency controlling access to the memory of an electronic device.

Claims

1. A method performed by a memory controller, the method comprising: Detecting that a transaction queue threshold is violated, the transaction queue threshold corresponding to an occupied portion of the length of a transaction queue for accessing a memory; In response to the detection, starting a counter to measure a duration, the counter based on a clock frequency that controls a rate of accessing the memory; Determining that the transaction queue threshold continues to be violated for the duration; And In response to the determination, changing the clock frequency.

2. The method according to claim 1, wherein: The transaction queue threshold includes an upper threshold; Violating the transaction queue threshold for the duration includes exceeding the transaction queue threshold for the duration; And Changing the clock frequency includes increasing the clock frequency such that a rate of accessing the memory is increased.

3. The method according to claim 1, wherein: The transaction queue threshold includes a lower threshold; Violating the transaction queue threshold for the duration includes falling below the transaction queue threshold for the duration; And Changing the clock frequency includes decreasing the clock frequency such that a rate of accessing the memory is decreased.

4. The method according to any one of claims 1 to 3, wherein, The memory includes a main memory, and the main memory includes a dynamic random access memory.

5. The method according to any one of claims 1 to 3, wherein The memory includes a cache memory, and the cache memory includes a static random access memory.

6. The method according to any one of claims 1 to 3, wherein The memory shares an on-chip system integrated circuit die with a processor.

7. A method performed by a memory controller, the method comprising: Calculating, for a second clock frequency that is lower than a first clock frequency currently controlling a rate of accessing a memory, a number of clock cycles consumed by performing transactions with the memory, the calculated number of clock cycles consumed by performing transactions with the memory corresponding to an analog occupied portion of the length of a transaction queue for accessing the memory; Based on the calculated number of clock cycles, determining that the analog occupied portion of the length of the transaction queue will fall below a transaction queue threshold for a duration; And In response to the determination, reducing a rate of accessing the memory to the second clock frequency.

8. The method according to claim 7, wherein The determining includes subtracting an offset from the transaction queue threshold.

9. The method according to claim 7, wherein The determining includes the memory controller determining the second clock frequency through iterative calculations using a plurality of other clock frequencies that are lower than the first clock frequency, the plurality of other clock frequencies being determined to have an analog occupied portion of the length of the transaction queue that is greater than or equal to the transaction queue threshold for the duration.

10. A method performed by an electronic device, the method comprising: Determining, by a first memory controller of a first memory of the electronic device, that a transaction queue threshold is violated for a duration, the transaction queue threshold corresponding to an occupied portion of the length of a transaction queue for accessing a second memory of the electronic device; And In response to the determination, sending, by the first memory controller to a second memory controller of the electronic device, a message including an instruction indicating that the second memory controller change a clock frequency to vary a rate of accessing the second memory.

11. The method according to claim 10, wherein, The transaction queue threshold includes a variable input by a user of the electronic device.

12. The method according to claim 10, wherein, The duration includes a variable input by a user of the electronic device.

13. The method according to any one of claims 10 to 12, wherein, The transaction queue is an outgoing transaction queue.

14. The method according to any one of claims 10 to 12, wherein The first memory includes a cache memory, and the second memory includes another cache memory.

15. The method according to any one of claims 10 to 12, wherein The first memory and the second memory share a system-on-chip integrated circuit die with a processor.

16. A computer-readable storage medium including computer-executable instructions that, when executed by a computer, cause the computer to perform the method according to any one of claims 1-15.

17. A computer system, comprising: one or more processors; and the computer-readable storage medium according to claim 16.

Images