Multi-terminal neuromorphic devices

Abstract

Neuromorphic memory elements (100, 200, 300, 706) include memristors, and multiple neuromorphic memory elements (100, 200, 300, 706) and methods for operating the neuromorphic memory elements are provided. The memristor includes an input signal terminal (104), an output signal terminal (106), and a control signal terminal, as well as a memristor active channel (108) comprising a phase change material. The memristor active channel (108) extends longitudinally between the input signal terminal (104) and the output signal terminal (106), and a control signal voltage at the control signal terminal is configured to represent a volatile biological neural process of the neuromorphic memory element (100, 200, 300, 706), and a bias voltage between the input signal terminal (104) and the output signal terminal (106) is configured to represent a non-volatile biological process of the neuromorphic memory element (100, 200, 300, 706).

Description

Background Technology

[0001] This document discloses neuromorphic memory elements including memristors, and more specifically, neuromorphic memory elements that mimic synaptic brain behavior. This disclosure particularly relates to a plurality of neuromorphic memory elements and methods for operating neuromorphic memory elements including memristors.

[0002] Data analytics continues to thrive due to the ever-increasing availability of information in the scientific community and businesses. To analyze the growing portion of unstructured or semi-structured data, artificial intelligence techniques are used (very often in the form of machine learning systems). Machine learning systems are frequently implemented as artificial neural network systems based on the classic von Neumann architecture. This architecture typically performs a loop of extracting commands / data, executing them, and optionally storing the returns. The CPU (Central Processing Unit) is connected to system memory via a bus system.

[0003] Compared to the conventional von Neumann architecture, the human brain comprises a vast number of neurons with synapses, each of which acts as both a computational and memory system, thus functioning as an intracellular computational system within biological memory. This unique structure makes the brain extremely energy-efficient in processing emotions, learning, and thinking. For example, simulating five seconds of brain activity using a state-of-the-art supercomputer operating at 20W of power takes approximately several hundred seconds and might require kW or even up to MW of power. In the circuitry of this natural neural network, neurons integrate inputs from other neurons, while synapses relay the signals. There are orders of magnitude more synapses than neurons, and the processes of learning and memory within the network are associated with synapses (synaptic efficiency or weights). Summary of the Invention

[0004] According to one aspect of the present invention, a neuromorphic memory element including a memristor is provided. The memristor may include an input signal terminal, an output signal terminal, and a control signal terminal. The neuromorphic memory element may further include a memristor active channel comprising a phase change material, wherein the memristor active channel extends longitudinally between the input signal terminal and the output signal terminal.

[0005] The control signal voltage at the control signal terminal can be configured to represent a volatile biological neural process of the neuromorphic memory element, and the bias voltage between the input signal terminal and the output signal terminal can be configured to represent a non-volatile biological neural process of the neuromorphic memory element.

[0006] According to another aspect, a method for operating a neuromorphic memory element including a memristor is provided. The memristor may include an input signal terminal, an output signal terminal, and a control signal terminal, and a memristor active channel including a phase change material. The memristor active channel may extend longitudinally between the input signal terminal and the output signal terminal.

[0007] The method may further include applying a control signal voltage representing a volatile biological neural process of a neuromorphic memory element to a control signal terminal, and applying a bias voltage representing a non-volatile biological neural process of a neuromorphic memory element between an input signal terminal and an output signal terminal. Attached Figure Description

[0008] Embodiments of the invention have been described with reference to different subject matter. Specifically, some embodiments are described with reference to method type claims, while others are described with reference to apparatus type claims. However, those skilled in the art will conclude from the above and below description that, unless otherwise indicated, any combination of features relating to different subject matter (specifically, features of method type claims and features of apparatus type claims) is also considered to be disclosed herein, except for any combination of features belonging to one type of subject matter.

[0009] The aspects defined above, as well as other aspects of this disclosure, will be clear from examples of the embodiments described below and will be explained with reference to examples of the embodiments, but the invention is not limited thereto.

[0010] Different embodiments will be described by way of example only and with reference to the following figures:

[0011] Figure 1 This is a schematic block diagram of an embodiment of a neuromorphic memory element of the present invention, including a memristor, according to some embodiments.

[0012] Figure 2 This is a schematic block diagram illustrating an alternative embodiment of a neuromorphic memory element.

[0013] Figure 3 This is a block diagram illustrating an embodiment having a second top gate and optionally also a third top gate.

[0014] Figure 4A This is a block diagram illustrating the effect of homeoplasticity using a global gate according to some embodiments.

[0015] Figure 4B This is a timing diagram illustrating presynaptic and postsynaptic signals depending on the voltage applied to the global gate, according to some embodiments.

[0016] Figure 5AThis is a block timing diagram illustrating an embodiment of a first method for utilizing a global gate STP according to some embodiments.

[0017] Figure 5B This is a timing diagram illustrating typical signal development during time-simulated device-level STP fatigue according to some embodiments.

[0018] Figure 6 This is a timing block diagram illustrating an embodiment of a second method for utilizing a global gate STP according to some embodiments.

[0019] Figure 7 This is a schematic diagram illustrating an example of embedding multiple neuromorphic memory elements into a cross-shaped array according to some embodiments.

[0020] Figure 8 This is a schematic block diagram illustrating components for operating a cross-shaped array of multiple neuromorphic memory elements according to some embodiments. Detailed Implementation

[0021] The area where driving neuromorphic platforms to enhance existing and enable newer applications is to make neurons and synapses increasingly stimulating to the brain. This may require a radical rethinking of the concept of artificial devices that simulate synaptic dynamics. Several independent processes are known to govern synaptic efficiency, which can be broadly categorized into two classes: long-term plasticity (LTP) and short-term plasticity (STP). Based on this, synaptic efficiency (G) can be expressed as a function:

[0022] G(t) = α(t) ) (t)

[0023] in:

[0024] W(t) represents long-term plasticity (W),

[0025] F(t) represents short-term plasticity (F), and

[0026] α(t) can be associated with changes in the network medium (homeostasis) and can represent multiplicative mathematical operations (e.g., addition, subtraction).

[0027] Homeostasis refers to the global modulation (homeostasis or homeostatic plasticity) of the synaptic basal layer. This is mainly controlled by ion concentration, the concentration of various hormones, and temperature, to name just a few parameters that provide global regulation of synaptic strength and neurite firing.

[0028] W(t) is associated with long-term memory and F(t) with short-term memory, sometimes also representing an effect known as synaptic fatigue / facilitation. Furthermore, neurons can exhibit various temporal dynamics, such as adaptive thresholding and membrane leakage. Therefore:

[0029] T'(t) = α(t) (t) (t);

[0030] in:

[0031] T'(t) represents the dynamic firing threshold of the neuron.

[0032] T(t) represents the resting firing threshold of the neuron, and

[0033] α(t) is related to the changes in the network medium (homeostasis).

[0034] Furthermore, regarding synaptic characteristics, it is known that:

[0035] K'(t) = α(t) (t);

[0036] in

[0037] K'(t) represents the transient voltage trajectory in the postsynaptic signal.

[0038] K(t) represents the presynaptic signal or the postsynaptic decay tail, and

[0039] α(t) can be correlated with changes in the network medium (homeostasis).

[0040] Currently available neuromorphic hardware, synapses, and neural dynamics are typically implemented using conventional CMOS and memristor circuitry. Implementations include two-transistor / one-memristor solutions, as well as one-transistor / one-memristor solutions (e.g., for simulating synapses). One of the challenges of working with fully tunable memristors may require non-memristor circuitry, which complicates device fabrication and is often unrelated to device physics.

[0041] Attempts to simulate the synapses of a projected phase-change memory device with a phase-change memory core have shown that an intermediate layer surrounded by an active channel and then by a gate oxide has proven problematic. For full tunability, the device requires additional material (the active channel), which complicates the fabrication process and reduces the memristor's operating efficiency.

[0042] A third approach can be seen in PCM (phase-change memory) devices, which achieve integral activation of neurons by integrating the input in the PCM conductance state and resetting it once the conductance reaches the activation threshold. In this case, the memristor conductance represents the neuron's membrane potential. However, this solution also has drawbacks: there is no "membrane leakage" that may be needed for some spatiotemporal data computations, and there is no threshold dynamics required for adoptive learning.

[0043] Therefore, current available technical models of synapses or neurons have only limited potential to simulate fully functional synaptic / neuronal networks due to the limited options for modeling neural dynamics. Consequently, neuromorphic devices that allow for better simulation of synaptic activity may be needed.

[0044] In the context of this specification, the following conventions, terms and / or expressions may be used.

[0045] The term "neuromorphic memory element" here can refer to a multi-terminal device that does not require separate PCM and active layers—that is, a memristor device with at least three terminals. Conversely, the PCM layer or core and active channel are identical, omitting one layer of material. Neuromorphic memory elements can be used to mimic synaptic effects known from the mammalian brain.

[0046] The term "memristor" (i.e., a combination of memory and resistor) can refer to a known nonlinear, two-terminal electrical component involving charge and magnetic flux. However, in the concept discussed here, the nonlinear characteristics of a memristor can be affected by an additional gate. The resistance value can be applied between several levels during a write operation. Even if no voltage is applied to the memristor, the resistance value thus programmed retains its value. However, over time, the resistance value may change due to the non-ideal behavior of such a device. The resistance value programmed once can be read, allowing the memristor to be used as a memory or a storage element.

[0047] The term "memristor active channel" can refer to the channel of a PCM connected between the input and output terminals.

[0048] In the context of memristors, the term "phase change material" (PCM) can refer to the transition between states of a material, such as the transition between non-classical (as opposed to the classical states of liquid and solid) states of a substance, such as the uniformity of a crystal, where a material changes from conforming to one crystal structure to conforming to another crystal structure, which can be a higher or lower energy state, i.e., from a crystalline state to an amorphous state exhibiting different electrical conductances.

[0049] The term "volatile biological neural process" can refer to short-term effects, such as, in the context of short-term memory, due to leakage behavior of the neuronal membrane. In the context of synapses, this effect can also be referred to as synaptic fatigue.

[0050] The term "non-volatile biological neural process" can refer to long-term effects associated with long-term memory in the mammalian brain. It can also be referred to as long-term plasticity (LTP).

[0051] The term "long-term plasticity" (LTP) can be associated with synaptic plasticity in brain models (i.e., neuroscience) and can specifically represent the ability of synapses to strengthen or weaken over time, which is important for the neurochemical basis of learning and memory. LTP should not be confused with long-term enhancement, which contrasts with long-term depression (LTD), both of which can be affected in the mammalian brain by the availability of neurotransmitters and hormones, both of which are the basis of long-term (synaptic) plasticity. Typically, LTP effects can last from minutes to hours.

[0052] The term "short-term plasticity" (STP)—specifically, short-term synaptic plasticity as opposed to long-term synaptic plasticity—describes the effect of synaptic activity over a shorter timeframe than long-term synaptic plasticity (LTP). STP can operate on timescales ranging from tens of milliseconds to minutes. Therefore, the effects of STP and LTP can be clearly distinguished. Furthermore, STP can either enhance or weaken synapses.

[0053] The proposed neuromorphic memory element including a memristor, the plurality of neuromorphic memory elements, and the method for operating the neuromorphic memory element can provide several advantages, contributions, and technical effects.

[0054] The proposed solution overcomes the problems found in projected PCM-based synaptic elements, where the phase-change memory is surrounded by an active channel, gate oxide, and an external gate. Such configurations are relatively difficult to fabricate and require a relatively large volume. Furthermore, such configurations may require active channel material, which can be omitted in the proposed solution. Instead, in the proposed device, the active channel and surface-changing material can be the same, thus enhancing the operating efficiency of the memristor and simulating neuronal dynamics.

[0055] By utilizing the inherent field-effect properties of memristors, the proposed method eliminates the need for a projection layer. This reduces material costs, time, and labor, and eliminates complexity in chip design and manufacturing.

[0056] By utilizing a back-gate configuration, the embodiments enable gate-level modulation of neural networks implemented using multiple proposed neuromorphic devices. Specifically, in hybrid devices, the back gate enables global modulation, while selective gates facilitate local modulation specific to individual neuromorphic devices.

[0057] Furthermore, eliminating the core projection layer for the phase-change memory device improves thermal confinement and reduces power consumption. Overall, this leads to a significant improvement in energy consumption for operating the proposed device.

[0058] The field effect introduced by the gate (in any form) can be used to represent the firing threshold of a neuron and to realize a long-term value of the threshold in the non-volatile state of the device, and additionally to achieve a dynamic or adaptive threshold by tuning the gate of the device. In biological context, a neuron integrates presynaptic impulses, and if the accumulation exceeds the firing threshold, it also fires postsynaptic impulses. However, the firing threshold is not constant, and its magnitude changes in adaptive learning patterns.

[0059] The field effect introduced by the device's gate can also be used to realize the properties of leaky neuronal membranes by adding transient nonlinearities to the simulated neurons. In a biological context, the delay in the accumulation and descent of postsynaptic signals is due to the leaky behavior of the neuronal membrane. The voltage trajectory of the leaky integral excitation model is crucial for how most sensing information is processed. If the presynaptic pulse has a vertical edge, the postsynaptic pulse has a circular edge for a leaky membrane.

[0060] In short, a complete lineage of properties that can mimic biological synapses allows for much more natural behavior in artificial neural networks. Both volatile and non-volatile neural processes can be achieved using memristor active channels.

[0061] Further embodiments of the device are described below (and may also be applied to related methods).

[0062] According to some advantageous embodiments of the neuromorphic memory element, the neuromorphic memory element can be configured to simulate long-term plasticity (LTP) dynamics via non-volatile modulation of the memristor conductance during write operations (i.e., during programming operations). The neuromorphic memory element can also be configured to simulate short-term plasticity (STP) dynamics via volatile modulation of the memristor conductance during read operations. Thus, the neuromorphic memory element can be configured to simulate neuronal dynamics via volatile modulation of the memristor conductance during both read and write operations. Therefore, this novel neuromorphic device allows for the simulation or emulation of the full complex behavior of natural biological synapses, including short-term, long-term local, and global effects. This makes the device ideal for better constructing artificial neural networks.

[0063] According to some embodiments of neuromorphic memory devices, a memristor device may include a top surface and a back surface, a first dielectric material layer above the top surface of a carrier material, and source and drain terminals connected by a memristor active channel above the dielectric material. Furthermore, the memristor device may include a back gate below the first dielectric material layer. A carrier material may be disposed between the first dielectric material layer and the back gate. This carrier material may include a silicon-based material. Additionally, the back gate may also include a conductive material.

[0064] According to some embodiments of neuromorphic memory elements, a memristor device may include a carrier material having: a source terminal and a drain terminal connected by a memristor-type active channel over the carrier material; a dielectric material layer over the memristor-type active channel; and a control gate over the dielectric material layer.

[0065] These embodiments can be considered as direct replacements for the previously described embodiments. However, here, the back gate can be replaced by a control gate on the active channel and can be used in the same manner as described below, for example as a global gate for a plurality of neuromorphic memory elements having a common top control gate.

[0066] According to some alternative embodiments of the neuromorphic memory element, the carrier material can be conductive and can be directly used as the back gate. Therefore, the carrier material and the back gate can be the same. This reduces the manufacturing effort and cost of the neuromorphic memory element. However, in the selected case, a version of the neuromorphic memory element with an explicit carrier material may be a more practical approach, for example, if other active elements (e.g., in CMOS technology) can be integrated with one or more of the neuromorphic memory element.

[0067] According to other alternative embodiments of the neuromorphic memory element, the carrier material may be a metal or a highly doped semiconductor (e.g., highly doped silicon). Conductive silicon (or another semiconductor) may be attached to a connection terminal to provide a wired-to-gate voltage source.

[0068] According to other alternative embodiments of the neuromorphic memory device, the carrier material may be a silicon substrate, and the back gate may be a conductive layer above the back surface of the silicon substrate. The conductive layer on the back side of the silicon substrate (or another semiconductor as the carrier material) can typically be a metal gate.

[0069] According to embodiments of some alternative designs, a neuromorphic memory element may include a second dielectric material layer over a memristor active channel and a first top gate over the second dielectric material layer. However, another material layer may be located between the active channel and the second dielectric material layer. The first top gate, in addition to or besides the back gate, may also affect characteristics. Specifically, the voltage applied to the back gate and / or the alternative top gate may both represent transient effects (i.e., short-term plasticity dynamics) of the artificial synapse (i.e., the neuromorphic memory element).

[0070] According to another design and therefore some further alternative embodiments of neuromorphic memory elements, the memristor device may also include a second top gate adjacent to a first side of the memristor active channel. The second top gate may also be located on the same dielectric layer as the active channel. Thus, in terms of the carrier material, the second top gate is not above the active channel, but rather beside it. It may also be referred to as a side gate, as it may be located on one side of the active channel in the same horizontal plane.

[0071] Additionally, according to an additional embodiment of the neuromorphic memory, the memristor device may further include a third top gate, which is located on the side of the memristor active channel opposite to the second top gate and adjacent to a second side of the memristor active channel. The second and third top gates can be configured in another form. Therefore, the active channel can be located between the second and third top gates. Thus, the second top gate, the active channel, and the third top gate can all be positioned above the dielectric layer, i.e., in the same horizontal plane.

[0072] Some advanced embodiments of the present invention may also include multiple neuromorphic memory elements, wherein the control signal terminal may be shared by multiple neuromorphic memory elements. Thus, the control signal terminal can be adapted to simulate more global effects of volatile biological neural processes. Therefore, individual memristors of different neuromorphic memory elements can be selected one after another, but a global control terminal (i.e., gate signal) may be sufficient to handle a larger number of neuromorphic memory elements at once.

[0073] The conductance of a memristor can decrease or increase depending on the polarity of the gate voltage. If the global gate and the top gate have different polarities, the field effect on the memristor may be ineffective.

[0074] A detailed description of the accompanying drawings is given below. The instructions in the drawings are schematic. First, a block diagram of an embodiment of the neuromorphic memory element of the present invention is given. Then, further embodiments of the plurality of memristors and the plurality of neuromorphic memories, as well as embodiments of a method for operating a neuromorphic memory element including memristors, will be described.

[0075] Figure 1 An embodiment of a neuromorphic memory element 100 is shown. It includes a memristor comprising an input signal terminal 104, an output signal terminal 106, and a control signal terminal 110. Between the input signal terminal 104 and the output signal terminal 106, a memristor active channel 108 (i.e., a channel element) includes a phase-change material serving as an active channel. The memristor active channel extends longitudinally between the input signal terminal and the output signal terminal; that is, its extension perpendicular to a first direction defined by the line between the input signal terminal 104 and the output signal terminal 106 is less than its extension in the first direction.

[0076] Thus, the control signal voltage Vgs at the control signal terminal is configured to represent the volatile biological neural process of the neuromorphic memory element, and the bias voltage Vd between the input signal terminal and the output signal terminal is configured to represent the non-volatile biological neural process of the neuromorphic memory element.

[0077] The neuromorphic memory element 100 may further include (for physical stability) a carrier material 102 (e.g., a silicon-like semiconductor) and a dielectric layer 112 between the carrier material 102 on one side and the input signal terminal 104, active channel 108, and output signal terminal 106 on the other side. Therefore, the input signal terminal 104, the active channel 108 (as a PCM), and the output signal terminal 106 are located in a single plane, i.e., above the dielectric layer 112. The second terminal of the control signal voltage Vgs and the input signal terminal 104 may also be grounded.

[0078] Figure 2 An alternative embodiment 200 of the neuromorphic memory element is shown. Besides in Figure 1 In addition to the elements already discussed in the context, a second dielectric layer 202 lies above the active channel 108, which includes memristor material. The second dielectric layer 202 isolates the top gate 204 from the active channel 108. In this configuration, a short-term dynamic plasticity neuromorphic memory element can be simulated via the top gate. Because the second dielectric layer 202 can be much thinner than the carrier material 102 (i.e., the substrate), the top gate can be much smaller and may require a smaller amount of charge to affect the active channel 108 compared to the control signal terminal 110 (i.e., the back gate) on the other side of the carrier material 102.

[0079] However, a single control signal terminal 110 (i.e., the back gate) can actively influence multiple neuromorphic memory elements 100, representing global modulation of the array of neuromorphic memory elements 100 at the chip or wafer level. Alternatively, the top gate can also be used for the same purpose. Purely local modulation can also be achieved through the embodiment shown in the figure below.

[0080] Figure 3 An embodiment 300 is shown, having a second top gate 302 and optionally also a third top gate 304. Figure 1 and 2 Compared to (a side view of a cross-section), Figure 3 This is a top view of the neuromorphic memory element 100. The active channel 108 is located here between the second top gate 302 and the third top gate 304. Both top gates 302 and 304 can also be positioned on the control signal terminal 110 (i.e., the back gate or dielectric layer). The second top gate 302 and the third top gate 304 can advantageously be used for localized modulation of the active channel 108, i.e., operating at a separate device level. In this configuration, the first top gate can be additionally positioned at the top of the active channel, such as... Figure 2 As shown. In addition, in other configurations, a control signal terminal 110 (i.e., the back gate) may also be present.

[0081] Therefore, in any case, the neuromorphic memory element 100 is at least a three-terminal device. The input signal terminal 104 can also be represented as the drain, and the output signal terminal 106 can also be represented as the source. The third terminal (i.e., the gate or control terminal) can be unique for a single neuromorphic memory element's memristor, or shared by multiple memristors in several different neuromorphic element units (NMEs). Each NME can thus simulate LTP dynamics via non-volatile modulation of memristor conductance during write (programming) operations; each NME can simulate STP dynamics via volatile modulation of memristor conductance during read operations. Furthermore, each NME can simulate neurodynamics via volatile modulation of memristor conductance during both read and write operations.

[0082] Figure 4A The effect of homologous plasticity using a global gate is shown. Figure 4A An arrangement 400 of presynaptic element 404 and postsynaptic element 406 is shown, while the combination of element 408 with the connection shown in rectangle 402 represents an artificial synapse and its corresponding synaptic effect. In mammals, global brain mechanisms regulate neural processing, namely, homologous plasticity. Ion concentration, the concentration of various hormones, and temperature are some of the parameters that provide global regulation of synaptic strength and neuronal firing. Homologous plasticity can be rendered using a global dating scheme with neuromorphic chips. These so-called global clock concepts can be used for adaptive learning, where neuronal firing can be enhanced or inhibited. This is analogous to the increased and inhibited responses of mammalian synapses to psychotropic drugs.

[0083] Figure 4BThe presynaptic signal 410 and postsynaptic signal 414, depending on the voltage 410 applied to the global gate, are shown. When no voltage is applied to the global gate, the amplitudes of the presynaptic signal 410 and the postsynaptic signal 414 can be considered to be at 100% level. However, if a positive voltage 410 is applied to the global gate during time period 416, the postsynaptic signal 414 is clearly shown to be below 100% level.

[0084] On the other hand, if a negative voltage 410 is applied to the global gate during time period 418, the postsynaptic signal 414 is clearly shown to be above 100%. After time period 418 and without a gate voltage signal 412, the presynaptic signal 410 and the postsynaptic signal 414 are again at their respective 100% levels. Therefore, the postsynaptic signal 414 can be increased or decreased globally for a single neuromorphic memory element or for multiple neuromorphic memory elements, depending on the gate design.

[0085] Figure 5A An embodiment 500 of a first method for utilizing a global gate STP is shown, wherein an asynchronous input X is used to address the R of a neuromorphic device. Line 502 symbolizes the input signal pulse X(t). i The input lines (e.g., at times t3, t2, t1), namely X(t3), X(t2), X(t1), are used as inputs for reading and writing operations on weights to be read from or written to (i.e., programmed) from the corresponding memristors. Two units (modulation signal selector 504 and 2-terminal input routing module 506) control which signals will reach a specific memristor among memristors 508, 510, and 512 (indicated by switch 514). The two terminals mentioned above are the source and drain of the aforementioned devices.

[0086] The inputs to the two terminals and the global gate are asynchronous to each other. For time t i 2-terminal input pulse (X(t) i ), R j ), at time t i To device R j The input to the third terminal (i.e., the gate) must be equal to f. j (t i (That is, R(t) is the input to the encoded f). At other times, it can be any other signal. Therefore, it can be F0=0 or it can be f. k , k≠j. Therefore, if it is true at each time t i By switching the relevant signal, a single global signal can be used at the gates of all memristor devices. This is the task of modulation signal selector 504. Symbol 516 shows the correlation function value f over time.

[0087] Figure 5B The diagram illustrates typical signal development during level STP fatigue in a time-simulation device, which can be understood as a transient decrease in synaptic efficacy from the applied volatile effect triggered when the presynaptic input arrives. Signal 518 represents the input signal pulse, signal 520 represents the output signal without an applied gate voltage, and signal 522 represents the output signal with an applied gate voltage (as selected by modulation signal selector 502).

[0088] Figure 6 An embodiment 600 of a second approach for STP using a global gate is shown, wherein an asynchronous input X is used to address R of the neuromorphic device. Apart from only minor differences, if compared with... Figure 5A In contrast, the same reference numerals are used, and no further detailed description is provided.

[0089] Furthermore, jitter is introduced. By making the two-terminal input jitter non-overlapping while still using a global signal switching scheme, the jitter must either: (i) be small in time dynamics relative to the gate modulation signal, or (ii) also be applied to the gate terminal. Furthermore, the jitter must be small in time dynamics relative to the two-terminal input.

[0090] Therefore, the synapse that needs to remain immune to global gate action can be used in parallel with the global gate input and can be modulated with the top gate (as described above), but with a gate polarity opposite to the field effect from the bottom gate. Figure 5A and Figure 6 The main difference lies in how the input signal X(t) of the memristor R(t) at 602 and the modulation signal selector 504 work.

[0091] Figure 7 An example of embedding multiple neuromorphic memory elements 706 into a cross-array 700 is shown. The cross-array 700 includes horizontal word lines 702 (only one of which has a reference label) and vertical bit lines 704 (only one of which has a reference label) for addressing multiple neuromorphic memory elements 706 at corresponding cross-points. Word lines 702 and bit lines 704 are used to address the corresponding neuromorphic memory element 706 (or, as also example, 708). Word lines 702 can be activated by terminals 714, 716, and 718. The terminals of bit lines 704 are not explicitly shown. The cross-array represents an m x n matrix with a range from G... 11 To G m1 Down to G n1 To G nm The row of the neuromorphic memory element 706.

[0092] Furthermore, gate contacts 712 (e.g., for the lower right corner of a cross-array) are shown for each neuromorphic memory element 706. These gate contacts are diagonally connected compared to word lines 702 and bit lines 704. Diagonal gate lines (not explicitly labeled) connect multiple neuromorphic memory elements 706 across the diagonally located intersections of word lines 702 and bit lines 704. Gate voltages can be applied to gate terminals 720, ..., 730. The corresponding gate voltages will only become effective for the addressed neuromorphic memory element 706. The gate can be any gate selected from the back gate and any type of top gate. Additionally, parallel gate lines can be present to distinguish between the back gate and the top gate.

[0093] Figure 8 A component 800 for operating a cross-array 700 containing multiple neuromorphic memory elements is shown. Word lines (only three are shown) are connected to a digital-to-analog converter 802 to convert read or write commands into pulses 804. Bit lines are connected to an amplifier 806, which in turn is connected to an analog-to-digital converter 808. In this way, the cross-array 700 can be processed digitally, and the results of the cross-array can also be processed digitally.

[0094] Furthermore, symbolically, connections to the gate line are shown, while the digital-to-analog converter 810 connected to the global gate contacts the neuromorphic memory element 706 of the cross-type array 700. Additionally, an additional digital-to-analog converter 812 is shown for addressing local gates (typically implemented as top gates) in... Figure 7 and Figure 8 (Not explicitly shown in the image). These gates are controlled by a volatile signal 814, symbolically shown as a signal that decreases over time.

[0095] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements over those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. Any advantages of a particular embodiment are not necessarily applicable to all embodiments, and a particular embodiment does not require the use of all the advantages discussed herein.

[0096] This disclosure may cover systems and methods, and / or may be implemented in conjunction with a computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to execute aspects of the invention.

[0097] The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system used for propagation. Examples of computer-readable media can include semiconductor or solid-state memory, magnetic tape, removable computer disks, random access memory (RAM), read-only memory (ROM), rigid disks, and optical discs. Current examples of optical discs include compact disc-read-only memory (CD-ROM), compact disc-read / write (CD-R / W), DVDs, and Blu-ray discs.

[0098] Computer-readable storage media can be tangible means for retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital universal disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or protrusions in slots having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0099] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0100] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may be personalized to execute computer-readable program instructions by utilizing state information from the computer-readable program instructions in order to perform aspects of this invention.

[0101] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0102] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions includes an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0103] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0104] The flowcharts and / or block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0105] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It should also be understood that when the terms “comprises” and / or “comprising” are used in this specification, they specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0106] All means or steps in the following claims, plus corresponding structures, materials, actions, and equivalents of the functional elements, are intended to include any structure, material, or action for performing the said function in conjunction with other claimed elements as specifically claimed. The description of the invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. These embodiments were chosen and described in order to best explain the principles and practical application of the invention, and to enable others skilled in the art to understand different embodiments of the invention with different modifications, as suited to the particular intended use.

Claims

1. A neuromorphic memory element including a memristor, the memristor comprising: Input signal terminals; Output signal terminals; Control signal terminals; Including memristor active channels made of phase change materials; in: The memristor active channel extends longitudinally between the input signal terminal and the output signal terminal; The control signal at the control signal terminal is configured to represent the volatile biological neural processes of the neuromorphic memory element; and The bias voltage between the input signal terminal and the output signal terminal is configured to represent a non-volatile biological neural process of the neuromorphic memory element. The memristor further includes: A carrier material having a top surface and a back surface; A first dielectric material layer above the top surface of the carrier material; The source and drain terminals are connected via the memristor active channel above the first dielectric material layer; and The back gate located below the first dielectric material layer.

2. The neuromorphic memory element according to claim 1, wherein, The neuromorphic memory element is configured to simulate: Long-term plasticity dynamics during write operations via non-volatile modulation of the memristor conductance of the memristor; Short-term plastic dynamics during read operations via volatile modulation of the memristor conductance; as well as Neuronal dynamics during the read and write operations via volatile modulation of the memristor conductance.

3. The neuromorphic memory element according to claim 1, wherein, The carrier material is conductive, and wherein the carrier material is the back gate.

4. The neuromorphic memory element according to claim 3, wherein, The carrier material is a metal or a highly doped semiconductor.

5. The neuromorphic memory element according to claim 1, wherein, The carrier material is a silicon substrate, and the back gate is a conductive layer on the back surface of the silicon substrate.

6. The neuromorphic memory element according to claim 1, further comprising: A second dielectric material layer above the memristor active channel; as well as The first top gate above the second dielectric material layer.

7. The neuromorphic memory element according to claim 1, wherein, The memristor further includes a second top gate adjacent to the first side of the memristor active channel.

8. The neuromorphic memory element according to claim 7, wherein, The memristor further includes a third top gate, which is adjacent to a second side of the memristor active channel and is located on the side of the memristor active channel opposite to the second top gate.

9. A plurality of said neuromorphic memory elements, each of which is a neuromorphic memory element according to claim 1. in, The control signal terminal is shared by multiple neuromorphic memory elements.

10. A method for operating a neuromorphic memory element including a memristor, the memristor comprising: Input signal terminals; Output signal terminals; Control signal terminals; The memristor active channel, comprising a phase change material, extends longitudinally between the input signal terminal and the output signal terminal; The method includes: A control signal voltage representing a volatile biological neural process of the neuromorphic memory element is applied to the control signal terminal; and A bias voltage representing a non-volatile biological neural process of the neuromorphic memory element is applied between the input signal terminal and the output signal terminal. The memristor further includes: A carrier material having a top surface and a back surface; A first dielectric material layer above the top surface of the carrier material; The source and drain terminals are connected via the memristor active channel over the dielectric material; and The back gate located below the first dielectric material layer.

11. The method of claim 10, further comprising emulation via the neuromorphic memory element: Long-term plasticity dynamics during write operations via non-volatile modulation of the memristor conductance of the memristor; Short-term plastic dynamics during read operations via volatile modulation of the memristor conductance; as well as Neuronal dynamics during the read and write operations via volatile modulation of the memristor conductance.

12. The method of claim 10, wherein: The carrier material is conductive; and The carrier material is the back gate.

13. The method according to claim 12, wherein, The carrier material is a metal or a highly doped semiconductor.

14. The method of claim 10, wherein: The carrier material is a silicon substrate; and The back gate is a conductive layer on the back surface of the silicon substrate.

15. The method of claim 10, wherein, The memristor further includes: A second dielectric material layer above the memristor active channel; and The first top gate above the second dielectric material layer.

16. The method of claim 10, wherein, The memristor further includes: The second top gate adjacent to the first side of the memristor active channel.

17. The method according to claim 16, wherein, The memristor includes: The third top gate is adjacent to the second side of the memristor active channel and is located on the side of the memristor active channel opposite to the second top gate.

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