Robust link synchronization in Ethernet networks

Abstract

The second device receives a first synchronization signal transmitted by the first device for training synchronization between the second device and the first device. The second device then transmits one or more initial synchronization response signals to the first device. The one or more initial synchronization response signals are from a fixed number of synchronization response signals that the second device is configured to transmit to the first device. After transmitting the one or more initial synchronization response signals, the second device receives a second synchronization signal from the first device. After receiving the second synchronization signal, the second device continues to transmit synchronization response signals to the first device until the fixed number of synchronization response signals are transmitted from the second device to the first device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 083630, filed on September 25, 2020, entitled “Enhancing Robustness of LinkSynchronization in Automotive Ethernet,” which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to Ethernet communication systems, and more particularly to training synchronization between network devices in an Ethernet communication system operating in a noisy environment. Background Art

[0004] Modern vehicles, such as advanced automobiles, have begun using automotive Ethernet technology to connect components via a wired physical network within the vehicle. A key requirement of automotive Ethernet networks is the startup time of the Ethernet network components. Typically, vehicle network components need to be linked and operational within a certain period of time after the vehicle is started (for example, within one hundred or several hundred milliseconds after the vehicle is started), allowing the vehicle to be fully operational within a certain period of time after the vehicle is started (such as no more than two seconds). The linking process in automotive applications typically includes a synchronization phase followed by a training phase. During the synchronization phase, a device operating as a master device sequentially transmits one or more synchronization signals, wherein transmission pauses separate the respective transmissions of the synchronization signals. When a device operating as a slave device detects the synchronization signal transmitted by the master device, the slave device transmits a synchronization response signal to the master device. After the master device detects the synchronization response signal from the slave device, the master device stops transmitting its synchronization signal to the slave device. After the synchronization signal exchange between the master and slave devices is completed, the master device initiates the training phase of the linking process by transmitting a training signal to the slave device.

[0005] However, in some cases, the master device may miss the detection of the synchronization signal transmitted by the slave device, for example due to transient noise that may temporarily exist on the link between the master device and the slave device. In this case, the master device will continue the transmission of the synchronization signal, for example until the expiration of a timer set at the master device. Because the slave device is in training mode, the slave device will no longer transmit the synchronization signal to the master device. The link between the master device and the slave device will therefore fail and will be restarted, which in turn may result in a violation of the link timing requirements of the automotive network. The possibility of a link failure due to the master device missing the detection of the synchronization signal increases as the physical length of the link between the master device and the slave device (e.g., cable length) increases; in other words, longer Ethernet cables are more susceptible to noise that may be present in the automotive network, which in turn may affect the ability to synchronize timing between link partners. Summary of the Invention

[0006] In one embodiment, a method for training synchronization between a first network interface device and a second network interface device includes: receiving, at the second network interface device, a first synchronization signal transmitted by the first network interface device, the synchronization signal being used to train synchronization between the second network interface device and the first network interface device; in response to receiving the first synchronization signal from the first network interface device, transmitting, using the second network interface device, one or more initial synchronization response signals to the first network interface device, the one or more initial synchronization response signals being selected from a fixed number of synchronization response signals that the second network interface device is configured to transmit to the first network interface device; after transmitting the one or more initial synchronization response signals, receiving a second synchronization signal from the first network interface device; and, after receiving the second synchronization signal, continuing to transmit synchronization response signals from the second network interface device to the first network interface device until the fixed number of synchronization response signals are transmitted from the second network interface device to the first network interface device.

[0007] In another embodiment, an apparatus includes a second network interface device for coupling the apparatus to a first network interface device via a network link. The second network interface device includes a physical layer (PHY) processor implemented on one or more IC devices, the physical layer (PHY) processor being configured to: receive a first synchronization signal transmitted by the first network interface device, the first synchronization signal being used to train synchronization between the second network interface device and the first network interface device; in response to receiving the first synchronization signal from the first network interface device, transmit one or more initial synchronization response signals to the first network interface device, the one or more initial synchronization response signals being selected from a fixed number of synchronization response signals that the second network interface device is configured to transmit to the first network interface device; after transmitting the one or more initial synchronization response signals, receive a second synchronization signal from the first network interface device; and after receiving the second synchronization signal, continue transmitting synchronization response signals to the first network interface device until the fixed number of synchronization response signals are transmitted from the second network interface device to the first network interface device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an example system in which a slave device is configured to transmit a plurality of synchronization response signals during a synchronization procedure establishment between a master device and a slave device, according to one embodiment.

[0009] Figure 2 According to one embodiment, Figure 1 FIG2 is an example timing diagram of a synchronization signal handshake sequence performed during the synchronization phase of link establishment between a master device and a slave device.

[0010] Figure 3 According to one embodiment, Figure 1 A diagram of a synchronization sequence performed during the synchronization phase of a link establishment process between a master device and a slave device of a system.

[0011] Figure 4 is a diagram illustrating a method according to an embodiment of the present invention. Figure 1 A state diagram showing example states and state transitions during a synchronization procedure between a master and slave devices.

[0012] Figure 5 According to one embodiment, for training Figure 1 A flow chart of an example method for synchronization between a master device and a slave device. DETAILED DESCRIPTION

[0013] In various embodiments described below, link establishment between a first network device (e.g., a master device) and a second network device (e.g., a slave device) in an Ethernet network includes transmitting multiple synchronization signals from the slave device to the master device. For example, in the presence of transient noise on the link between the master device and the slave device, transmitting multiple synchronization signals from the slave device to the master device increases the probability that the master device detects the synchronization signals from the slave device. For example, in one embodiment, if the master device misses detection of one or more initial synchronization signals from the slave device due to, for example, transient noise on the link between the master device and the slave device, the master device will detect subsequent synchronization signals from the multiple synchronization signals transmitted by the slave device. Therefore, in at least some embodiments, transmitting multiple synchronization signals from the slave device to the master device reduces or eliminates the probability of link failure in a link establishment procedure performed between the master device and the slave device.

[0014] In one embodiment, the slave device is configured to transmit a predetermined fixed number of synchronization signals to the master device. In some scenarios, in one embodiment, after transmitting one or more initial synchronization signals from the fixed predetermined number of synchronization signals to the master device, the slave device receives the synchronization signal from the master device. In one embodiment, after transmitting the one or more initial synchronization signals to the master device, receiving the synchronization signal from the master device generally indicates that the master device missed detecting the one or more initial synchronization signals from the slave device. In response to receiving the synchronization signal from the master device after transmitting the one or more initial synchronization signals to the master device, the slave device continues to transmit multiple synchronization response signals to the master device until the predetermined fixed number of synchronization signals are transmitted from the slave device to the master device. In one embodiment, the slave device continues to transmit the predetermined fixed number of synchronization response signals to the master device without restarting the transmission of the predetermined fixed number of synchronization signals to the master device. In one embodiment, continuing to transmit the synchronization signal to the master device without restarting the transmission of the predetermined fixed number of synchronization signals to the master device ensures that the transmission of the predetermined fixed number of synchronization response signals will not be restarted due to an erroneous detection of the synchronization signal from the master device.

[0015] Figure 11 is a block diagram of an example system according to one embodiment, in which a slave device is configured to transmit multiple synchronization signals during a synchronization procedure in link establishment between a master device and a slave device. System 100 includes a first network interface device 102 coupled to a second network interface device 104 via a network link 106. In one embodiment, first network interface device 102 and second network interface device 104 are generally configured to operate according to an automotive Ethernet standard, such as the IEEE 802.3 standard. In another embodiment, first network interface device 102 and second network interface device 104 are generally configured to operate according to one or more other suitable communication protocols.

[0016] In one embodiment, the first network interface device 102 and the second network interface device 104 are associated with electronic devices of a vehicle network system. By way of example only, in one embodiment, the first network interface device 102 is associated with an accessory device (such as a camera or telematics radio) in the vehicle, and the second network interface device 104 is associated with a central processing unit in the vehicle. In other embodiments, the first network interface device 102 and / or the second network interface device 104 are associated with other suitable electronic devices in the vehicle, such as infotainment devices, sensor devices (e.g., lidar devices, radars, audio sensors, video sensors, proximity sensors, etc.), control devices, etc. In one embodiment, the network link 106 between the network interface device 102 and the network interface device 104 comprises a single twisted-pair copper link. In another embodiment, the network link 106 is a suitable link other than a single twisted-pair copper link. For example, in various embodiments, the network link 106 is a multi-pair copper link, an optical link, a fiber optic link, a radio frequency plastic waveguide link, etc. In some embodiments, the first network interface device 102 and the second network interface device 104 are used in a network other than the vehicle network. For example, in some embodiments, the first network interface device 102 and the second network interface device 104 are used in an industrial or process industry network.

[0017] The network interface device 102 includes one or more physical layer (PHY) processors 130 (sometimes referred to herein as "PHY processors 130" for brevity). The PHY processors 130 include a transceiver 180 configured to transmit and receive signals over the link 106. In one embodiment, the network interface device 102 also includes one or more medium access control (MAC) processors 132 (sometimes referred to herein as "MAC processors 132" for brevity) coupled to the PHY processors 130. In another embodiment, the network interface device 102 omits the MAC processors 132. For example, in one embodiment, the MAC processors 132 are external to the network interface device 102. In various embodiments in which the MAC processors 132 are external to the network interface device 102, the MAC processors 132 may be co-located on the same printed circuit board (PCB) as the PHY processors 130, or may be located on a separate PCB from the PHY processors 130.

[0018] According to one embodiment, the PHY processor 130 includes one or more encoder devices (not shown), a scrambler device (not shown), and a modulator (not shown) for encoding, scrambling, and modulating data as part of generating a transmission signal. According to one embodiment, the PHY processor 130 also includes a demodulator (not shown), a descrambler device (not shown), and one or more decoder devices (not shown) for demodulating, descrambling, and decoding as part of generating received data. In some embodiments, the PHY processing device 130 also includes an analog-to-digital converter (hereinafter referred to as "ADC", not shown), which converts an analog signal received via a communication medium into a digital signal. In some embodiments, the PHY processor 130 also includes a digital signal processor (hereinafter referred to as "DSP", not shown), which processes the digital signal to generate a signal corresponding to the modulation symbol, which is then demodulated by the demodulator (not shown).

[0019] The network interface device 102 is implemented using one or more integrated circuits (ICs) configured to operate as described below. For example, the PHY processor 130 may be implemented at least in part on a first IC, and the MAC processor 132 may be implemented at least in part on a second IC. As another example, at least a portion of the PHY processor 130 and at least a portion of the MAC processor 132 may be implemented on a single IC. For example, the network interface device 102 may be implemented using a system on a chip (SoC), wherein the SoC includes at least a portion of the PHY processor 130 and at least a portion of the MAC processor 132. In one embodiment, where the various IC components are implemented on different ICs, the ICs may be packaged together to form a single network interface device.

[0020] The network interface device 104 includes one or more physical layer (PHY) processors 150 (sometimes referred to herein as "PHY processors 150" for brevity). The PHY processors 150 include a transceiver 190 configured to transmit and receive signals over the link 106. In one embodiment, the network interface device 104 also includes one or more medium access control (MAC) processors 152 (sometimes referred to herein as "MAC processors 152" for brevity) coupled to the PHY processors 150. In another embodiment, the network interface device 104 omits the MAC processors 152. For example, in one embodiment, the MAC processors 152 are external to the network interface device 104. In various embodiments where the MAC processors 152 are external to the network interface device 104, the MAC processors 152 may be co-located on the same printed circuit board (PCB) as the PHY processors 150, or may be located on a separate PCB from the PHY processors 150.

[0021] According to one embodiment, the PHY processor 150 includes one or more encoder devices (not shown), a scrambler device (not shown), and a modulator (not shown) for encoding, scrambling, and modulating data as part of generating a transmission signal. According to one embodiment, the PHY processor 150 also includes a demodulator (not shown), a descrambler device (not shown), and one or more decoder devices (not shown) for demodulating, descrambling, and decoding as part of generating received data. In some embodiments, the PHY processor 150 also includes an analog-to-digital converter (hereinafter referred to as "ADC", not shown), which converts an analog signal received via a communication medium into a digital signal. In some embodiments, the PHY processor 150 also includes a digital signal processor (hereinafter referred to as "DSP", not shown), which processes the digital signal to generate a signal corresponding to a modulation symbol, which is then demodulated by a demodulator (not shown).

[0022] The network interface device 104 is implemented using one or more integrated circuits (ICs) configured to operate as described below. For example, the PHY processor 150 may be implemented at least in part on a first IC, and the MAC processor 152 may be implemented at least in part on a second IC. As another example, at least a portion of the PHY processor 150 and at least a portion of the MAC processor 152 may be implemented on a single IC. For example, the network interface device 104 may be implemented using a system on a chip (SoC), wherein the SoC includes at least a portion of the PHY processor 150 and at least a portion of the MAC processor 152. In one embodiment, where the various IC components are implemented on different ICs, the ICs may be packaged together to form a single network interface device.

[0023] In various embodiments, the PHY processors in system 100 (e.g., PHY processors 130, 150) can be configured as a master PHY processor or a slave PHY processor. In one embodiment, the master PHY processor uses a free-running local clock to determine the timing of transmitter operations. The slave PHY processor recovers the clock from a signal received from the master PHY processing device and uses the received signal to determine the timing of transmitter operations. In addition, the master PHY processor and the slave PHY processor are configured to synchronize their clocks and the timing of transmitter operations during a synchronization phase before entering the normal data transmission phase. In various embodiments, synchronization between sensors in the automotive network ensures that inputs from multiple various sensors distributed in the vehicle can be combined into an accurate comprehensive representation of events affecting the vehicle. As an example, in one embodiment, the PHY processor 130 of the network interface device 102 (sometimes referred to herein as the “master network interface device 102”) is configured as a master PHY processor (sometimes referred to herein as the “master PHY processor 130”), and the PHY processor 150 of the network interface device 104 (sometimes referred to herein as the “slave network interface device 104”) is configured as a slave PHY processor (sometimes referred to herein as the “slave PHY processor 150”).

[0024] In one embodiment, the master PHY processor 130 includes a link synchronization controller 182 and a synchronization signal detector 184. In one embodiment, the link synchronization controller 182 is configured to generate one or more synchronization signals 186 to enable the slave PHY processor 150 to synchronize its operation with the master PHY processor 130. In one embodiment, the transceiver 180 is configured to transmit the one or more synchronization signals 186 to the slave PHY processor 150 over the network link 106 during the synchronization phase of link establishment between the network interface device 102 and the network interface device 104. In one embodiment, the transceiver 180 is further configured to receive one or more synchronization signals from the slave PHY processor 150 over the network link 106 during the synchronization phase of link establishment between the network interface device 102 and the network interface device 104. In one embodiment, the synchronization signal detector 184 is configured to detect the synchronization signal received from the slave PHY processor 150. For example, in one embodiment, the synchronization signal comprises a known periodic pseudo-random sequence. In one embodiment, the synchronization signal detector 184 is configured to perform a correlation of the received signal with a known periodic pseudo-random sequence and determine that the received signal is a synchronization signal if the correlation result is above a detection threshold.

[0025] In one embodiment, the link synchronization controller 182 and / or the synchronization signal detector 184 are implemented by a processor configured to execute machine-readable instructions stored in a memory device (not shown), such as RAM, ROM, flash memory, etc. In one embodiment, the link synchronization controller 182 and / or the synchronization signal detector 184 additionally or alternatively include a hardware state machine configured to generate and / or detect synchronization signals, such as those described herein.

[0026] In one embodiment, the slave PHY processor 150 includes a link synchronization controller 192 and a synchronization signal detector 194. The transceiver 190 of the slave PHY processor 150 is configured to receive the synchronization signal 184 transmitted by the master PHY processor 130 during the synchronization phase of link establishment between the network interface device 102 and the network interface device 104. In one embodiment, the synchronization signal detector 194 is configured to detect the synchronization signal received from the master PHY processor 130. For example, in one embodiment, the synchronization signal comprises a known periodic pseudorandom sequence. In one embodiment, the synchronization signal detector 194 is configured to perform a correlation between the received signal and the known periodic pseudorandom sequence and determine that the received signal is a synchronization signal if the correlation result is above a detection threshold.

[0027] In response to the detection of the synchronization signal by the synchronization signal detector 184, the link synchronization controller 192 is configured to transmit a plurality of synchronization signals 188 (sometimes referred to herein as "synchronization response signals") to the master PHY processor 130. For example, the link synchronization controller 192 is configured to transmit a fixed number of the plurality of synchronization response signals 188 to the master PHY processor 130. In one embodiment, the fixed number of synchronization response signals 188 that the link synchronization controller 192 is configured to transmit is configurable and / or programmable in the slave PHY processor 150. In at least some embodiments, transmitting the plurality of synchronization response signals 188 from the slave PHY processor 150 to the master PHY processor 130 increases the probability of detecting the synchronization signals 188 at the master PHY processor 130, for example, in the presence of transient noise on the network link 106 between the master PHY processor 130 and the slave PHY processor 150.

[0028] In one embodiment, the link synchronization controller 192 and / or the synchronization signal detector 194 are implemented by a processor configured to execute machine-readable instructions stored in a memory device (not shown) such as RAM, ROM, flash memory, etc. In one embodiment, the link synchronization controller 192 and / or the synchronization signal detector 194 additionally or alternatively include a hardware state machine configured to generate and / or detect synchronization signals such as described herein.

[0029] Figure 2 is an example timing diagram of a synchronization signal exchange sequence 200 according to one embodiment. Figure 1 The synchronization signal exchange sequence 200 is performed during the synchronization phase of a link establishment process for establishing a communication link between the network interface device 102 and the second network interface device 104 of the system 100. For ease of explanation, Figure 1 The synchronization signal exchange sequence 200 is described in the context of the system 100 of FIG. Figure 1 The system 100 utilizes a synchronization signal handshake sequence 200 during the process of establishing a communication link within the system.

[0030] The master PHY processor 130 of the network interface device 102 initiates the synchronization signal exchange sequence by transmitting one or more synchronization signals 210 to the slave PHY processor 150 of the network interface device 104 over the link 106. In one embodiment, the one or more synchronization signals 210 correspond to Figure 1 The one or more synchronization signals 210 are generally used to synchronize the operation of the slave PHY processor 150 with the master PHY processor 130. In one embodiment, each respective synchronization signal 210 comprises a pseudo-random sequence transmitted by the master PHY processor 130. In another embodiment, each respective synchronization signal 210 comprises an appropriate synchronization signal other than a pseudo-random sequence. In one embodiment, the master PHY processor 130 is configured to transmit the one or more synchronization signals 210 until the master PHY processor 130 receives and detects a synchronization response signal from the slave PHY processor 150. In one embodiment, the master PHY processor 130 is configured to, in response to detecting the synchronization response signal from the slave PHY processor 150, cease transmission of the synchronization signal 210 and transition to a state of the next phase (e.g., a training phase) of the link establishment process, such as a check link state of the link check phase of the link establishment process.

[0031] In one embodiment, the slave PHY processor 150 is in a signal detection wait mode until the slave PHY processor 150 detects the synchronization signal 210 from the master PHY processor 130. In one embodiment, in response to detecting the synchronization signal 210 from the master PHY processor 130, the slave PHY processor 150 initiates transmission of a synchronization signal 212 to the master PHY processor 130. In one embodiment, each respective synchronization response signal 212 includes a pseudorandom sequence transmitted by the slave PHY processor 150. In another embodiment, each respective synchronization response signal 212 includes a suitable synchronization signal other than a pseudorandom sequence. In one embodiment, the slave PHY processor 150 transmits a plurality of synchronization response signals 212 to the master PHY processor 130. For example, the slave PHY processor 150 is configured to transmit a fixed (e.g., configurable and / or programmable) number of synchronization response signals 212 to the master PHY processor 130. In one embodiment, for example, in the presence of noise on the link 106, transmitting the plurality of synchronization signals 212 from the slave PHY processor 150 to the master PHY processor 130 increases the probability of detecting one of the synchronization response signals 212 transmitted by the slave PHY processor 150. For example, if the master PHY processor 130 does not detect an initial one or more synchronization response signals 212 due to, for example, noise on the link 106, the master PHY processor 130 may detect subsequent synchronization response signals 212 in the plurality of synchronization response signals 212 once the noise on the link 106 subsides. Furthermore, in at least some embodiments, because upon detecting a synchronization response signal 212, the master PHY processor 130 enters the next stage of the link establishment procedure and does not expect to receive a synchronization response signal from the slave PHY processor 150, the transmission of the additional synchronization response signals 212 does not negatively impact the operation of the master PHY processor 130 or delay the completion of the link establishment. Upon completion of the transmission of the plurality of synchronization response signals 212 to the master PHY processor 130, the slave PHY processor 150 transitions to the next phase of link establishment, such as the training phase of link establishment. In one embodiment, the master PHY processor 130 and the slave PHY processor 150 are then synchronized and ready to begin the next phase of link establishment, such as the training phase of link establishment.

[0032] Figure 3 is a diagram of a synchronization sequence 300, 350 performed during the synchronization phase of a link establishment process according to one embodiment. In one embodiment, the synchronization signal transmission sequence 300 consists of Figure 1 In one embodiment, the synchronization signal transmission sequence 350 is implemented by the main PHY processor 130. Figure 1 In other embodiments, the synchronization sequences 300, 350 are implemented by different Figure 1 The master PHY processor 130 and the slave PHY processor 150 are implemented in the device.

[0033] The synchronization sequence 300 begins with the master PHY processor 130 in a transmit disabled state 302. For example, the master PHY processor 130 initiates the transmit disabled state 302 upon power-up. The master PHY processor 130 then begins transmitting one or more synchronization signals, such as one or more Tx_Send_S signals 304. After transmitting each of the one or more Tx_Send_S signals 304, the master PHY processor 130 transitions to a signal detect wait (SIGDET_WAIT) state 306 and remains in the signal detect wait state 306 for a pause time, which corresponds to a signal detect wait period. In one embodiment, the signal detect wait period is a maximum of 4 μs, as defined by the IEEE 803.3ch standard. In another embodiment, the signal detect wait period has a suitable maximum duration different from 4 μs. In one embodiment, if the master PHY processor 130 detects a synchronization signal from the slave PHY processor 150 during the signal detect wait period, the master PHY processor 130 transitions to a pause state 310 to complete the synchronization procedure. In one embodiment, the master PHY processor 130 then enters a link check state 312 to perform a link check as part of the link establishment between the network interface device 102 and the network interface device 104. On the other hand, in one embodiment, if the master PHY processor 130 does not detect a synchronization signal from the slave PHY processor 150 during the signal detection wait period, the master PHY processor transmits another synchronization signal 304 to the slave PHY processor 130.

[0034] Continue to refer Figure 3Similar to the state transition and synchronization signal transmission sequence 300 implemented by the master PHY processor 130, the state transition and synchronization signal transmission sequence 350 implemented by the slave PHY processor 150 begins with the slave PHY processor 150 in the transmit disable state 352. Immediately after the transmit disable state 322, the slave PHY processor 150 enters the signal detect wait state 354. In one embodiment, the slave PHY processor 150 remains in the signal detect wait state 352 until the slave PHY processor 150 receives and detects the synchronization signal 304 from the master PHY processor 130. In one embodiment, in response to receiving and detecting the synchronization signal 304 from the master PHY processor 130, the slave PHY processor 150 transitions to the silent wait state 356 and remains in the silent wait state 356 for the duration of the silent wait period. In one embodiment, the duration of the silent wait period is 1 μs. In another embodiment, the silent wait period has a suitable duration other than 1 μs.

[0035] In one embodiment, upon completion of the silent wait period, the slave PHY processor 150 begins transmitting a fixed number of synchronization response signals 358 to the master PHY processor 130. In one embodiment, the synchronization signals 358 correspond to Figure 2 In another embodiment, the synchronization signal 358 is different from Figure 2 Sync signal 212. In an embodiment, the slave PHY processor 150 enters a slave wait state 360 ​​between transmissions of consecutive sync signals 358. In one embodiment, in the slave wait state 360, the slave PHY processor 150 does not perform any transmissions. In one embodiment, the slave PHY processor 150 remains in the slave wait state 360 ​​for the duration of a pause time, which corresponds to the slave wait time period. In one embodiment, the duration of the slave wait time period is 4 μs. In another embodiment, the slave wait time period has a suitable duration different from 4 μs. In one embodiment, the transmission of a fixed number of sync signals 358 to the master PHY processor 130 increases the probability that the master PHY processor 130 will detect the sync signal 358 even in the presence of noise on the link 106. For example, in one embodiment, as Figure 3 As shown in , if the master PHY processor 130 misses detection of one or more initial synchronization signals 358 due to, for example, transient noise on the link 106 , the master PHY processor 130 will detect subsequent synchronization signals 358 .

[0036] Figure 4is a state diagram 400 illustrating example states and state transitions of operations during a synchronization procedure performed by a PHY processor according to one embodiment. In one embodiment, Figure 1 The PHY processors 130, 150 are configured to function according to the state diagram 400 and for ease of description, reference is made to Figure 1 right Figure 4 In other embodiments, Figure 1 The PHY processors 130 , 150 are configured to function according to another suitable state diagram. Additionally, in other embodiments, suitable PHY processing devices other than the PHY processing devices 130 , 150 are configured to function according to the state diagram 400 .

[0037] Initially, in one embodiment, the PHY processor operates in a transmit disabled state 402. In one embodiment, the PHY processor enters the transmit disabled state 402 upon power-up or at the start of a link establishment procedure. In this embodiment, while in the transmit disabled state 402, the PHY processor enables various modes and starts various timers for signal synchronization. For example, in one embodiment, the PHY processor starts the interrupt link timer and sets the transmit mode to the send all zeros (Send_Z) mode so that no transmissions are performed. In one embodiment, the PHY processor also disables the synchronous link control mode and starts the send synchronization signal counter (send_s_counter). In one embodiment, the transition from the transmit disabled state 402 to the next state depends on whether the PHY processor is a master PHY processor (e.g., master PHY processor 130) or a slave PHY processor (e.g., slave PHY processor 150). If the PHY processor is a master PHY processor (e.g., master PHY processor 130), the master PHY processor 130 transitions from the transmit disabled state 402 to the transmit synchronization signal (Tx_Send_S) state 404. In one embodiment, in the transmit synchronization signal state 404, the master PHY processor 130 starts a send signal (send_s) timer and sets the transmit mode to send a synchronization signal (Send_S) for synchronization signal transmission. Thus, in one embodiment, the master PHY processor 130 transmits the synchronization signal until the send signal timer expires. Upon expiration of the synchronization signal send timer, the master PHY processor 130 transitions to the signal detect wait state 406. In one embodiment, in the signal detect wait state 406, the master PHY processor 130 starts a signal detect wait timer and sets the transmit mode to the send all zeros (Send_Z) state so that the master PHY processor 130 does not perform any transmissions.

[0038] Continuing with reference to the signal detect wait state 406, in one embodiment, if the master PHY processor 130 detects a synchronization response signal from the slave PHY processor 150 while the master PHY processor 130 is in the signal detect wait state 406, the master PHY processor 130 transitions to the silent wait state 408, followed by the pause state 410. On the other hand, if the master PHY processor 130 does not detect a synchronization response signal from the slave PHY processor 150 while in the signal detect wait state 406, the master PHY processor 130 cycles back to the synchronization transmit state 404 and transmits another synchronization signal to the slave PHY processor 150. In one embodiment, the master PHY processor 130 continues to transition between the synchronization signal transmit state 404 and the signal detect wait state 406 until the master PHY processor 130 detects a synchronization response signal from the slave PHY processor 150 during the signal detect wait state 406.

[0039] Referring back to the transmit disabled state 402, in one embodiment, if the PHY processor is a slave PHY processor (e.g., slave PHY processor 150), the slave PHY processor 150 transitions from the transmit disabled state 402 to the signal wait state 406. In one embodiment, the slave PHY processor 150 remains in the signal detect wait state 406 until the slave PHY processor 150 detects a synchronization signal from the master PHY processor 130. In response to detecting the synchronization signal from the PHY processor 130, the slave PHY processor 150 transitions to the silent state 410. In one embodiment, the slave PHY processor 150 transitions from the silent state 410 to the transmit synchronization signal state 404. In one embodiment, the transmit synchronization state 410 of the slave PHY processor 150 is generally identical to the transmit synchronization state 410 of the master PHY processor 130, except that, in one embodiment, the slave PHY processor 150 additionally increments a transmit synchronization signal counter. In one embodiment, the slave PHY processor 150 cycles between the transmit synchronization state 410 and the signal detect wait state 406 until the transmit synchronization signal counter reaches a predetermined fixed number. Thus, in one embodiment, the slave PHY processor 150 transmits a predetermined fixed number of synchronization response signals (separated by a signal detect period) to the master PHY processor 130. In some scenarios, the slave PHY processor 150 receives additional synchronization signals from the master PHY processor 130 during a signal detect period after transmitting one or more initial synchronization signals to the master PHY processor 130. In one embodiment, the receipt of additional synchronization signals from the master PHY processor 130 during a signal detect period after transmitting one or more initial synchronization signals to the master PHY processor 130 generally indicates that the master PHY processor 130 missed detecting one or more initial synchronization signals from the slave PHY processor 150. In one embodiment, in response to receiving the additional synchronization signals from the master PHY processor 130, the slave PHY processor 130 continues to transmit the predetermined fixed number of synchronization response signals to the master PHY processor 130. In one embodiment, the slave PHY processor 130 continues to transmit the predetermined fixed number of synchronization response signals to the master PHY processor 130 without restarting the transmission of the predetermined fixed number of synchronization response signals to the master PHY processor 130. For example, in one embodiment, the slave PHY processor 150 continues to transmit the predetermined fixed number of synchronization response signals without resetting the transmit synchronization signal counter.In one embodiment, continuing to transmit the synchronization response signals to the master PHY processor 130 without restarting the transmission of the predetermined fixed number of synchronization response signals to the master PHY processor 130 ensures that the transmission of the predetermined fixed number of synchronization response signals is not restarted due to false detection of additional synchronization signals from the master PHY processor 130 during a signal detection period after the transmission of one or more initial synchronization signals to the master PHY processor 130.

[0040] Continue to refer Figure 4 In one embodiment, upon completion of transmitting a predetermined fixed number of synchronization response signals to the master PHY processor 130, the slave PHY processor 150 transitions to the pause state 410. In one embodiment, the pause state 410 completes the synchronization phase of the slave PHY processor 150. In one embodiment, upon expiration of the signal detection wait timer in the pause state 410, the slave PHY processor 150 transitions to the link good state.

[0041] Figure 5 is a flow chart of an example method 500 for training synchronization between a first network interface device and a second network interface device according to one embodiment. In one embodiment, the method 500 is performed by a slave device such as Figure 1 For ease of explanation, the method 500 is described herein in the context of a first network interface device being a master device (sometimes referred to herein as the “master network interface device”) and a second network interface device being a slave device (sometimes referred to herein as the “master network interface device”).

[0042] At block 502, a slave network interface device receives a first synchronization signal transmitted by a master network interface device (e.g., from the network interface device 104, from the PHY processor 150, etc.). In one embodiment, the synchronization signal is used to train synchronization between the slave network interface device and the master network interface device. In one embodiment, the slave network interface device receives a first synchronization signal transmitted by the master network interface device. Figure 2 The synchronization signal 210 or Figure 3 In another embodiment, a synchronization signal 304 is received from the network interface device that is different from Figure 2 The synchronization signal 210 or Figure 3 The synchronization signal 304 is a synchronization signal.

[0043] At block 504, in response to receiving the first synchronization signal from the master network interface device, the slave network interface device transmits one or more initial synchronization response signals to the master network interface device. In one embodiment, the initial one or more synchronization response signals transmitted by the slave network interface device are initial synchronization response signals among a fixed number of synchronization response signals that the slave network interface device is configured to transmit to the master network interface device. In one embodiment, the slave network interface device transmits Figure 2 One or more synchronous response signals 212 or Figure 3 In another embodiment, the network interface device transmits a synchronization response signal 358 different from Figure 2 The synchronization signal 212 or Figure 3 The synchronous response signal 358 is one or more synchronous response signals.

[0044] At block 506, the slave network interface device receives a second synchronization signal from the master network interface device after transmitting the one or more initial synchronization response signals to the master network interface device. In one embodiment, receiving the second synchronization signal from the master network interface device at block 506 after transmitting the one or more initial synchronization response signals to the master network interface device at block 504 generally indicates that the master network interface device missed detection of the one or more initial synchronization response signals transmitted by the slave network interface device at block 504.

[0045] At block 508, after receiving the second synchronization signal from the master network interface device, the slave network interface device continues to transmit synchronization response signals from the slave network interface device to the master network interface device until a fixed number of synchronization response signals are transmitted from the slave network interface device to the master network interface device. In one embodiment, the slave network interface device continues to transmit the predetermined fixed number of synchronization signals to the master network interface device without restarting transmission of the predetermined fixed number of synchronization signals to the master network interface device. In one embodiment, continuing transmission of synchronization signals to the master network interface device without restarting transmission of the predetermined fixed number of synchronization signals to the master network interface device ensures that transmission of the predetermined fixed number of synchronization signals is not restarted due to erroneous detection of synchronization signals from the master network interface device after one or more initial synchronization signals have been transmitted to the master network interface device.

[0046] In one embodiment, a method for training synchronization between a first network interface device and a second network interface device includes: receiving, at the second network interface device, a first synchronization signal transmitted by the first network interface device, the synchronization signal being used to train synchronization between the second network interface device and the first network interface device; in response to receiving the first synchronization signal from the first network interface device, transmitting, using the second network interface device, one or more initial synchronization response signals to the first network interface device, the one or more initial synchronization response signals being selected from a fixed number of synchronization response signals that the second network interface device is configured to transmit to the first network interface device; after transmitting the one or more initial synchronization response signals, receiving a second synchronization signal from the first network interface device; and, after receiving the second synchronization signal, continuing to transmit synchronization response signals from the second network interface device to the first network interface device until the fixed number of synchronization response signals are transmitted from the second network interface device to the first network interface device.

[0047] In other embodiments, the method further includes one or any suitable combination of two or more of the following features.

[0048] The method further includes initializing a send synchronization signal counter at the second network interface device; and incrementing the send synchronization signal counter for transmitting a corresponding synchronization response signal to the first network interface device.

[0049] Continuing to transmit the synchronization response signal from the second network interface device to the first network interface device includes continuing to transmit the synchronization response signal until a sent synchronization signal counter reaches a fixed predetermined number.

[0050] Continuing to transmit the synchronization response signal from the second network interface device to the first network interface device includes continuing to transmit the synchronization response signal without resetting the send synchronization signal counter in response to receiving the second synchronization signal from the first network interface device.

[0051] Continuing to transmit the synchronization response signal from the second network interface device to the first network interface device includes continuing to transmit the synchronization response signal during a time period when the first network interface device does not expect to receive the synchronization response signal from the second network interface device.

[0052] Transmitting, by the second network device, the one or more initial synchronization response signals includes pausing transmission for a duration of a pause time after a corresponding one of the initial synchronization response signals among the one or more initial synchronization response signals.

[0053] Receiving the second synchronization signal from the first network interface device includes receiving the second synchronization signal during a pause time after transmission of an initial synchronization response signal among the one or more initial synchronization response signals transmitted by the second network interface device.

[0054] After a corresponding initial synchronization response signal among the one or more initial synchronization response signals, pausing transmission for a duration of the pause time includes pausing transmission for 4 μs.

[0055] The method further includes transitioning to a link check state at the second network interface device after transmitting a fixed number of synchronization response signals from the second network interface device to the first network interface device.

[0056] Transmitting the one or more initial synchronization response signals includes transmitting the one or more initial synchronization response signals from among a programmable fixed number of synchronization response signals that the second network interface device is configured to transmit to the first network interface device.

[0057] Transmitting a particular initial synchronization response signal among the fixed number of synchronization response signals to the first network interface device includes transmitting a periodic pseudo-random sequence to the first network interface device.

[0058] In another embodiment, an apparatus includes a second network interface device for coupling the apparatus to a first network interface device via a network link. The second network interface device includes a physical layer (PHY) processor implemented on one or more IC devices, the physical layer (PHY) processor being configured to: receive a first synchronization signal transmitted by the first network interface device, the first synchronization signal being used to train synchronization between the second network interface device and the first network interface device; in response to receiving the first synchronization signal from the first network interface device, transmit one or more initial synchronization response signals to the first network interface device, the one or more initial synchronization response signals being selected from a fixed number of synchronization response signals that the second network interface device is configured to transmit to the first network interface device; after transmitting the one or more initial synchronization response signals, receive a second synchronization signal from the first network interface device; and after receiving the second synchronization signal, continue transmitting synchronization response signals to the first network interface device until the fixed number of synchronization response signals are transmitted from the second network interface device to the first network interface device.

[0059] In other embodiments, the device further includes one or any appropriate combination of two or more of the following features.

[0060] The PHY processor is further configured to: initialize a transmit synchronization signal counter; increment the transmit synchronization signal counter for transmitting a corresponding synchronization response signal to the first network interface device; and continue transmitting the synchronization response signal to the first network interface device until the transmit synchronization signal counter reaches a fixed predetermined number.

[0061] The PHY processor is configured to, in response to receiving the second synchronization signal from the first network interface device, continue to transmit the synchronization response signal to the first network interface device without resetting the transmit synchronization signal counter.

[0062] The PHY processor is configured to continue transmitting the synchronization response signal to the first network interface device during a time period when the first network interface device does not expect to receive the synchronization response signal from the second network interface device.

[0063] The PHY processor is configured to pause transmission for a duration of a pause time following a corresponding initial synchronization response signal among the one or more initial synchronization response signals.

[0064] The PHY processor is configured to receive a second synchronization signal from the first network interface device during a pause time after transmission of an initial synchronization response signal among the one or more initial synchronization response signals transmitted by the second network interface device.

[0065] The PHY processor is configured to pause transmission for a duration of 4 μs after a corresponding initial synchronization response signal among the one or more initial synchronization response signals.

[0066] The PHY processor is further configured to transition to the link check state after a fixed number of synchronization response signals are transmitted from the second network interface device to the first network interface device.

[0067] The fixed number of synchronization response signals that the second network interface device is configured to transmit to the first network interface device is programmable.

[0068] The PHY processor is further configured to transmit a specific synchronization response signal among the fixed number of synchronization response signals to the first network interface device at least by transmitting a periodic pseudo-random sequence to the first network interface device.

[0069] At least some of the various blocks, operations, and techniques described above may be implemented using hardware, a processor executing firmware instructions, a processor executing software instructions, or any combination thereof. When implemented using a processor executing software or firmware instructions, the software or firmware instructions may be stored in any suitable computer-readable memory, such as random access memory (RAM), read-only memory (ROM), flash memory, etc. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause the one or more processors to perform various actions.

[0070] When implemented in hardware, the hardware may include one or more of discrete components, integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), and the like.

[0071] Although the present invention has been described with reference to specific examples (which are intended to be illustrative only and not limiting of the invention), changes, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention.

Claims

1. A method for training synchronization between a first network interface device and a second network interface device, the method comprising: receiving, at the second network interface device, a first synchronization signal transmitted by the first network interface device, the synchronization signal being used to train synchronization between the second network interface device and the first network interface device; in response to receiving the first synchronization signal from the first network interface device, transmitting, using the second network interface device, one or more initial synchronization response signals to the first network interface device, the one or more initial synchronization response signals being selected from a fixed predetermined number of synchronization response signals that the second network interface device is configured to transmit to the first network interface device; receiving a second synchronization signal from the first network interface device after transmission of the one or more initial synchronization response signals; as well as After receiving the second synchronization signal, transmission of synchronization response signals from the second network interface device to the first network interface device continues until the fixed predetermined number of synchronization response signals are transmitted from the second network interface device to the first network interface device.

2. The method according to claim 1, further comprising Initializing a send synchronization signal counter at the second network interface device, and Incrementing the sending synchronization signal counter to transmit a corresponding synchronization response signal to the first network interface device, wherein Continuing to transmit the synchronization response signal from the second network interface device to the first network interface device includes: The synchronization response signal is continuously transmitted until the transmission synchronization signal counter reaches the fixed predetermined number.

3. The method of claim 2, wherein continuing to transmit the synchronization response signal from the second network interface device to the first network interface device comprises: In response to receiving the second synchronization signal from the first network interface device, continuing to transmit the synchronization response signal without resetting the transmit synchronization signal counter.

4. The method of claim 1 , wherein continuing to transmit the synchronization response signal from the second network interface device to the first network interface device comprises: During a time period in which the first network interface device does not expect to receive a synchronization response signal from the second network interface device, the synchronization response signal continues to be transmitted.

5. The method of claim 1 , wherein transmitting, by the second network device, one or more initial synchronization response signals comprises: After transmission of a respective one of the one or more initial synchronization response signals, transmission is paused for a duration of a pause time.

6. The method of claim 5, wherein receiving the second synchronization signal from the first network interface device comprises: The second synchronization signal is received during the pause time after transmission of an initial synchronization response signal among the one or more initial synchronization response signals transmitted by the second network interface device.

7. The method of claim 5 , wherein pausing transmission for a duration of a pause time after a corresponding one of the one or more initial synchronization response signals comprises: Pause transmission for 4μs.

8. The method according to claim 1, further comprising: After the fixed predetermined number of synchronization response signals are transmitted from the second network interface device to the first network interface device, a transition to a link check state is made at the second network interface device.

9. The method of claim 1 , wherein transmitting the one or more initial synchronization response signals comprises: The one or more initial synchronization response signals are transmitted from among a programmable fixed predetermined number of synchronization response signals that the second network interface device is configured to transmit to the first network interface device.

10. The method of claim 1, wherein transmitting a specific initial synchronization response signal among the fixed predetermined number of synchronization response signals to the first network interface device comprises: A periodic pseudo-random sequence is transmitted to the first network interface device.

11. A device comprising: a second network interface device for coupling the apparatus with the first network interface device via a network link, the second network interface device comprising a physical layer (PHY) processor implemented on one or more IC devices, the physical layer (PHY) processor being configured to: receiving a first synchronization signal transmitted by the first network interface device, where the first synchronization signal is used to train synchronization between the second network interface device and the first network interface device; in response to receiving the first synchronization signal from the first network interface device, transmitting one or more initial synchronization response signals to the first network interface device, the one or more initial synchronization response signals being selected from a fixed predetermined number of synchronization response signals that the second network interface device is configured to transmit to the first network interface device; receiving a second synchronization signal from the first network interface device after transmission of the one or more initial synchronization response signals; as well as After receiving the second synchronization signal, synchronization response signals continue to be transmitted to the first network interface device until the fixed predetermined number of synchronization response signals are transmitted from the second network interface device to the first network interface device.

12. The apparatus of claim 11 , wherein the PHY processor is further configured to: Initialize the sending synchronization signal counter, Incrementing the sending synchronization signal counter to transmit a corresponding synchronization response signal to the first network interface device, and The synchronization response signal continues to be transmitted to the first network interface device until the transmission synchronization signal counter reaches the fixed predetermined number.

13. The apparatus of claim 12, wherein the PHY processor is configured to, in response to receiving the second synchronization signal from the first network interface device, continue to transmit the synchronization response signal to the first network interface device without resetting the transmit synchronization signal counter.

14. The apparatus of claim 11, wherein the PHY processor is configured to continue transmitting the synchronization response signal to the first network interface device during a time period when the first network interface device does not expect to receive the synchronization response signal from the second network interface device.

15. The apparatus of claim 11, wherein the PHY processor is configured to pause transmission for a duration of a pause time after transmission of a corresponding initial synchronization response signal among the one or more initial synchronization response signals.

16. The apparatus of claim 15 , wherein the PHY processor is configured to: receive the second synchronization signal from the first network interface device during the pause time after transmission of an initial synchronization response signal among the one or more initial synchronization response signals transmitted by the second network interface device. 17 . The apparatus of claim 15 , wherein the PHY processor is configured to pause transmission for a duration of 4 μs after a corresponding one of the one or more initial synchronization response signals.

18. The apparatus of claim 11, wherein the PHY processor is further configured to transition to a link check state after the fixed predetermined number of synchronization response signals are transmitted from the second network interface device to the first network interface device.

19. The apparatus of claim 11, wherein the fixed predetermined number of synchronization response signals that the second network interface device is configured to transmit to the first network interface device is programmable.

20. The apparatus of claim 11, wherein the PHY processor is further configured to transmit a specific synchronization response signal among the fixed predetermined number of synchronization response signals to the first network interface device at least by transmitting a periodic pseudo-random sequence to the first network interface device.

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