A cached routing device, method, and chip

Abstract

This disclosure presents a cache routing device, method, and chip. The cache routing device includes: a request cache pool (1) containing A cache areas (Top), a request cache logic group (2) containing B request selection logic units (mux) with different priorities, a data transmission module (3) containing C data transmission areas (bot), and a routing exit (4). Each routing exit (4) is connected to an arbitrator (5). Each data transmission area (bot) is connected to a routing exit (4). The cache area (Top) caches the target object and the routing exit identifier. The request selection logic unit (mux) selects the cache area (Top) according to priority order, obtains the target object and the routing exit identifier from the selected cache area (Top), and transmits them to the idle data transmission area (bot). The data transmission area (bot) transmits the target object to the arbitrator (5) through the routing exit (4).

Description

Technical Field

[0001] This disclosure relates to data transmission technology, and more particularly to a cache routing device, method, and chip. Background Technology

[0002] With the continuous development of chip technology and the widespread application of multi-core technology, on-chip network interconnection structures are becoming increasingly common, and their resource allocation is also gradually increasing. Improving throughput and optimizing resources have become key challenges and important design metrics for excellent network interconnection structures. Routers and arbitrators are indispensable components in network interconnection schemes. Related technologies propose using a cached routing structure circuit with a cache module and a route filtering module to achieve high bandwidth and multi-port applications while balancing resources and efficiency. Invention Overview

[0004] The following is an overview of the subject matter described in detail herein, and this overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a cached routing device, method, and chip.

[0006] This disclosure provides a cache routing device, which may include: a request cache pool, a request cache logic group, a data transmission module, and a routing exit; each routing exit is connected to an arbitrator; the request cache pool includes A cache areas, the request cache logic group includes B request selection logic units, and the data transmission module includes C data transmission areas; A, B, and C are all positive integers greater than 1; each data transmission area is connected to all the routing exits; the B request selection logic units each have different priorities;

[0007] The buffer is configured to cache the target object to be transmitted and the routing exit identifier corresponding to the target object; the routing exit identifier is used to indicate the routing exit for outputting the target object.

[0008] The request selection logic unit is configured to select a cache area from A cache areas according to a preset selection strategy, and obtain the target object and the corresponding routing exit identifier from the selected cache area, and transmit them to an idle data transmission area; the selection strategy includes: selecting a cache area from A cache areas in order of priority;

[0009] The data transmission area is configured to cache the target object to be transmitted, and according to the routing exit identifier corresponding to the target object, the target object to be transmitted is transmitted to the corresponding arbitrator through the routing exit corresponding to the routing exit identifier.

[0010] In an exemplary embodiment of this disclosure, the request selection logic unit is further configured to, after selecting a cache area, pass the route exit identifier corresponding to the target object cached in the selected cache area, as well as the route exit identifier corresponding to the target object cached in the cache area selected by the request selection logic unit with a higher priority than itself, to the request selection logic unit with the next higher priority.

[0011] In an exemplary embodiment of this disclosure, the routing exit identifier may include: a routing exit number and / or an indicator for indicating the selected status of each routing exit.

[0012] In an exemplary embodiment of this disclosure, the number of routing exits is D, where D is a positive integer greater than 1;

[0013] The indicator may include D indicator bits, each indicating the selected status of a different route exit through a first value or a second value; wherein, the first value is used to indicate that the route exit is selected, and the second value is used to indicate that the route exit is not selected.

[0014] In an exemplary embodiment of this disclosure, the target object may include: cached data, a cached pointer, or a cached identity ID, wherein the pointer is used to indicate the storage address of the data to be transmitted.

[0015] In an exemplary embodiment of this disclosure, when the target object includes a cached pointer, the cache routing device may further include: a data caching module and a data output logic module;

[0016] The data caching module may include: multiple storage areas, each of which is configured to cache data;

[0017] The data output logic module is connected to each storage area, each data transmission area, and each routing exit, respectively. It is configured to receive the pointer transmitted by the data transmission area and the routing exit identifier corresponding to the pointer, determine the address of the storage area corresponding to the received pointer, obtain cached data from the corresponding storage area according to the address of the storage area, and transmit the cached data to the routing exit corresponding to the received routing exit identifier.

[0018] In an exemplary embodiment of this disclosure, when the target object includes a cached id, the cache routing device further includes: a data caching module and a data output logic module;

[0019] The data caching module includes: multiple storage areas, each of which is configured to cache data;

[0020] The data output logic module is connected to each storage area, each data transmission area, and each routing exit, respectively. It is configured to receive the ID transmitted by the data transmission area and the routing exit identifier corresponding to the ID, compare the received ID with the ID stored in the data output logic module itself, obtain the ID that is the same as the received ID from the ID stored in the data output logic module itself, determine the address of the storage area corresponding to the same ID, obtain cached data from the corresponding storage area according to the address of the storage area, and transmit the cached data to the routing exit corresponding to the received routing exit identifier.

[0021] In an exemplary embodiment of this disclosure, the data output logic module includes Y request selection logic units, where Y is a positive integer greater than 1;

[0022] The number of Y request selection logic units is the same as the number of C data transmission areas; each of the Y request selection logic units is connected to one of the data transmission areas.

[0023] The Y request selection logic units have no priority.

[0024] In an exemplary embodiment of this disclosure, the Y request selection logic units are configured to receive the target object transmitted by the data transmission area of ​​the connection and the routing exit identifier corresponding to the target object, determine the address of the storage area corresponding to the received target object, obtain cached data from the corresponding storage area according to the address of the storage area, and transmit the cached data to the routing exit corresponding to the received routing exit identifier.

[0025] This disclosure also provides a cached routing method, which, based on the aforementioned cached routing device, may include:

[0026] The request caching logic group in the cache routing device comprises B request selection logic units, each selecting a cache area from the A cache areas in the request cache pool of the cache routing device according to a preset selection strategy. The selected cache area then retrieves the target object and its corresponding routing exit identifier, and transmits them to an idle data transmission area in the C data transmission areas of the data transmission module in the cache routing device. A, B, and C are all positive integers greater than 1. The B request selection logic units each have different priorities. The selection strategy includes selecting a cache area from the A cache areas according to priority order.

[0027] The selected data transmission area buffers the target object to be transmitted, and transmits the target object to the corresponding arbitrator through the route exit corresponding to the route exit identifier of the target object.

[0028] In an exemplary embodiment of this disclosure, the method may further include:

[0029] Each of the request selection logic units selects one cache area from the A cache areas according to priority order;

[0030] After selecting a cache area, each request selection logic unit passes the route exit identifier corresponding to the target object cached in the selected cache area, as well as the route exit identifier corresponding to the target object cached in the cache area selected by a request selection logic unit with a higher priority, to the next priority request selection logic unit.

[0031] This disclosure also provides a chip including the aforementioned cache routing device.

[0032] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0033] Overview of the attached figures

[0034] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0035] Figure 1 This is a schematic diagram of a first type of cache routing device according to an embodiment of the present disclosure;

[0036] Figure 2 This is a schematic diagram of a second type of cache routing device according to an embodiment of the present disclosure;

[0037] Figure 3 This is a schematic diagram of the data caching module and data output logic module in the second type of cache routing device according to an embodiment of the present disclosure;

[0038] Figure 4 This is a schematic diagram of a third type of cache routing device according to an embodiment of the present disclosure;

[0039] Figure 5 This is a flowchart of the cached routing method according to an embodiment of the present disclosure;

[0040] Figure 6 This is a block diagram of the chip composition according to an embodiment of the present disclosure.

[0041] Detailed Explanation

[0042] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0043] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0044] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0045] This disclosure provides a cached routing device, such as... Figure 1 As shown, it may include: a request cache pool 1, a request cache logic group 2, a data transmission module 3, and a routing exit 4; each of the routing exits 4 is connected to an arbitrator 5; the request cache pool 1 includes A cache areas, the request cache logic group 2 includes B request selection logic units, and the data transmission module 3 includes C data transmission areas; A, B, and C are all positive integers greater than 1; each of the data transmission areas is connected to all of the routing exits 4; the B request selection logic units each have different priorities;

[0046] The buffer is configured to cache the target object to be transmitted and the routing exit identifier corresponding to the target object; the routing exit identifier is used to indicate the routing exit for outputting the target object.

[0047] The request selection logic unit is configured to select a cache area from A cache areas according to a preset selection strategy, and obtain the target object and the corresponding routing exit identifier from the selected cache area, and transmit them to an idle data transmission area; the selection strategy includes: selecting a cache area from A cache areas in order of priority;

[0048] The data transmission area is configured to cache the target object to be transmitted, and according to the routing exit identifier corresponding to the target object, the target object to be transmitted is transmitted to the corresponding arbitrator through the routing exit corresponding to the routing exit identifier.

[0049] The known cache routing device circuit in related technologies includes a cache module and a route filtering module. The cache module is configured to receive routing requests and cache them in its respective cache pool. The route filtering module is configured to filter routing requests from its respective cache pool and send them to the corresponding arbitrator. Routing requests filtered by different routers are sent to different arbitrators so that any arbitrator receives at most one routing request from a router within a processing cycle. Because the atomicity of the transmission operation needs to be guaranteed (atomicity is a characteristic of database transactions; in the context of database transactions, atomicity means that all operations in a transaction either complete completely or not at all, without ending at some intermediate stage), the route filtering module can only complete the transmission operation from one cache area of ​​the cache module to the corresponding arbitrator within a time unit (e.g., one circuit clock cycle). In the above-mentioned mechanism for sending computation requests, when multiple computation units send requests to the same access address, only one computation unit's request is received by the arbitrator unit, leading to a decrease in the overall data transmission efficiency. In the exemplary embodiments of this disclosure, the cache routing device circuit in related technologies is optimized to solve the problem of insufficient transmission efficiency.

[0050] In exemplary embodiments of this disclosure, such as Figure 1 As shown, compared with the cache routing device circuit in the related art, the cache routing device of the present disclosure uses request selection logic group 2, which improves the data transmission efficiency between request cache pool 1 and data transmission module 3, thereby improving the utilization rate of data transmission area 31 in data transmission module 3 and improving the performance of the entire cache routing device.

[0051] In exemplary embodiments of this disclosure, the cache routing apparatus of this disclosure will be described in detail below.

[0052] In an exemplary embodiment of this disclosure, the request selection logic group 2 consists of B request selection logic units, wherein the number B can be arbitrary and can be defined according to requirements. In this embodiment, B=2 is used as an example to illustrate the scheme of this embodiment.

[0053] In an exemplary embodiment of this disclosure, the B request selection logic units each have different priorities; each request selection logic unit in the request selection logic group 2 can be called a mux (e.g., mux1 and mux2), and each mux has a fixed priority, so that when the total number of muxes is large, all muxes will not conflict when the request is transmitted; the cache area in the request cache pool 1 can be called Top (e.g., Top1, Top2, ..., TopA), and the data transmission area in the data transmission module 3 can be called bot (e.g., bot1, bot2, ..., botC). The target object of the request and the routing exit identifier corresponding to the target object are cached in the cache area Top.

[0054] In an exemplary embodiment of this disclosure, each of the request selection logic units (mux) is further configured to select one cache from the A caches in order of priority.

[0055] In an exemplary embodiment of this disclosure, the priority order may include, but is not limited to, a priority order from high to low. That is, a high-priority request selection logic unit mux first selects a cache top from A cache tops, then the next-priority request selection logic unit mux first selects a cache top from the remaining A-1 cache tops, and so on, until all the request selection logic units mux have selected a cache top.

[0056] In an exemplary embodiment of this disclosure, the selection strategy for each request selection logic unit mux when selecting a cache area Top may include, but is not limited to: selecting from the beginning to the end or from the beginning to the end according to the arrangement order of the multiple cache areas Top, or randomly selecting a cache area Top from the multiple cache areas Top according to a random selection strategy (subsequent lower priority request selection logic units mux may randomly select a cache area Top from the multiple cache areas Top after removing the already selected cache area Top when selecting a cache area Top).

[0057] In an exemplary embodiment of this disclosure, in order to effectively remove the selected cache area Top, the route exit identifier corresponding to the target object cached in the selected cache area Top can be passed to the lower priority request selection logic unit mux, as detailed below.

[0058] In an exemplary embodiment of this disclosure, each request selection logic unit mux is further configured to, after selecting a cache area Top, pass the cache area identifier of the selected cache area Top, as well as the cache area identifier of the cache area Top selected by the request selection logic unit mux with a higher priority than itself, to the request selection logic unit mux with the next higher priority.

[0059] In an exemplary embodiment of this disclosure, the B request selection logic units (mux) may be further grouped, with each group including multiple request selection logic units. The number of request selection logic units in different groups may be the same or different.

[0060] In an exemplary embodiment of this disclosure, multiple groups of request selection logic units (mux) have different priorities; each group of muxes has a fixed priority, and each mux within each group also has a fixed priority, so that when the total number of muxes is large, all muxes will not conflict when request transmission is working.

[0061] In an exemplary embodiment of this disclosure, each group of request selection logic units (mux) is further configured to select one first cache from A first caches in priority order. This priority order may include, but is not limited to, an order of priority from high to low.

[0062] In an exemplary embodiment of this disclosure, there are D routing exits (D is a positive integer greater than 1) and A buffer Tops. The values ​​of A and D can be the same or different. When the value of A is greater than the value of D, the routing exit identifiers corresponding to the target objects cached in multiple buffer Tops will be the same. That is, multiple target objects need to be transmitted out from the same routing exit. If the buffer Tops containing these multiple target objects are selected at the same time, it is possible that these multiple target objects need to be transmitted out through the same routing exit at the same time, which will inevitably cause routing exit congestion and seriously affect transmission efficiency.

[0063] In an exemplary embodiment of this disclosure, the following solution is proposed to address the above problems: Each request selection logic unit mux is further configured to, after selecting a cache top, pass the route exit identifier corresponding to the target object cached in the selected cache top, and the route exit identifier corresponding to the target object cached in the cache top selected by the request selection logic unit mux with a higher priority than itself, to the request selection logic unit mux with the next higher priority.

[0064] In the exemplary embodiments of this disclosure, the above-described scheme ensures that when each request selection logic unit (mux) selects a cache top from the remaining multiple cache tops, the cache tops that store the route exit identifiers stored in the previously selected cache tops within a preset time period are removed. That is, the remaining multiple cache tops are filtered again, and a cache top is selected from the remaining cache tops after this second filtering. This ensures that within a short period, the selected cache tops do not store the same route exit identifier, thus preventing the target objects stored in the selected cache tops from being output through the same route exit. This embodiment ensures that the route exit does not become congested during the transmission of the target object.

[0065] In an exemplary embodiment of this disclosure, for example, if mux1 has a higher priority than mux2, and if mux1 currently selects Top1, then mux1 will pass the route exit identifier corresponding to the target object cached in Top1 to mux2. When mux2 selects the cache area Top in the request cache pool 1, it will skip all cache areas Top that store the same route exit identifier as the one stored in Top1. Similarly, when the request selection logic group 2 also includes mux3, mux4, etc., the same applies. When mux3 selects the cache area Top, it will avoid the route exit identifiers stored in the cache areas Top selected by mux2 and mux1.

[0066] In an exemplary embodiment of this disclosure, the routing exit identifier may include, but is not limited to: a routing exit number and / or an indicator for indicating the selected status of each routing exit.

[0067] In an exemplary embodiment of this disclosure, the routing exit number may include, but is not limited to, using letters and numbers, such as: Portout1, Portout2, ..., PortoutD.

[0068] In an exemplary embodiment of this disclosure, the indicator may include D indicator bits, each of which indicates the selection status of a different routing exit through a first value or a second value; wherein the first value is used to indicate that the routing exit is selected, and the second value is used to indicate that the routing exit is not selected.

[0069] In an exemplary embodiment of this disclosure, for example, when there are 16 routing exits, D = 16, the indicator may include 16 indicator bits. For example, it can be represented as abcd efgh igkl mnop, where a, b, c, d, e, f, g, h, i, g, k, l, m, n, o, and p each represent an indicator bit, and each indicator bit represents a routing exit (e.g., a can represent the 1st routing exit, b can represent the 2nd routing exit, ..., P can represent the 16th routing exit, or conversely, a can represent the 16th routing exit, b can represent the 15th routing exit, ..., P can represent the 1st routing exit; in this embodiment of the disclosure, a representing the 1st routing exit, b representing the 2nd routing exit, ..., P representing the 16th routing exit is used as an example for illustration). Each indicator bit can be denoted by 0 and 1 to indicate its selected state; 1 indicates that the indicator is not selected, and 0 indicates that the indicator bit is not selected. For example, 0000 0000 0000 0001 means that the 16th route exit is selected, and the remaining route exits are not selected; 1000 1000 0000 0000 means that the 1st and 5th route exits are selected, and the remaining route exits are not selected.

[0070] In an exemplary embodiment of this disclosure, the route exit identifier cached in the cache Top can be converted into the format of the aforementioned indicator before storage.

[0071] In an exemplary embodiment of this disclosure, when the route exit identifier stored in Top1 selected by mux1 is used to indicate the 11th route exit, the mask passed from mux1 to mux2 is 0000 00000010 0000; when the route exit identifier stored in Top2 selected by mux2 is used to indicate the 1st route exit, the mask passed from mux2 to mux3 is 10000000 0010 0000.

[0072] In exemplary embodiments of this disclosure, the above-described embodiments can significantly increase the rate at which the target object and the route exit identifier are transferred from the request cache pool 1 to the data transmission module 3.

[0073] In an exemplary embodiment of this disclosure, the target object may include: cached data, a cached pointer pin, and / or a cached identity ID, wherein the pointer pin is used to indicate the storage address of the data to be transmitted.

[0074] In an exemplary embodiment of this disclosure, when the target object is cached data, it can be directly based on... Figure 1 The structure implements the above-described embodiment to achieve direct data transmission.

[0075] In the exemplary embodiments of this disclosure, the content stored in the cache area Top includes two parts: the target object and the routing exit identifier corresponding to the target object. The routing exit identifier is used during the routing process, while the target object itself remains unchanged during the routing process except for being transmitted, and has no other use; it is merely transferred from the cache area Top in the request cache pool 1 to the data transmission area bot in the data transmission module 3. Therefore, if the target object is data, since some data is large, it will inevitably occupy a certain amount of space during transmission. Therefore, it is advisable to consider caching the data to be transmitted separately. In the cache routing device of this embodiment, only the pointer corresponding to the data is transmitted. This pointer is used to indicate the cache address of the data. Since the space occupied by the pointer is much smaller than the data itself, the space occupied during data transmission can be reduced, saving resources.

[0076] In exemplary embodiments of this disclosure, such as Figure 2 As shown, when the target object includes a cached pointer pin, the cache routing device may further include: a data cache module 11 and a data output logic module 12;

[0077] The data caching module 11 may include: multiple storage areas buf (e.g., buf_1, buf_2, ..., buf_X, where X is a positive integer), each storage area buf is set to cache data;

[0078] The data output logic module 12 is connected to each storage area buf, each data transmission area bot, and each routing exit 4, respectively. It is configured to receive the pointer pin transmitted by the data transmission area bot and the routing exit identifier corresponding to the pointer pin, determine the address of the storage area corresponding to the received pointer pin, obtain cached data from the corresponding storage area according to the address of the storage area, and transmit the cached data to the routing exit 4 corresponding to the received routing exit identifier.

[0079] In exemplary embodiments of this disclosure, such as Figure 3 As shown, when the target object includes a cached ID, the cache routing device may further include: a data caching module 11 and a data output logic module 12;

[0080] The data caching module 11 may include: multiple storage areas buf (e.g., buf_1, buf_2, ..., buf_X, where X is a positive integer), each storage area buf is set to cache data;

[0081] The data output logic module 12 is connected to each storage area buf, each data transmission area bot, and each routing exit 4. It is configured to receive the ID transmitted by the data transmission area bot and the routing exit identifier corresponding to the ID. The received ID is compared with the ID stored in the data output logic module 12 itself. The same ID is obtained from the ID stored in the data output logic module 12 itself. The address of the storage area corresponding to the same ID is determined. The cached data is obtained from the corresponding storage area according to the address of the storage area. The cached data is then transmitted to the routing exit 4 corresponding to the received routing exit identifier.

[0082] In an exemplary embodiment of this disclosure, the data output logic module 12 includes Y request selection logic units, where Y is a positive integer greater than 1;

[0083] The number of Y request selection logic units is the same as the number of C data transmission areas; each of the Y request selection logic units is connected to one of the data transmission areas.

[0084] The Y request selection logic units have no priority.

[0085] In an exemplary embodiment of this disclosure, the Y request selection logic units are configured to receive the target object (pin and / or id) transmitted by the data transmission area of ​​the connection and the routing exit identifier corresponding to the target object, determine the address of the storage area corresponding to the received target object, obtain cached data from the corresponding storage area according to the address of the storage area, and transmit the cached data to the routing exit corresponding to the received routing exit identifier.

[0086] In exemplary embodiments of this disclosure, such as Figure 3As shown, the structure of the data output logic module 12 does not have priority judgment. Therefore, the number of muxes (e.g., mux1, mux2, ..., muxY, where Y is a positive integer) in the data output logic module 12 is the same as the number of bots (i.e., C = Y). The logic link of the muxes is completed by the pointer pin of the target data transmitted by the bot, corresponding to the buf information in the data buffer module 11, and the port_out signal. This avoids the fact that all bufs in the data buffer module 11 need to be directly connected to port_out, which would have resulted in the bus number being X*D*bit width. The current bus number is (X*C+C*D)*bit width. However, when C is sufficiently small, (X*C+C*D) is less than X*D, reducing the scale of the logic.

[0087] In exemplary embodiments of this disclosure, such as Figure 4 As shown, each piece of data has a unique ID (identifier). This ID includes information about the port_out the data is destined for, as well as addressing information for subsequent routing structures and the data's own serial number, making each data ID almost unique. This ID can be stored in Top and bot. Figure 4 The right-hand side determines the order in which requests are passed. After the ID is passed to the data output logic module 12, the data output logic module 12 matches the data according to the ID, and only data with the same ID will be passed.

[0088] In an exemplary embodiment of this disclosure, the buf in the data caching module 11 stores data and its corresponding ID. Figure 4 The right side of the middle section contains another copy of the same ID.

[0089] In an exemplary embodiment of this disclosure, each routing exit 4 can be connected to an arbitrator 5 (e.g., arbitrators 51, 52, ..., 5D). When any pointer is read by an arbitrator 5, the cache address of the corresponding data can be determined based on the pointer, and the required data can be read from the cache address.

[0090] In the exemplary embodiments of this disclosure, the above-described embodiments replace the data portion originally cached in the cache Top with pointers of smaller bit width, thereby reducing resource consumption and reducing the number of data transmission operations in the cache routing device.

[0091] The exemplary embodiments disclosed herein include at least the following advantages:

[0092] 1. It reduces the transient efficiency drop caused by insufficient request transmission efficiency between the two caches in the dual-caching routing device circuit of related technologies, thereby improving transmission efficiency.

[0093] 2. It solves the problem of using additional cache resources due to the large bit width of data during direct data transmission.

[0094] This disclosure also provides a cached routing method based on the aforementioned cached routing device, such as... Figure 5 As shown, the method may include steps S101-S102:

[0095] S101. The request caching logic group in the cache routing device includes B request selection logic units, each selecting a cache area from the A cache areas in the request caching pool of the cache routing device according to a preset selection strategy. The selected cache area then retrieves the target object and the corresponding routing exit identifier, and transmits them to an idle data transmission area in the C data transmission areas of the data transmission module in the cache routing device. A, B, and C are all positive integers greater than 1. The B request selection logic units each have different priorities. The selection strategy includes selecting a cache area from the A cache areas according to priority order.

[0096] S102. The selected data transmission area buffers the target object to be transmitted, and according to the routing exit identifier corresponding to the target object, transmits the target object to the corresponding arbitrator through the routing exit corresponding to the routing exit identifier.

[0097] In an exemplary embodiment of this disclosure, the method may further include:

[0098] Each of the request selection logic units selects one cache area from the A cache areas according to priority order;

[0099] After selecting a cache area, each request selection logic unit passes the route exit identifier corresponding to the target object cached in the selected cache area, as well as the route exit identifier corresponding to the target object cached in the cache area selected by a request selection logic unit with a higher priority, to the next priority request selection logic unit.

[0100] In the exemplary embodiments of this disclosure, any of the embodiments in the foregoing cache routing device embodiments are applicable to the above method embodiments, and will not be described in detail here.

[0101] This disclosure also provides a chip 100, such as Figure 6 As shown, it includes the aforementioned cache routing device 200.

[0102] In the exemplary embodiments of this disclosure, any of the embodiments in the foregoing cache routing device embodiments are applicable to this chip embodiment, and will not be described in detail here.

[0103] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A cache routing device, characterized by, The cache routing device comprises a request cache pool, a request cache logic group, a data transmission module and a routing outlet; each of the routing outlets is connected with an arbitrator; the request cache pool comprises A cache areas, the request cache logic group comprises B request selection logic units, and the data transmission module comprises C data transmission areas; A, B and C are all positive integers greater than 1; each of the data transmission areas is connected with all the routing outlets; the B request selection logic units have different priorities; The cache area is configured to cache a target object to be transmitted and a routing outlet identifier corresponding to the target object; The routing outlet identifier is used to indicate a routing outlet for outputting the target object; The request selection logic unit is configured to select one cache area from the A cache areas according to a preset selection strategy, and obtain the target object and the routing outlet identifier corresponding to the target object from the selected cache area, and transmit the target object and the routing outlet identifier to an idle data transmission area; the selection strategy comprises selecting one cache area from the A cache areas according to a priority order; The data transmission area is configured to cache the transmitted target object, and transmit the transmitted target object to a corresponding arbitrator through a routing outlet corresponding to the routing outlet identifier corresponding to the transmitted target object according to the routing outlet identifier.

2. The cache routing device according to claim 1, wherein The request selection logic unit is further configured to, after selecting one cache area, transmit the routing outlet identifier corresponding to the target object cached in the selected cache area and the routing outlet identifier corresponding to the target object cached in the cache area selected by the request selection logic unit with a higher priority than itself to the request selection logic unit of a next priority. The routing outlet identifier comprises a number of the routing outlet and / or an indicator for indicating a selected state of each routing outlet.

3. The cache routing device of claim 1, wherein, The routing outlet is D in number; 4. The cache routing device of claim 3, wherein, D is a positive integer greater than 1; The indicator comprises D indicator bits, different indicator bits indicate the selected states of different routing outlets by a first value or a second value; wherein the first value is used to indicate that the routing outlet is selected, and the second value is used to indicate that the routing outlet is not selected. The target object comprises cached data, a cached pointer or a cached identity identifier id, and the pointer is used to indicate a storage address of the data to be transmitted.

5. The cache routing device of any of claims 1-4, wherein, When the target object comprises the cached pointer, the cache routing device further comprises a data cache module and a data output logic module; 6. The cache routing device of claim 5, wherein, The data cache module comprises a plurality of storage areas, each of which is configured to cache data; The data output logic module is connected with each storage area, each data transmission area and each routing outlet, and is configured to receive the pointer transmitted by the data transmission area and the routing outlet identifier corresponding to the pointer, judge the address of the storage area corresponding to the received pointer, obtain the cached data from the corresponding storage area according to the address of the storage area, and transmit the cached data to the routing outlet corresponding to the received routing outlet identifier. ​ 7. The cache routing device of claim 5, wherein, When the target object comprises a cached id, the cache routing device further comprises a data cache module and a data output logic module; The data cache module comprises a plurality of storage areas, each of which is configured to cache data; The data output logic module is connected to each storage area, each data transmission area and each routing exit, and is configured to receive the id transmitted by the data transmission area and the routing exit identifier corresponding to the id, compare the received id with the id stored in the data output logic module, obtain an id identical to the received id from the id stored in the data output logic module, determine the address of the storage area corresponding to the identical id, and obtain cache data from the corresponding storage area according to the address of the storage area, and transmit the cache data to the routing exit corresponding to the received routing exit identifier.

8. The cache routing device of claim 6 or 7, wherein, The data output logic module comprises Y request selection logic units, and Y is a positive integer greater than 1; The number of Y request selection logic units is the same as the number of C data transmission areas, and each request selection logic unit in the Y request selection logic units is connected to a data transmission area; The Y request selection logic units have no priority.

9. A method of caching routing, characterized by, The cache routing device according to any one of claims 1-8, the method comprising: The B request selection logic units in the request cache logic group in the cache routing device select a cache area from the A cache areas in the request cache pool in the cache routing device according to a predetermined selection strategy, and obtain a target object and a routing exit identifier corresponding to the target object from the selected cache area, and transmit to an idle data transmission area in the C data transmission areas in the data transmission module in the cache routing device; A, B and C are all positive integers greater than 1; the B request selection logic units have different priorities; and the selection strategy comprises selecting a cache area from the A cache areas in order of priority. The selected data transmission area caches the transmitted target object, and transmits the transmitted target object to the corresponding arbiter through the routing exit corresponding to the routing exit identifier corresponding to the transmitted target object.

10. The cache routing method of claim 9, wherein, Further comprising: Each request selection logic unit selects a cache area from the A cache areas in order of priority; After selecting a cache area, each request selection logic unit transmits the routing exit identifier corresponding to the target object cached in the selected cache area, and the routing exit identifier corresponding to the target object cached in the cache area selected by the request selection logic unit with a higher priority than itself, to the request selection logic unit of the next priority.

11. A chip, characterized by The cache routing device according to any one of claims 1-8.

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