Charge demultiplexing high-speed CMOS time delay integration imaging

Abstract

Apparatuses, methods, and techniques are provided for performing readout of a plurality (N) of time delay integration (TDI) pixel registers to receive respective signal charges at a plurality (N) of sense nodes (SNs). The readout uses a plurality (N) of charge steering (CST) gates to steer and de-multiplex respective charges from the respective pixel registers to the corresponding SNs. Output is provided from the SNs to produce respective digital values (e.g., by using parallel conversion of ADCs). In one embodiment, the charges are transferred vertically to the CSTs to be de-multiplexed horizontally to the SNs. The CSTs can be configured in a multi-stage configuration to help good charge transfer. The CSTs can be associated with a barrier implant to help correct charge steering.

Description

Technical Field

[0001] This disclosure relates to a complementary metal-oxide-semiconductor (CMOS) time-delay integration (TDI) high-fidelity imaging method and apparatus for parallel readout operations, and more specifically, to charge demultiplexing of high-speed charge-connected CMOS time-delay integration (TDI) imaging. Background Technology

[0002] In a traditional CMOS TDI imager, the following line-by-line readout operation is performed. This sequential operation limits the sensor's speed. 1. The sensing node (SN) is reset to the reset drain voltage (VDD) via the reset gate (RST). 2. The signal charge of the final TDI stage is transferred to the SN. 3. The signal charge is converted into a signal voltage at the SN and output via the source follower (SF). 4. The analog signal voltage is then converted into a digital value by an analog-to-digital converter (ADC).

[0003] In the most advanced CMOS TDI imagers currently available, it takes at least 3 μs to complete the processing of one TDI line (i.e., the maximum line rate is about 300 kHz). Summary of the Invention

[0004] The embodiments described herein relate to a high-speed charge-coupled CMOS TDI image sensor in which multiple charge-coupled device (CCD) pixels are arranged in a matrix. In one embodiment, a column slice of such a pixel array includes M TDI imaging pixels, N charge-guided gates (CSTs), N serial gates (SNs), a global reset structure (e.g., RST and VDD), and N parallel readout structures, wherein the N parallel readout structures include N serial gates (SFs), N sample-and-hold (S / H) capacitor circuits for correlated double sampling (CDS) operation, and N column-parallel ADCs, where N is equal to or less than M.

[0005] Apparatus, methods, and techniques are provided for performing readouts of multiple (N) TDI pixel registers to receive corresponding signal charges at multiple (N) SNs. The readout uses multiple (N) CSTs to guide and demultiplex the corresponding charges from the corresponding pixel registers to the corresponding SNs. Outputs are provided from the SNs to generate corresponding digital values ​​(e.g., by using parallel conversion of an ADC). In one embodiment, the charges are vertically transferred to the CSTs to be horizontally demultiplexed to the SNs. The CSTs can be configured in a multi-level configuration to facilitate good charge transfer. The CSTs can be associated with barrier implantation to aid proper charge guidance. The apparatus can be a high-speed charge-coupled CMOS TDI image sensor in which multiple CCD pixels are arranged in a matrix. Such an image sensor can be configured for bidirectional operation.

[0006] In one embodiment, a method is provided comprising: performing readouts of a plurality of (N) time-delay-integrated (TDI) pixel registers to receive corresponding signal charges at a plurality of (N) sensing nodes, wherein the readouts utilize a plurality of (N) charge-guiding gates to guide and demultiplex the corresponding charges from the corresponding pixel registers to the plurality of sensing nodes; and providing outputs from the plurality of sensing nodes to generate corresponding digital values.

[0007] In one embodiment, the method is performed by a high-speed CMOS TDI image sensor, which includes a plurality of charge-connected device (CCD) pixels arranged in the form of a CCD pixel matrix, the column slices of the CCD pixels including a plurality (N) of TDI pixel registers; a plurality (N) of isolation (ISO) registers including a plurality (N) of CSTs; a plurality of output structures including a plurality (N) of sensing nodes, a global reset structure and a plurality of SFs; and a plurality (N) of parallel conversion units, each of which includes an S / H capacitor array and a column-parallel ADC.

[0008] In one embodiment, an apparatus is provided including circuitry configured to perform a method according to any of the method embodiments herein.

[0009] In one embodiment, an apparatus is provided, comprising: a plurality (N) of time delay integration (TDI) pixel registers; a plurality (N) of isolation (ISO) registers including a plurality (N) of charge-guiding gates connected to the plurality (N) of TDI pixel registers; a plurality (N) of output structures including a plurality (N) of sensing nodes connected to receive corresponding signal charges read from the plurality (N) of TDI pixel registers, the corresponding signal charges being guided and demultiplexed by the plurality (N) of charge-guiding gates, and the plurality (N) of sensing nodes being connected to provide outputs to generate digital values.

[0010] In one embodiment, each of the plurality of (N) sensing nodes is configured with circuitry providing parallel reset functionality. In another embodiment, each of the plurality of (N) sensing nodes is coupled via a plurality of (N) source followers (SF) to a plurality of (N) sample-and-hold (S / H) capacitor circuitry and a plurality of (N) column-parallel analog-to-digital converters (ADCs) to generate a corresponding digital value for each respective signal charge in parallel.

[0011] In one embodiment, the device includes a CMOS TDI image sensor, wherein a plurality of CCD pixels are arranged in the form of a CCD pixel matrix, wherein column slices of the CCD pixels include a plurality of (N) TDI pixel registers, a plurality of (N) ISO registers, a plurality of (N) CSTs, a plurality of (N) output structures, a plurality of (N) sensing nodes, a global reset structure providing parallel reset functionality, and a plurality of (N) SFs, a plurality of (N) S / H capacitor arrays, and a plurality of (N) column-parallel ADCs.

[0012] This invention solves the traditional, slow, sequential readout operation by demultiplexing the charge accumulated in multiple TDI rows to the corresponding readout structure, which enables fast, parallel readout operations. Attached Figure Description

[0013] Figure 1 is a diagram showing a column slice of a high-speed charge-connected CMOS TDI imager pixel array according to one embodiment.

[0014] Figure 2 is a diagram showing a column slice of an imager pixel array according to one embodiment, which is configured for 3 TDI row operations.

[0015] Figure 3 is a schematic diagram illustrating the S / H capacitor circuit and the implementation scheme of the column-parallel ADC that provides parallel conversion functionality.

[0016] Figure 4 This is a diagram illustrating the operational timing according to one implementation scheme.

[0017] Figure 5A and Figure 5B It is a corresponding implementation of a column slice of an imager pixel array configured for 4TDI row operation.

[0018] Figure 6 This is a diagram showing the timing of operations for a two-level configuration used for N=4TDI row operations.

[0019] Figure 7 This is a diagram showing a column slice of a high-speed charge-coupled CMOS TDI imager pixel array according to one embodiment, the pixel array being configured for 2TDI row operation and using charge-guided gates associated with barrier implantation.

[0020] Figure 8 It is based on an implementation plan. Figure 7 A cross-sectional view along line A-A' or B-B'.

[0021] Figure 9 This shows the time along when CST1 and CST2 are timed high and low, respectively. Figure 7The curves of the simulated channel potentials at the cutting lines A-A' and B-B'.

[0022] Figure 10 This illustrates an implementation scheme. Figure 7 A diagram showing the operation timing of the high-speed charge-coupled CMOS TDI imager pixel array.

[0023] Figure 11A and 11B This is a block diagram illustrating a column slice of a high-speed charge-connected CMOS TDI imager pixel matrix configured for bidirectional operation according to a corresponding implementation scheme.

[0024] Figure 12 A flowchart of a charge demultiplexing high-speed CMOS TDI imaging operation according to one embodiment is shown. Detailed Implementation

[0025] Figure 1 is a diagram illustrating a column slice of a high-speed charge-connected CMOS TDI imager pixel array 100 according to one embodiment. The pixel array 100 is partial, and only its column slice 102 is shown. The pixel array 100 includes additional columns. Column slice 102 includes multiple (M) TDI registers 104 (e.g., pixel registers), which include individual TDI (pixel) registers (e.g., 1041, 1042, ... 104). N-1 104 N …104 M-1 104 M N TDI registers 106 include subsets 1041, 1042, ... 104 of TDI registers 106. N Where N is less than or equal to M, and the multiple (N) sensing nodes (SN) 108 include individual sensing nodes (e.g., 1081, 1082, ... 108). N-1 108 N N SN 108 are components of N output structures.

[0026] Multiple (M)TDI registers 104 are connected to multiple (N) sensing nodes 108 to receive signal charge from N TDI registers 106. The multiple (N) sensing nodes 108 are connected to receive signal charge from the multiple (N) TDI registers 106 via multiple (N) charge-guiding gates 110, the charge-guiding gates 110 including individual charge-guiding (CST) gates (e.g., 1101, 1102, ... 110). N-1 and 110 N N CST 110s are components of N isolated (ISO) registers.

[0027] Each of the N sensing nodes 108 has a global signal reset function 112 and outputs via N source followers (SF) 116 to a parallel conversion function 114, to N corresponding correlated double sampling (CDS) and ADC circuits, as further described in Figures 3 and 4.

[0028] According to one implementation scheme, in contrast to traditional readout, high-speed, parallel operation based on multiple TDI rows is achieved as follows.

[0029] The N SN108s in TDI column 102 are reset in parallel via function 112, ready to retrieve the (signal) charge transferred from the N TDI row pixel registers 106 from the M TDI row pixel registers 104.

[0030] Each charge is vertically transferred from each of the N TDI pixel registers and guided by each of the corresponding N CSTs, and horizontally demultiplexed to each of the corresponding N SNs.

[0031] Each of the N signal charges stored at each of the N SNs is converted into a signal voltage in parallel.

[0032] Each analog signal voltage is output from each of the corresponding N SFs and then converted into a digital value in parallel by each of the corresponding N parallel conversion functions 114. The AD processing overlaps with the subsequent charge transfer. That is, the AD conversion of the current group of analog signal voltages is performed in parallel while the next group of signal charges accumulated in the N TDI registers is being transferred.

[0033] Figure 2 is a diagram of a column slice configured for operation of an imager array 200 with three TDI rows. The imager array shows TDI rows 1, 2, and 3 (e.g., 202, 204, and 206), where each row (202, 204, and 206) is timed using a 4-phase image register clock, with the gate electrodes shown as Clx, where x = 1, 2, 3, and 4. Clx in ISO row 214 (e.g., the ISO register) between N CSTs 110 and N SNs 108 is similarly timed. Because the N CSTs are in phase with Cl1 (see...), the imager array is timed accordingly. Figure 4 Therefore, Cl1 is not present in ISO line 214. Figure 2 illustrates a reset function 112 including a reset gate (RST) 112A and a reset drain (VDD) 112B. In one embodiment, function 112 is used to reset multiple sensing nodes in parallel, wherein the reset includes clearing the multiple sensing nodes to the reset drain voltage by resetting the gate in parallel.

[0034] Each Clx is horizontally continuous in ISO row 214 and in active imaging TDI rows 202, 204, and 206, while each CST is discontinuous (e.g., each is a separate and not continuous horizontal structure). Figure 2 illustrates multiple (N-1) channel stops 216 in ISO row 214 to limit charge diffusion between adjacent corresponding channels (not shown), where the corresponding channels extend between corresponding CSTs 110 and SN 108 in ISO row 214. Although not shown, additional channel stops exist in active imaging TDI rows 202, 204, and 206, for example, between adjacent TDI columns. In one embodiment, the continuous Clx gate eliminates the need for addressing the Clx of individual pixels and the xy matrix in the ISO rows (e.g., target-specific addressing).

[0035] Figure 3 is a schematic diagram of a readout circuit 300 for a single TDI row (e.g., the second row 204). The readout circuit 300 includes a corresponding source follower SF2, a sample-and-hold (S / H) capacitor array 302, and a comparator 304 for a column-parallel ADC for the second TDI row 204. In general, the SF2, the S / H capacitor (array) circuit 302, and the column-parallel ADC 304 provide parallel conversion functionality 1142 for the second TDI row 204. It should be understood that the corresponding readout circuits for the first row 202 and the third row 206 are not shown. Figure 4 The operating timing 400 of the image array 200 and the readout circuit (such as circuit 300) is shown.

[0036] Operation timing 400 illustrates a charge transfer cycle 402 for the three TDI rows when transferring the corresponding charge at the current time, a charge transfer cycle 404 for the three TDI rows when transferring the corresponding charge at the next time, an AD conversion window 406 for the three TDI rows during which charge from the previous cycle is converted, and an AD conversion window 408 for the three TDI rows during which charge from the current cycle is converted. Therefore, Figure 4 The overlap between charge transfer and AD conversion is shown, where the AD conversion lags by one cycle.

[0037] When the charge accumulated in the first TDI row 202 is demultiplexed to SN 1 (the first in SN 108), only CST 1 (the first in CST 110) is timed high synchronously with C1, while CST 2 and CST 3 (the second and third CSTs in CST 110, respectively) are kept low, as... Figure 4 As shown in the image.

[0038] Similarly, when the accumulated charge in the second and third TDI rows (204 and 206) is vertically transferred, the corresponding CST2 and CST3 (the second and third CSTs of CST 110) are timed high in sync with CH, while the other two corresponding CSTs (e.g., CST 1+CST 3 and CST 1+CST 2, respectively) are kept low for horizontal charge demultiplexing. These charge guiding operations are indicated by the dashed structures 208, 210, and 212 in Figure 2.

[0039] exist Figure 4 In the diagram, OSx, where x = 1, 2, and 3 are the analog voltage signals at the outputs of the corresponding SF116 (e.g., SF1, SF2, and SF3). OS2 is also shown in Figure 3. As follows, referring to Figures 3 and 4, after the charge demultiplexing of the three TDI rows 202, 204, and 206 is completed, the analog signal voltages are sampled and parallel AD converted via N parallel conversion functions 114.

[0040] When both the SHS (Sample-Hold Signal) and SHR (Sample-Hold Reset) switches are closed, and the first switch (SH1) is closed while the second switch (SH2) is open, the pixel reference level is sampled to C1. Then, both the SHR and SH1 switches are open to hold the reference level at C1. Simultaneously, the SH2 switch is closed for CDS operation of the pixel signal voltage sampled at Csig, which is carried over from the second TDI row of the previous time, while the pixel reference level is held at C2, which is sampled from the previous time. Then, for the next cycle, the SHS switch is open. An AD conversion of the signal voltage from the previous TDI row occurs when the signal charge stored in the current TDI row is demultiplexed. This completes the process. Figure 4 A loop of the operation timing diagram provided in the document.

[0041] For the next cycle, when both SHS and SHR switches are turned off again, and SH2 switch is off while SH1 switch is on, the pixel reference level is sampled to C2. Then, both SHR and SH2 switches are turned on to maintain the reference level at C2. Simultaneously, SH1 switch is turned off for CDS operation of the pixel signal voltage sampled at Csig, which is carried over from the current second TDI row, and the current pixel reference level is maintained at C1. Then, for the next cycle, the SHS switch is turned on again. An AD conversion of the signal voltage of the current TDI row occurs when the signal charge stored in the next TDI row is demultiplexed.

[0042] Therefore, referring to Figure 3, the corresponding circuit converts the corresponding signal voltage in a ping-pong manner through the following operations of the S / H capacitor array circuit: sampling the corresponding reference voltage at the current time in parallel to the corresponding first reference capacitor of the corresponding S / H capacitor array; sampling the corresponding earlier time signal voltage in parallel to the corresponding signal capacitor; and providing the corresponding CDS voltages from the corresponding earlier time reference voltage sampled at the corresponding second reference capacitor and the corresponding earlier time signal voltage sampled at the signal capacitor in parallel to the corresponding column-parallel ADC to generate the corresponding earlier time digital value.

[0043] In one embodiment, the operation further includes: receiving, in parallel, a next-time corresponding reference voltage to a corresponding second reference capacitor and a current signal voltage to a corresponding signal capacitor; and providing, in parallel, corresponding CDS voltages from the corresponding current reference voltage sampled at the corresponding first reference capacitor and the corresponding current signal voltage sampled at the signal capacitor to the corresponding column-parallel ADC to generate the corresponding current digital value.

[0044] In one implementation, the conversion of corresponding signal voltages into corresponding digital values ​​is performed in parallel at the current time and further in parallel with reading out multiple corresponding signal charges at the next time to multiple sensing nodes. In another implementation, the reading out of multiple TDI registers to receive corresponding signal charges is performed in parallel at the current time and further in parallel with converting corresponding earlier time signal voltages into corresponding earlier time digital values.

[0045] Multilevel charge guidance

[0046] Figure 5A and Figure 5BThese are corresponding implementations (500 and 520, respectively) of a column slice of an imager pixel array configured for operation of N=4 TDI rows. Section 500 shows the corresponding N=4 sensing nodes 108, which includes SN 1, SN 2, SN 3, and SN 4 for the four TDI rows (not shown). Section 500 shows an N=4 CST 110 including CST 1, CST 2, CST 3, and CST 4 in a single level or layer, similar in configuration to the N=3 CST 110 of the N=3 TDI row implementation of FIG. 2. Conversely, section 520 shows a multi-level configuration 522 of the corresponding N=4 sensing nodes 108 and CSTs. Here, the N=4 CSTs 110 define a second layer or level, which includes CST 2-1, CST 2-2, CST 2-3, and CST 2-4 adjacent to SN 502. The N CSTs with SN channels form the last layer of the cascade. Note that there is a channel stop 216 between adjacent corresponding channels. Furthermore, portion 520 includes a first layer 524 of CSTs (an embodiment of the previous layer), comprising CSTs 1-1 and CST 1-2, which supply the second layer CST 110. Therefore, in Figure 5B In the middle, when and only as Figure 5A As shown, when directly demultiplexing to one-quarter of the column via CST 1-CST 4 110, for good charge transfer, the 1-pixel column is gradually demultiplexed to half of the column via the first stage of CST 524, and then to the other half of the column (i.e., one-quarter) via the second stage 110.

[0047] In section 500, the leftmost charge of a pixel is directed to the rightmost point via CST 4, as indicated by single-dot dashed arrow 506. However, in section 520, the same charge travels in two stages, each transfer comprising a smaller transfer than the total transfer indicated by single-dot dashed arrow 506. In section 520, in the cascaded (or multi-stage) configuration of section 520, the same charge first travels (a smaller distance) to CST 1-2 as indicated by double-dot dashed arrow 526, and then travels to CST 2-4 as indicated by even-numbered dashed arrow 528.

[0048] In one implementation, this cascaded configuration can be extended to any k stages with 2^k final CST gates for better charge transfer. Between the CST stages, in this implementation, there are no channel stops for piloting operations, but as described above, there is a channel stop 216 between the last layer 110 and SN 108 of the CST.

[0049] Figure 6 This is a diagram illustrating the operation timing 600 for a two-level configuration used for N=4 TDI row operations, for example, for... Figure 5BThe configuration. Operation timing 600 shows the periods 602, 604, 606, 608, and 610 for TDI rows 1 to 4 at the current time and TDI row 1 at the next time. From Figure 6 It can be seen that: CST 1-1 is timed high during the time periods when CST 2-1 and CST 2-2 are timed high (even-numbered dashed arrows 612 and 614); CST 1-2 is timed high during the time periods when CST 2-3 and CST 2-4 are timed high (even-numbered dashed arrows 616 and 618); and CST 2-x lags behind CST 1-x by n rows, where n is the number of ISO rows between CST 1-x and CST 2-x.

[0050] Building Infrastructure Modeling (BIM)

[0051] Figure 7 This is a diagram showing a column slice of a high-speed charge-coupled CMOS TDI imager pixel array 700 according to one embodiment, the pixel array being configured for N=2 TDI row operation and using charge-guiding gates 110 associated with barrier implantation (BIM) 702. ISO row 214 includes additional gates Cl-last 704 and SET 706. Figure 8 yes Figure 7 A cross-sectional view along line A-A' or B-B' shows a portion 800 of an imager pixel array 700 according to one embodiment, which includes charge-guiding gates CSTx, x = 1 or 2, corresponding to one of the CSTs 110 associated with a barrier implant 702. Figure 9 The graph 900 shows the analog channel potentials 902 and 904 along the cutting lines A-A' and B-B' when CST1 and CST2 are timed high and low, respectively. Figure 10 This is a diagram illustrating an operation timing 1000 according to one embodiment. Operation timing 1000 relates to a high-speed charge-connected CMOS TDI imager pixel array 700. Operation timing 1000 shows timing cycles 402, 404, 406, and 408, similar to... Figure 4 The implementation scheme, but where N=2, and for Figure 7 The implementation schemes have different specific timings. The operation timing 1000 further includes the timing of the last AC gate electrode Cl-last 704 prior to the DC gate SET 706.

[0052] In one implementation scheme, such as Figure 8As shown, portion 800 includes a silicon substrate 802 on which a buried channel 804 with a gate oxide 806 is carried. On the gate oxide 806 are various gate electrodes (collectively referred to as 808), including electrodes for four phase clocks (Cl1, Cl2, O3, and Cl4) and a charge-guiding gate CSTx. A BIM 702 is located in the buried channel 804 below the CSTx and below the gate oxide 806. BIM 702 includes a p-type dopant (e.g., boron) to create a barrier when the gate CSTx clock is low. Graph 900 shows a simulation of the resulting channel potential values. The use of BIM 702 facilitates charge demultiplexing and prevents charge leakage on the CST when its clock is low.

[0053] In BIM implementation plans, for single-story non-BIM implementation plans, such as Figure 10 The timing shown Figure 4 The timing is different. Unlike a CST without BIM, charge cannot be stored beneath a CST with BIM. Although shown in embodiments including a single-layer CST 110, BIM is useful for multi-level CSTs.

[0054] bidirectional

[0055] Figure 11A and 11B This is a block diagram illustrating high-speed charge-coupled CMOS TDI imagers 1100A and 1100B configured for bidirectional operation according to corresponding embodiments. Bidirectional operation is responsive to the scanning direction (e.g., forward and reverse) performed by the CMOS TDI imager. In a first bidirectional embodiment, a CCD pixel array 1101, marked by a single-dot dashed box, is shown, comprising a plurality of TDI pixel registers 1102, each connected at its respective end to a plurality of bottom (forward) ISO registers 1004 and a plurality of top (reverse) ISO registers 1006.

[0056] In one implementation, corresponding ISO registers 1104 and 1106 include CST 110. Corresponding ISO registers 1104 and 1106 are respectively connected to SN 108, reset function 112, and SF 116. Figure 11A Multiple output structures 1108 and 1110 (not shown in the diagram) are provided, and output structures 1104 and 1110 are respectively connected to multiple S / H capacitor array circuits and column-parallel ADCs 1112 and 1114.

[0057] Figure 11AA representative column slice 1116 of the CMOS TDI imager 1100A, marked with even-numbered dashed lines, is shown. Column slice 1116 includes a column subset of TDI pixel register 1102, column subsets of ISO registers 1104 and 1106, a column subset of each of output structures 1108 and 1110, and a column subset of each of the S / H capacitor array circuit and column-parallel ADCs 1112 and 1114. The column subset of TDI pixel register 1102 is equivalent to M TDI pixel registers 104.

[0058] In the second bidirectional implementation scheme 1100B, the corresponding output structures 1108 and 1110 at the corresponding ends of the CCD pixel array 1101 are multiplexed to the S / H capacitor array and column-parallel ADC 1112 located at one end of the CMOS TDI imager 1100A.

[0059] It should be understood that Figure 11A and 11B It is simplified and can be implemented by making appropriate adjustments to the CST 110 and readout circuit 300 shown and described above.

[0060] Figure 12 This is a flowchart illustrating operation 1200 according to one embodiment. In one embodiment, the operation is performed by a means including circuitry. In one embodiment, the means includes circuitry shown in any of the corresponding embodiments of Figures 1, 2, 7, 11A, and 11B. At 1202, the operation performs readouts of a plurality of (N) TDI pixel registers to receive corresponding signal charges at a plurality of (N) sensing nodes, wherein the readouts use a plurality of (N) charge-guiding gates to guide and demultiplex the corresponding charges from the corresponding pixel registers to the plurality of sensing nodes. At 1204, the operation provides outputs from the plurality of sensing nodes to generate corresponding digital values. In one embodiment, the outputs are used to perform parallel conversions of the plurality of sensing nodes. In one embodiment, the operation of performing parallel conversions includes: converting the corresponding signal charges in parallel to corresponding signal voltages; and converting the corresponding signal voltages in parallel to corresponding digital values.

[0061] In one embodiment, the method includes resetting a plurality of sensing nodes in parallel to receive corresponding signal charges. Resetting the plurality of sensing nodes in parallel includes clearing the plurality of sensing nodes to a reset drain voltage by resetting their gates in parallel.

[0062] In one implementation, the charge is transferred vertically, guided by multiple (N) charge-guiding gates, to be horizontally demultiplexed to multiple sensing nodes.

[0063] In one implementation, a plurality of (N) charge-guiding gates define the last stage of the guiding gate, and the operation includes cascading charge (e.g., from a TDI row) to the previous stage of the guiding gate to guide to the last stage of the guiding gate.

[0064] In one implementation, each of the plurality (N) charge gates is associated with (e.g., receiving) a corresponding barrier implant (BIM) that defines a barrier when the clock of each charge gate is low.

[0065] In one implementation, a multiphase image register clock is used to time corresponding pixel registers in a pixel register, corresponding charge gates in a charge gate, and corresponding ISO registers in a plurality of (N) ISO registers for charge transfer. In one implementation, corresponding gate electrodes (Clx) are associated with corresponding phases of the clock, and their corresponding Clxes are horizontally continuous to eliminate xy matrix addressing of the corresponding Clxes in the ISO registers. In one implementation, channel stop layers are used between channels extending from the corresponding charge gates in the plurality of (N) charge gates to the corresponding sensing nodes in the plurality of (N) sensing nodes to avoid charge mixing between channels in the ISO registers.

[0066] In one implementation, each sensing node is coupled to a corresponding source follower (SF) to provide a corresponding signal voltage for conversion into a corresponding digital value.

[0067] In one embodiment, the operation is performed by a high-speed CMOS TDI image sensor comprising a plurality of CCD pixels arranged in a matrix, column slices comprising a plurality of TDI pixel registers, a plurality of ISO registers comprising CST, a plurality of output structures comprising a plurality of sensing nodes, a global reset structure and a plurality of SF, a plurality of S / H capacitor arrays and a plurality of column-parallel ADCs.

[0068] In the bidirectional implementation, the forward sensing node is connected to one end of the CCD pixel array; the reverse sensing node is connected to the other end of the CCD pixel array; and in response to the scanning direction, one of the forward sensing node and the reverse sensing node is used as multiple sensing nodes to perform the operation.

[0069] Practical implementations may include any or all of the features described herein. These and other aspects, features, and various combinations may be represented as methods, apparatus, systems, components, program products, and other combinations of the features described herein for performing functions. Numerous embodiments have been described. However, it will be understood that various modifications may be made without departing from the spirit and scope of the processes and techniques described herein. Furthermore, additional steps may be provided from the described processes, or steps may be omitted, and other components may be added to or removed from the described system. Therefore, other embodiments are within the scope of the appended claims.

[0070] Throughout the description and claims of this specification, the words “comprising” and “including,” and variations thereof, mean “including, but not limited to,” and are not intended to exclude other parts, integrals, or steps. Throughout the specification, the singular encompasses the plural unless the context requires otherwise. Specifically, where the indefinite article is used, this specification should be understood to consider both the plural and singular unless the context requires otherwise.

[0071] Features, integers, characteristics, or groups described in connection with a particular aspect, embodiment, or example of the invention should be understood to be applicable to any other aspect, embodiment, or example, unless incompatible therewith. All features disclosed herein (including any appended claims, abstract, and drawings) and / or all steps of any method or process so disclosed may be combined in any combination, except that at least some of such features and / or steps are mutually exclusive combinations. The invention is not limited to the details of any of the foregoing embodiments or examples. The invention extends to any novel one or any novel combination of features disclosed in this specification (including any appended claims, abstract, and drawings), or to any novel one or any novel combination of steps of any disclosed method or process.

Claims

1. A high-fidelity imaging method for complementary metal-oxide-semiconductor time-delay integration, comprising: Perform readouts of multiple (N) time-delay integral (TDI) pixel registers to receive corresponding signal charges at multiple (N) sensing nodes, wherein the readouts utilize multiple (N) charge-guiding gates to guide and demultiplex the corresponding charges from the corresponding pixel registers to the multiple sensing nodes; and Outputs from the plurality of sensing nodes are provided to generate corresponding digital values.

2. The method of claim 1, further comprising resetting the plurality of sensing nodes in parallel to receive the corresponding signal charges.

3. The method according to claim 2, wherein, Resetting the plurality of sensing nodes in parallel includes clearing the plurality of sensing nodes to the reset drain voltage by resetting the gates in parallel.

4. The method according to any one of claims 1 to 3, wherein, The charge is transmitted vertically and guided by the plurality of (N) charge-guiding gates to be horizontally demultiplexed to the plurality of sensing nodes.

5. The method according to any one of claims 1 to 4, wherein, The plurality (N) of charge guiding gates define the last stage of the charge guiding gate, and wherein the method includes transferring the charge to the previous stage of the guiding gate in a cascaded manner to guide it to the last stage of the charge guiding gate.

6. The method according to any one of claims 1 to 5, wherein, Each of the plurality (N) charge-guiding gates receives a corresponding barrier implanted in the BIM, wherein the barrier implantation defines the barrier when the clock of each charge-guiding gate is low.

7. The method according to any one of claims 1 to 6, comprising: The corresponding pixel register in the pixel register, the corresponding charge gate in the charge gate, and the corresponding isolation register in the plurality of (N) isolation ISO registers are timed using a multiphase image register clock to transfer charge; Using corresponding gate electrodes Clx associated with the corresponding phase of the multiphase image register clock, wherein the corresponding Clx is horizontally continuous, to eliminate xy matrix addressing of the corresponding Clx in the ISO register; and A channel stop layer is used between channels extending from the respective charge guide gates of the plurality (N) charge guide gates to the respective sensing nodes of the plurality (N) sensing nodes to avoid charge mixing between channels in the ISO register.

8. The method according to any one of claims 4 to 6, wherein, In order to transfer charge from one of the pixel registers to the corresponding charge gate in the charge gate, only the clock of the corresponding charge gate in the charge gate is high, while the clocks of the remaining charge gates of the plurality of (N) charge gates are low.

9. The method according to any one of claims 1 to 8, wherein, Each of the sensing nodes is connected to a corresponding source follower SF to provide a corresponding signal voltage for conversion into the corresponding digital value.

10. The method according to any one of claims 1 to 9, wherein, The output is provided to perform parallel conversion of the plurality of sensing nodes to produce the corresponding digital values.

11. The method of claim 10, wherein, Performing the parallel transformation includes: The corresponding signal charge is converted into the corresponding signal voltage in parallel; and The corresponding signal voltages are converted into corresponding digital values ​​in parallel.

12. The method according to claim 11, wherein, Converting the corresponding signal voltage involves performing the following operations on the sample-and-hold S / H capacitor array circuit in a ping-pong manner: The corresponding reference voltage at the current time is sampled in parallel to the corresponding first reference capacitor of the corresponding S / H capacitor array; The corresponding earlier time signal voltages are sampled in parallel onto the corresponding signal capacitors; as well as The corresponding correlated double-sampled CDS voltages from the corresponding earlier time reference voltage sampled at the corresponding second reference capacitor and the corresponding earlier time signal voltage sampled at the signal capacitor are provided in parallel to the corresponding column-parallel analog-to-digital converter (ADC) to generate the corresponding earlier time digital value.

13. The method of claim 12, further comprising: Further, the corresponding reference voltage at the next time step is received in parallel to the corresponding second reference capacitor and the current signal voltage is received to the corresponding signal capacitor; as well as The respective CDS voltages, derived from the respective current reference voltage sampled at the respective first reference capacitor and the respective current signal voltage sampled at the respective signal capacitor, are provided in parallel to the respective column-parallel ADC to generate the respective current digital value.

14. The method according to any one of claims 11 to 13, wherein, At the current time and further, in parallel with reading out the corresponding signal charges to the multiple sensing nodes at the next time, the corresponding signal voltages are converted into corresponding digital values ​​in parallel.

15. The method according to any one of claims 1 to 14, wherein, At the current time, and further in parallel with converting the corresponding earlier time signal voltage into a corresponding earlier time digital value, the readout of multiple TDI registers is performed to receive the corresponding signal charge.

16. The method according to any one of claims 1 to 15, wherein, The method is performed by a high-speed CMOS TDI image sensor, which includes a plurality of charge-connected device CCD pixels arranged in the form of a CCD pixel matrix, and the column slices of the CCD pixels include the plurality (N) TDI pixel registers; Multiple (N) isolated ISO registers, including the multiple (N) CSTs; multiple output structures, including the multiple (N) sensing nodes, a global reset structure, and multiple SFs; And multiple (N) parallel conversion units, each of which includes an S / H capacitor array and a column-parallel ADC.

17. The method of claim 16, wherein: A forward sensing node is connected to one end of the CCD pixel matrix; The reverse sensing node is connected to the other end of the CCD pixel matrix; and In response to the scanning direction, the method is performed using one of i) the forward sensing node and ii) the reverse sensing node as the plurality (N) sensing nodes.

18. A complementary metal-oxide-semiconductor time-delay integration high-fidelity imaging device, comprising: Multiple (N) Time Delay Integration (TDI) pixel registers; Multiple (N) isolated ISO registers, including multiple (N) charge-guiding gates connected to the multiple (N) TDI pixel registers; Multiple (N) output structures, including multiple (N) sensing nodes, are connected to receive corresponding signal charges read from multiple (N) TDI pixel registers. These corresponding signal charges are guided and demultiplexed by multiple (N) charge-guiding gates. The multiple (N) sensing nodes are connected to provide outputs to generate digital values. in: Each of the plurality (N) sensing nodes is configured with circuitry that provides parallel reset functionality; and Each of the plurality of (N) sensing nodes is connected via a plurality of (N) source followers (SF) to a plurality of (N) sample-and-hold (S / H) capacitor circuits and a plurality of (N) column-parallel analog-to-digital converters (ADCs) to generate a corresponding digital value for each of the respective signal charges in parallel.

19. The apparatus according to claim 18, wherein, Charge is transferred vertically, guided by the plurality of (N) charge-guiding gates, to be horizontally demultiplexed to the plurality of sensing nodes.

20. The apparatus according to claim 18 or 19, wherein, The plurality (N) charge guiding gates define the last stage of the charge guiding gates, and wherein the device includes a guiding gate cascaded to the TDI pixel register and the stage preceding the last stage of the charge guiding gates to guide the charge to the last stage of the charge guiding gates.

21. The apparatus according to claim 18 or 19, wherein, Each of the plurality (N) charge-guiding gates receives a corresponding barrier implanted in the BIM, wherein the barrier implantation defines the barrier when the clock of each charge-guiding gate is low.

22. The apparatus according to any one of claims 18 to 21, comprising: The multiphase image register clock times the corresponding pixel register in the pixel register, the corresponding charge guide gate in the charge guide gate, and the corresponding ISO register in the ISO register, in order to transfer the charge; The corresponding gate electrode Clx is associated with the corresponding phase of the multiphase image register clock, and its corresponding Clx is horizontally continuous to eliminate xy matrix addressing of the corresponding Clx in the ISO register; as well as A channel stop layer is provided between channels extending from the respective charge guide gates of the plurality of (N) charge guide gates to the respective sensing nodes of the plurality of (N) sensing nodes to avoid charge mixing between channels in the ISO register.

23. The apparatus according to any one of claims 19 to 21, configured to transfer charge from one of the pixel registers to a corresponding charge gate in the charge gates, wherein the apparatus sets only the clock of the corresponding charge gate in the charge gates to a high level, while setting the remaining charge gate clocks of the plurality (N) charge gates to a low level.

24. The apparatus according to any one of claims 18 to 23, wherein, Each of the sensing nodes is connected to the corresponding S / H capacitor via an SF for CDS operation.

25. The apparatus according to any one of claims 23 and 24, wherein, The device is configured to read out the corresponding signal charge at the next time step to the sensing node, while the column-parallel ADC converts the corresponding signal charge from the current time step.

26. The apparatus according to claim 25, wherein, Each of the sensing nodes is connected to the column-parallel ADC via a corresponding S / H capacitor array, each of the arrays including two reference capacitors and a signal capacitor for ping-pong S / H operation.

27. The apparatus according to claim 26, wherein, The corresponding S / H capacitor arrays operate together to: The corresponding reference voltage at the current time is sampled in parallel to the corresponding first reference capacitor of the corresponding S / H capacitor array; The corresponding earlier time signal voltages are sampled in parallel onto the corresponding signal capacitors; and The corresponding CDS voltages from the corresponding earlier time reference voltage sampled at the corresponding second reference capacitor and the corresponding earlier time signal voltage sampled at the signal capacitor are provided in parallel to the corresponding column-parallel ADC to generate the corresponding earlier time digital value.

28. The apparatus according to claim 27, wherein, The corresponding S / H capacitor arrays further operate together to: Furthermore, in parallel, the next time reference voltage is received to the corresponding second reference capacitor and the current signal voltage is received to the corresponding signal capacitor; and The corresponding CDS voltages, derived from the corresponding current reference voltage sampled at the corresponding first reference capacitor and the corresponding current signal voltage sampled at the signal capacitor, are provided in parallel to the corresponding column-parallel ADC to generate the corresponding current digital value.

29. The apparatus according to any one of claims 18 to 28, comprising a complementary metal-oxide-semiconductor (CMOS) TDI image sensor, wherein, Multiple charge-coupled device (CCD) pixels are arranged in the form of a CCD pixel matrix, wherein the column slices of the CCD pixels include the multiple (N) TDI pixel registers; the multiple (N) ISO registers, including the multiple (N) CSTs; the multiple (N) output structures, including the multiple (N) sensing nodes; a global reset structure providing parallel reset functionality; and the multiple (N) SFs; the multiple (N) S / H capacitor arrays; and the multiple (N) column-parallel ADCs.

30. The apparatus of claim 29, comprising: A forward sensing node is connected to the first end of the CCD pixel matrix; as well as A reverse sensing node is connected to the second end of the CCD pixel matrix; For bidirectional operation; as well as Wherein, in response to the scanning direction, one of i) the forward sensing node and ii) the reverse sensing node selectively defines the plurality (N) sensing nodes.

31. A complementary metal-oxide-semiconductor time-delay integration high-fidelity imaging apparatus, comprising circuitry configured to perform the method according to any one of claims 1 to 17.

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