A SAR / ss adc implementing a cds difference quantization operation in the analog domain

Abstract

The application provides a SAR / SS ADC for realizing CDS differential quantization operation in an analog domain, and belongs to the technical field of analog integrated circuits.The application adopts CDS differential quantization operation in an analog domain, reduces a quantization process, and improves the working speed of a readout chain; the application adopts a mixed structure of SAR ADC and SS ADC, reduces the area consumption of the SAR ADC, reduces the area by about 85%, and simultaneously adopts monotonic switching switch logic, which reduces the power consumption by about 97% compared with a traditional SAR ADC; the application adopts an asynchronous clock module to provide a clock for a counter of a conversion part of the SS ADC, avoids the input of an additional high-frequency clock signal, and simplifies the design difficulty. The implementation of the application solves the problem of designing a column-level ADC with a small area, a simple structure and capable of completing CDS differential quantization operation for a CMOS image sensor readout chain.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to a design method for a SAR / SS ADC (successive approximation register / single slope ADC) that implements CDS differential quantization in the analog domain. Background Technology

[0002] In recent years, CMOS image sensors, as the primary tool for transmitting image information, have been widely used in fields such as security, medicine, and photography. Simultaneously, the requirements for the accuracy, speed, and reliability of image sensors have become increasingly stringent. The analog-to-digital converter (ADC) is a crucial component of image sensors, capable of converting the analog voltage signals output by pixels into digital signals, and it has a vital impact on the performance of CMOS image sensors.

[0003] In CMOS image sensors, ADCs can be categorized based on their application into pixel-level ADCs, column-level ADCs, and chip-level ADCs. Among these, column-level analog-to-digital converters (ADCs) have become the mainstream ADC structure for CMOS image sensors due to their good balance between speed, design complexity, and power consumption. Common types of column-level ADCs in image sensors include ramp-type ADCs (RAMP ADCs) and successive approximation register ADCs (SAR ADCs). RAMP ADCs are simple in structure, occupy a small area, and have good linearity, but their conversion speed is slow, making them unsuitable for large image columns. SAR ADCs, on the other hand, have fast conversion speed and high accuracy, but their large area makes them difficult to integrate into the readout chain of an image sensor.

[0004] To reduce pixel reset noise, CMOS image sensors employ Correlated Double Sampling (CDS) operations. This involves reading out a reset signal upon pixel reset and then reading out an integrated signal after integration, carefully controlling the time interval between the two samplings. This ensures that the noise voltages of the two samples are nearly identical. Subtracting the two sample values ​​essentially eliminates reset noise interference, yielding the actual effective amplitude of the signal level. Traditionally, there are two methods for CDS difference calculation in the readout chain. One method uses a dual-slope ADC for addition and subtraction counting, performing the difference within a counter. However, this requires a dual-slope design and an additional high-frequency clock. The other method uses a dual-ended SAR ADC to directly quantize the difference. This method requires a large capacitor array and processing of the input analog signal to ensure common-mode level matching, increasing design complexity and making it difficult to integrate the ADC into a column-level readout chain. Therefore, designing a small-area, simple-structure column-level ADC capable of performing CDS difference quantization has become a crucial aspect of the CMOS image sensor readout chain. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a design method for a SAR / SS ADC that implements CDS differential quantization operation in the analog domain, and can be applied to the readout circuit of a CMOS image sensor.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] A SAR / SSADC that implements CDS differential quantization operation in the analog domain includes a bootstrap sample-and-hold switch, a ramp generation module, a binary MSB-Split CDAC capacitor array, a four-input dynamic comparator, an asynchronous clock generation module, and SAR / SS logic control circuitry.

[0008] The bootstrap sample-and-hold switch circuit includes 8 NMOS transistors, 4 PMOS transistors, and 1 capacitor C. G There are 8 NMOS transistors, designated NM1 to NM8, and 4 PMOS transistors, designated PM1 to PM4. The source of NM1 is grounded. The drain of NM1 is connected to the drain of PM1, the gate of NM2, and the gate of NM8. The gate of NM1 is connected to the gate of PM1 and the input signal CLK. The source of PM1 is connected to the power supply voltage. The source of PM2 is also connected to the power supply voltage. The gate of PM2 is connected to the gate of NM3 and the input signal CLK. The drain of PM2 is connected to the drain of NM3, the gate of PM4, and the drain of NM4. The source of NM2 is grounded. The drain of NM2 is connected to the source of NM3 and capacitor C.G The second terminal, the source of NM4 transistor, and the source of NM5 transistor. The drain of PM3 transistor is connected to the power supply voltage. The substrate of PM3 transistor is connected to the source of PM3 transistor, the source of PM4 transistor, the substrate of PM4 transistor, and capacitor C. G The first terminal connects the gate of PM3 to the source of NM7, the source of PM4, the gate of NM4, the gate of NM5, and the gate of NM6. The drain of NM5 is connected to the source of NM6 and the input signal VIN. The drain of NM6 is connected to the output signal VOUT. The gate of NM7 is connected to the power supply voltage, the drain of NM7 is connected to the source of NM8, and the drain of NM8 is grounded. In addition, except for PM3 and PM4, the substrates of all N-type transistors are grounded, and the substrates of all P-type transistors are connected to the power supply voltage.

[0009] The four-input dynamic comparator circuit includes six NMOS transistors, ten PMOS transistors, and two inverters. The six NMOS transistors are NM1 to NM6, the ten PMOS transistors are PM1 to PM10, and the two inverters are INV1 and INV2. The source of transistor PM1 is connected to the power supply voltage, and its gate is connected to the gate of transistor PM2 and the input signal CLK. The drain of transistor PM1 is connected to the sources of transistors PM3 and PM4. The source of transistor PM2 is connected to the power supply voltage, and its drain is connected to the sources of transistors PM5 and PM6. The gate of transistor PM3 is connected to the input signal VP, and its drain is connected to the drains of transistors PM5, NM1, PM7, and NM3. The gate of transistor PM4 is connected to the input signal VN, and its drain is connected to the drains of transistors PM6, NM2, PM10, and NM4. The gate of transistor PM5 is connected to the input signal VRP. The gate of transistor PM6 is connected to the input signal VRN. The gate of transistor NM1 is connected to the input signal CLK and the gate of transistor NM2, and the source of transistor NM1 is grounded. The source of transistor NM2 is grounded. The source of transistor PM7 is connected to the power supply voltage, and the drain of transistor PM7 is connected to the drain of transistor PM8, the drain of transistor NM3, the gate of transistor PM9, the gate of transistor NM6, and the input of inverter INV1. The source of transistor PM10 is connected to the power supply voltage, and the drain of transistor PM10 is connected to the drain of transistor PM9, the drain of transistor NM4, the gate of transistor PM8, the gate of transistor NM5, and the input of inverter INV2. The source of transistor NM3 is connected to the drain of transistor NM5. The source of transistor NM4 is connected to the drain of transistor NM6. The sources of transistors PM8 and PM9 are connected to the power supply voltage, and the sources of transistors NM5 and NM6 are grounded. The output terminal of inverter INV1 is connected to the output signal OUTN, and the output terminal of inverter INV2 is connected to the output signal OUTP.

[0010] The ramp generation module circuit includes one operational amplifier (OP), two POMS transistors, eight NMOS transistors, and three capacitors; the two POMS transistors are PM1 and PM2, the eight NMOS transistors are NM1 to NM8, and the three capacitors are C1, C2, and C3. RAMP The connections are as follows: the source of transistor PM1 is connected to the power supply voltage; the gate of transistor PM1 is connected to the drain of transistor PM1, the gate of transistor PM2, the drain of transistor NM1, and the upper plate of capacitor C2. The source of transistor PM2 is connected to the power supply voltage; the drain of transistor PM2 is connected to the drain of transistor NM4, the gate of transistor NM4, and the gate of transistor NM6. The gate of transistor NM1 is connected to the output of operational amplifier OP; the source of transistor NM1 is connected to the negative input of operational amplifier OP and the drain of transistor NM2. The positive input of operational amplifier OP is connected to a fixed voltage level V. CM The gate of transistor NM2 is connected to the input clock φ1. The source of transistor NM2 is connected to the drain of transistor NM3 and the upper plate of capacitor C1. The gate of transistor NM3 is connected to the input clock φ2, and the source of transistor NM3 is grounded. The lower plate of capacitor C1 is grounded. The lower plate of capacitor C2 is connected to the power supply voltage. The source of transistor NM4 is connected to the drain of transistor NM5, the gate of transistor NM5, and the gate of transistor NM7. The source of transistor NM5 is grounded. The source of transistor NM7 is grounded, and the drain of transistor NM7 is connected to the source of transistor NM6. The drain of transistor NM6 is connected to the output terminal V. RAMP Capacitor C RAMP The upper plate and the source of the NM8 transistor. Capacitor C RAMP The lower plate is connected to the power supply voltage. The gate of the NM8 transistor is connected to the control signal SS. ENB The drain of the NM8 transistor is connected to a fixed voltage level V. CM .

[0011] The binary MSB-SplitCDAC capacitor array includes capacitor C a C Ma C M0 C M1 ~C M5 The DAC consists of C0 to C5 and capacitor C RST C RN C RP Bootstrap sample-and-hold switch S S Switch S CDS S RN S RP Among them, the bootstrap sample-and-hold switch S S The first terminal is connected to the input signal VIN, and the bootstrap sample-and-hold switch S S The second terminal is connected to capacitor C a C Ma C M0 ~C M5 The upper electrode plates of C0 to C5 and switch SCDS The first terminal is connected to the input terminal VN of the four-input dynamic comparator. Capacitor C a The lower plate of capacitor C is always grounded; Ma C M0 ~C M5 Connect the lower electrode plates of C0 to C5 to a bidirectional switch, and connect the bidirectional switch to V. REF And ground. Switch S CDS The second terminal is connected to capacitor C RST The upper plate and the input terminal VP of the four-input dynamic comparator; capacitor C RST The lower plate is grounded. Capacitor C RN The upper plate is connected to the input terminals VRN of a four-input dynamic comparator and the switch S. RN The first terminal; capacitor C RP The upper plate is connected to the input terminals VRP of a four-input dynamic comparator and the switch S. RP The first terminal; capacitor C RN and C RP The lower electrode plates are all connected to the output terminal V of the ramp generation module. RAMP Switch S RN and S RP The second terminal is connected to a fixed voltage level V. CM .

[0012] The SAR / SS logic control circuit described above can implement the following switching methods:

[0013] During the sampling phase, the reset signal output by the pixel is sampled first: bootstrap sample-and-hold switch S. S Keep the switch S closed. CDS Keep closed, all capacitors of the DAC (C) a C Ma C M0 C M1 ~C M5 The lower plate of capacitors C0 to C5 is grounded, and capacitor C RST The upper plate of the DAC and all the upper plates of the capacitors sample the reset signal. Next, the integrated signal of the pixel output is sampled: bootstrap sample-and-hold switch S. S Keep the switch S closed. CDS When disconnected, the lower plates of all capacitors in the DAC are grounded, and the upper plates of all capacitors in the DAC sample the integrated signal.

[0014] During the conversion phase, the SAR ADC conversion phase begins first, with switch S... RN and S RP Closed, bootstrap sample-and-hold switch S S Disconnect. Connect capacitor C. Ma and C M0 ~C M5 The lower electrode plate is connected to VREF The four-input dynamic comparator maintains the voltage VN and C on the upper plate of the DAC capacitor. RST The voltage VN held at the top is compared to obtain the highest-order digit code D9. MSB represents the highest-order digit code, MSB-1 represents the second-highest-order digit code, denoted by D8, and so on, with D7 to D0 representing the digit codes of the corresponding bits. If VP > VN, the four-input dynamic comparator outputs a high value, indicating that the highest-order digit D9 = 1, and then the lower plate of C5 is switched to V. REF The lower plates of other capacitors remain unchanged; if VN > VP, the four-input dynamic comparator outputs a low value, indicating that the highest bit D9 = 0, then C... M5 The lower plate of C4 is switched to GND, while the lower plates of the other capacitors remain unchanged. The four-input dynamic comparator compares again to obtain the second-highest bit D8. If VP > VN, the four-input dynamic comparator outputs a high value, indicating that the second-highest bit D8 = 1. Then, the lower plate of C4 is switched to VND. REF The lower plates of other capacitors remain unchanged; if VN > VP, the four-input dynamic comparator outputs a low value, indicating that the second highest bit D8 = 0, then C... M4 The lower plate of the capacitor is switched to GND, while the lower plates of the other capacitors remain unchanged. The remaining bits can be generated similarly until D3 is generated. If D3 = 1, then switch S is switched... RP Disconnect; otherwise, switch S RN Disconnect. Enter the SS ADC conversion stage; the ramp generated by the ramp generation module is determined by V. RAMP The asynchronous clock module provides a clock for the counter, and the counting stops when the comparison result of the four-input dynamic comparator flips, thus obtaining the count codes D2 to D0. At this point, the conversion of all digital codes is complete.

[0015] Compared with the prior art, the present invention has the following advantages:

[0016] 1) This invention employs CDS difference quantization in the analog domain, which reduces one quantization process and improves the working speed of the readout chain.

[0017] 2) This invention adopts a hybrid structure of SAR ADC and SS ADC, which reduces the area consumption of SAR ADC by about 85% compared with traditional SAR ADC. At the same time, it adopts monotonic switching logic, which reduces the power consumption by about 97% compared with traditional SAR ADC.

[0018] 3) This invention uses an asynchronous clock module to provide a clock for the counter of the SS ADC conversion section, avoiding the input of an additional high-frequency clock signal and simplifying the design.

[0019] The implementation of this invention solves the problem of designing a column-level ADC with a small area, simple structure, and the ability to perform quantization operations of CDS difference for the readout chain of a CMOS image sensor. Attached Figure Description

[0020] Figure 1 This is a circuit diagram of a SAR / SS ADC that implements CDS differential quantization operation in the analog domain, provided by an embodiment of the present invention.

[0021] Figure 2 Timing diagrams provided for embodiments of the present invention;

[0022] Figure 3 This is a circuit structure diagram of the bootstrap sampling switch provided in an embodiment of the present invention;

[0023] Figure 4 The circuit structure diagram of the four-input dynamic comparator provided in the embodiment of the present invention;

[0024] Figure 5 The circuit structure diagram of the ramp generation module provided in the embodiment of the present invention is shown. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. The specific embodiments described herein are merely illustrative and are not intended to limit the invention.

[0026] This invention addresses the shortcomings of analog-to-digital converters in traditional CMOS image sensor readout chains by providing an improved version of a hybrid-structure SAR / SS ADC for CMOS image sensor readout chains. This ADC achieves differential operation of analog domain CDS while ensuring speed and area requirements.

[0027] like Figure 1 As shown, this invention provides a SAR / SSADC that implements CDS differential quantization in the analog domain. The circuit structure includes a bootstrap sample-and-hold switch, a ramp generation module, a binary MSB-SplitCDAC capacitor array, a four-input dynamic comparator, an asynchronous clock generation module, and a SAR / SS logic control circuit. The bootstrap sample-and-hold switch holds the input correlated double-sampled signals to capacitors C. RST and by capacitor C a C Ma C M0 C M1 ~C M5The upper plate of the DAC capacitor array composed of C0 to C5; the DAC capacitor array is composed of unit capacitors connected in parallel, and the analog signal to digital signal conversion process is realized through the SAR / SS logic control circuit; the four-input dynamic comparator compares the voltage magnitudes of the input terminals (VP+VRP) and (VN+VRN), and its output controls the asynchronous clock generation circuit; the asynchronous clock generation circuit generates the register control signal for the SAR conversion stage and the counter counting clock for the SS conversion stage; the SAR / SS logic control circuit generates the switch control signal to control the connection switch of the DAC capacitor array and the switching of the SAR conversion stage to the SS conversion stage mode.

[0028] like Figure 2 As shown, this invention provides a timing diagram for a SAR / SS ADC that implements CDS differential quantization in the analog domain: during the sampling phase (S S =1), the four-input dynamic comparator will be reset, and the bootstrap sample-and-hold switch will sample the input analog signal. When switch S CDS When = 1, the capacitor array samples the reset voltage signal onto capacitor C. RST The upper electrode plate; when switch S CDS When = 0, the capacitor array samples the integrated signal onto the capacitor C. a C Ma C M0 C M1 ~C M5 The upper plate of the DAC consists of C0 to C5. During the conversion stage (S... S =0), a four-input dynamic comparator in CLK COMP The comparison is performed on the falling edge, and the comparison result is output to the asynchronous clock control circuit. The asynchronous clock control circuit generates the register control signal for the SAR conversion stage and the counter clock for the SS conversion stage. The SAR / SS logic control circuit switches the capacitor switches according to the register control signal. Finally, the capacitor DAC network implements a binary search algorithm based on the charge redistribution principle.

[0029] like Figure 3As shown, the bootstrap sample-and-hold switch of this embodiment includes eight NMOS transistors, four PMOS transistors, and one capacitor. The eight NMOS transistors are NM1 to NM8, and the four PMOS transistors are PM1 to PM4. The connections are as follows: the source of NM1 is grounded; the drain of NM1 is connected to the drain of PM1, the gate of NM2, and the gate of NM8; the gate of NM1 is connected to the gate of PM1 and the input signal CLK. The source of PM1 is connected to the power supply voltage. The source of PM2 is connected to the power supply voltage; the gate of PM2 is connected to the gate of NM3 and the input signal CLK; the drain of PM2 is connected to the drain of NM3, the gate of PM4, and the drain of NM4. The source of NM2 is grounded; the drain of NM2 is connected to the source of NM3, the second terminal of capacitor CG, the source of NM4, and the source of NM5. The drain of the PM3 transistor is connected to the power supply voltage. The substrate of the PM3 transistor is connected to the source of the PM3 transistor, the source of the PM4 transistor, the substrate of the PM4 transistor, and the capacitor C. G The first terminal connects the gate of PM3 to the source of NM7, the source of PM4, the gate of NM4, the gate of NM5, and the gate of NM6. The drain of NM5 is connected to the source of NM6 and the input signal VIN. The drain of NM6 is connected to the output signal VOUT. The gate of NM7 is connected to the power supply voltage, the drain of NM7 is connected to the source of NM8, and the drain of NM8 is grounded. In addition, except for PM3 and PM4, the substrates of all N-type transistors are grounded, and the substrates of all P-type transistors are connected to the power supply voltage. When CLK is low, PM1 and PM2 are turned on. PM1 pulls up the gate voltage of NM8 and NM2, turning them on. NM2 then connects to capacitor C. G The voltage at the lower plate is pulled low to ground. The gate of transistor NM7 is connected to the voltage level, so NM7 is normally on. The conduction of transistor NM8 pulls down the gate voltages of transistors NM4, NM6, and PM3. Transistor NM6 is turned off, and transistor PM3 is turned on. Transistor PM3 then pulls down the gate voltage of capacitor C. G The upper plate is pulled high to the power supply voltage. When CLK is high, NM1 and NM3 are turned on. NM1 pulls down the gate voltages of NM2 and NM8, turning off NM3 and NM8. NM3 pulls down the gate voltage of PM4, turning on PM4. PM4 reduces the gate-source voltage of PM3 to 0, turning off PM3. Simultaneously, PM4 pulls up the gate voltages of NM4, NM5, and NM6, turning on NM4, NM5, and NM6. NM5 will then... G When the voltage across the lower plate rises to the input signal level VIN, since the voltage difference across the capacitor cannot change abruptly, the capacitor C... G The voltage at the upper plate will also rise by the level of the input signal. The conduction of NM4 ensures that the source-gate voltage of PM4 remains at a constant supply voltage, i.e., PM4 is on. Due to capacitor C...G Because of this, the gate-source voltage of the NM6 transistor remains constant at a given supply voltage. The on-resistance of the NM6 transistor is unaffected by the input signal level, ensuring the linearity of the sample-and-hold process.

[0030] like Figure 4As shown, the four-input dynamic comparator circuit of this embodiment includes six NMOS transistors, ten PMOS transistors, and two inverters. The six NMOS transistors are NM1 to NM6, the ten PMOS transistors are PM1 to PM10, and the two inverters are INV1 and INV2. The connections are as follows: the source of PM1 is connected to the power supply voltage; the gate of PM1 is connected to the gate of PM2 and the input signal CLK; the drain of PM1 is connected to the source of PM3 and the source of PM4. The source of PM2 is connected to the power supply voltage; the drain of PM2 is connected to the source of PM5 and the source of PM6. The gate of PM3 is connected to the input signal VP; the drain of PM3 is connected to the drain of PM5, the drain of NM1, the gate of PM7, and the gate of NM3. The gate of transistor PM4 is connected to the input signal VN. The drain of transistor PM4 is connected to the drain of transistor PM6, the drain of transistor NM2, the gate of transistor PM10, and the gate of transistor NM4. The gate of transistor PM5 is connected to the input signal VRP. The gate of transistor PM6 is connected to the input signal VRN. The gate of transistor NM1 is connected to the input signal CLK and the gate of transistor NM2. The source of transistor NM1 is grounded. The source of transistor NM2 is grounded. The source of transistor PM7 is connected to the power supply voltage. The drain of transistor PM7 is connected to the drain of transistor PM8, the drain of transistor NM3, the gate of transistor PM9, the gate of transistor NM6, and the input of inverter INV1. The source of transistor PM10 is connected to the power supply voltage. The drain of transistor PM10 is connected to the drain of transistor PM9, the drain of transistor NM4, the gate of transistor PM8, the gate of transistor NM5, and the input of inverter INV2. The source of transistor NM3 is connected to the drain of transistor NM5. The source of transistor NM4 is connected to the drain of transistor NM6. The sources of transistors PM8 and PM9 are connected to the power supply voltage, while the sources of transistors NM5 and NM6 are grounded. The output of inverter INV1 is connected to the output signal OUTN, and the output of inverter INV2 is connected to the output signal OUTP. When CLK is high, transistors PM1 and PM2 are off, and transistors NM1 and NM2 are on. When NM1 is on, it pulls the gate voltages of transistors NM3 and PM7 low to ground, causing NM3 to be off and PM7 to be on. Transistor PM7 pulls the input of inverter INV1 high to the power supply voltage, resulting in a low output OUTN after the action of inverter INV1. When NM2 is on, it pulls the gate voltages of transistors NM4 and PM10 low to ground, causing NM4 to be off and PM10 to be on. Transistor PM10 pulls the input of inverter INV2 high to the power supply voltage, resulting in a low output OUTP after the action of inverter INV2. A four-input dynamic comparator performs the reset operation. When CLK is low, PM1 and PM2 are turned on, while NM1 and NM2 are turned off. PM1 and PM2 provide current to the current branch, respectively. The gates of PM3 and PM5 are connected to the input signals VP and VRP, and the gates of PM4 and PM6 are connected to the input signals VN and VRN. PM3 and PM4 form a differential pair to shunt the current flowing out of PM1.Transistors PM5 and PM6 form a differential pair, shunting the current flowing from transistor PM2. Based on the relationship between (VP+VRP) and (VN+VRN), the charging speeds of the gates of transistors NM3 and NM4 are inconsistent. For ease of analysis, we assume (VP+VRP) > (VN+VRN). Therefore, the charging current of transistors PM6 and PM4 on the gate of transistor NM4 will be greater than the charging current of transistors PM3 and PM5 on the gate of transistor NM3. The gate voltage of transistor NM4 will exceed the threshold voltage faster than that of transistor NM3, and NM4 will turn on before NM3. Since the gates of transistors PM9 and NM6 are pulled high to the power supply voltage by transistor PM7 during the reset phase, transistor NM6 will pull low the input of inverter INV2, and the output signal OUTP becomes high after passing through inverter INV2. When NM3 turns on after NM4, the gates of transistors PM8 and NM5 are pulled low to ground by transistor NM6, and transistor PM8 turns on. The PM8 transistor pulls the input voltage of the inverter INV1 high to the power supply voltage. The output signal OUTN becomes low after passing through the inverter INV1.

[0031] like Figure 5 As shown, the ramp generation module circuit of this embodiment includes: one operational amplifier (OP), two POMS transistors, eight NMOS transistors, and three capacitors. The connections are as follows: the source of transistor PM1 is connected to the power supply voltage; the gate of transistor PM1 is connected to the drain of transistor PM1, the gate of transistor PM2, the drain of transistor NM1, and the upper plate of capacitor C2. The source of transistor PM2 is connected to the power supply voltage; the drain of transistor PM2 is connected to the drain of transistor NM4, the gate of transistor NM4, and the gate of transistor NM6. The gate of transistor NM1 is connected to the output terminal of operational amplifier OP; the source of transistor NM1 is connected to the negative input terminal of operational amplifier OP and the drain of transistor NM2. The positive input terminal of operational amplifier OP is connected to a fixed voltage level V. CM The gate of transistor NM2 is connected to the input clock φ1. The source of transistor NM2 is connected to the drain of transistor NM3 and the upper plate of capacitor C1. The gate of transistor NM3 is connected to the input clock φ2, and the source of transistor NM3 is grounded. The lower plate of capacitor C1 is grounded. The lower plate of capacitor C2 is connected to the power supply voltage. The source of transistor NM4 is connected to the drain of transistor NM5, the gate of transistor NM5, and the gate of transistor NM7. The source of transistor NM5 is grounded. The source of transistor NM7 is grounded, and the drain of transistor NM7 is connected to the source of transistor NM6. The drain of transistor NM6 is connected to the output terminal V. RAMP Capacitor C RAMP The upper plate and the source of the NM8 transistor. Capacitor C RAMP The lower plate is connected to the power supply voltage. The gate of the NM8 transistor is connected to the control signal SS. ENB The drain of the NM8 transistor is connected to a fixed voltage level V. CM When SS ENB When the value is 1, the capacitance C RAMP The upper electrode plate is reset to V CMThe output terminal V of the ramp generation circuit RAMP Also for V CM When SS ENB When the value is 0, the operational amplifier OP and transistor NM1 form a negative feedback loop, clamping the drain level of transistor NM2 to V. CM Clocks φ1 and φ2 are non-overlapping clocks, continuously charging and discharging across capacitor C1. This can be represented as a constant downward current with a magnitude of C1 × V. CM / T φ1 Transistors PM1 and PM2 form a current mirror, replicating the current in the branch containing PM1 to the branch containing PM2. Capacitor C2 removes high-frequency noise introduced by the switching circuit. Transistors NM4, NM5, NM7, and NM6 form a common-source, common-gate current mirror, replicating the current in the branch containing NM5 to the branch containing NM7. The current flowing through NM7 and NM6 affects capacitor C. RAMP Discharge is performed at the output terminal V RAMP It generates a downward ramp signal.

Claims

1. A SAR / SS ADC that implements CDS differential quantization operation in the analog domain, characterized in that, This includes a bootstrap sample-and-hold switch, a ramp generation module, a binary MSB-Split CDAC capacitor array, a four-input dynamic comparator, an asynchronous clock generation module, and SAR / SS logic control circuitry. The bootstrap sample-and-hold switch circuit includes 8 NMOS transistors, 4 PMOS transistors, and 1 capacitor C. G The system consists of 8 NMOS transistors (NM1 to NM8) and 4 PMOS transistors (PM1 to PM4). The source of NM1 is grounded, and its drain is connected to the drain of PM1, the gate of NM2, and the gate of NM8. The gate of NM1 is connected to the gate of PM1 and the input signal CLK. The source of PM1 is connected to the power supply voltage. The source of PM2 is also connected to the power supply voltage, and its gate is connected to the gate of NM3 and the input signal CLK. The drain of PM2 is connected to the drain of NM3, the gate of PM4, and the drain of NM4. The source of NM2 is grounded, and its drain is connected to the source of NM3 and capacitor C. G The second terminal, the source of NM4 transistor, and the source of NM5 transistor; the drain of PM3 transistor is connected to the power supply voltage, and the substrate of PM3 transistor is connected to the source of PM3 transistor, the source of PM4 transistor, the substrate of PM4 transistor, and capacitor C. G The first terminal connects the gate of PM3 to the source of NM7, the source of PM4, the gate of NM4, the gate of NM5, and the gate of NM6; the drain of NM5 is connected to the source of NM6 and the input signal VIN; the drain of NM6 is connected to the output signal VOUT; the gate of NM7 is connected to the power supply voltage, the drain of NM7 is connected to the source of NM8, and the drain of NM8 is grounded; in addition, except for PM3 and PM4, the substrates of all N-type transistors are grounded, and the substrates of all P-type transistors are connected to the power supply voltage. The four-input dynamic comparator circuit includes six NMOS transistors, ten PMOS transistors, and two inverters. The six NMOS transistors are NM1 to NM6, the ten PMOS transistors are PM1 to PM10, and the two inverters are INV1 and INV2. The source of PM1 is connected to the power supply voltage, the gate of PM1 is connected to the gate of PM2 and the input signal CLK, and the drain of PM1 is connected to the source of PM3 and P... The source of transistor M4; the source of transistor PM2 is connected to the power supply voltage, and the drain of transistor PM2 is connected to the source of transistors PM5 and PM6; the gate of transistor PM3 is connected to the input signal VP, and the drain of transistor PM3 is connected to the drain of transistor PM5, the drain of transistor NM1, the gate of transistor PM7, and the gate of transistor NM3; the gate of transistor PM4 is connected to the input signal VN, and the drain of transistor PM4 is connected to the drain of transistor PM6, the drain of transistor NM2, the gate of transistor PM10, and the gate of transistor NM4; PM The gate of transistor 5 is connected to the input signal VRP; the gate of transistor PM6 is connected to the input signal VRN; the gate of transistor NM1 is connected to the input signal CLK and the gate of transistor NM2, and the source of transistor NM1 is grounded; the source of transistor NM2 is grounded; the source of transistor PM7 is connected to the power supply voltage, and the drain of transistor PM7 is connected to the drain of transistor PM8, the drain of transistor NM3, the gate of transistor PM9, the gate of transistor NM6, and the input terminal of inverter INV1; the source of transistor PM10 is connected to the power supply voltage, and PM1... The drain of transistor 0 is connected to the drain of transistor PM9, the drain of transistor NM4, the gate of transistor PM8, the gate of transistor NM5, and the input terminal of inverter INV2; the source of transistor NM3 is connected to the drain of transistor NM5; the source of transistor NM4 is connected to the drain of transistor NM6; the sources of transistors PM8 and PM9 are connected to the power supply voltage, and the sources of transistors NM5 and NM6 are grounded; the output terminal of inverter INV1 is connected to the output signal OUTN, and the output terminal of inverter INV2 is connected to the output signal OUTP. The ramp generation module circuit includes one operational amplifier (OP), two POMS transistors, eight NMOS transistors, and three capacitors; the two POMS transistors are PM1 and PM2, the eight NMOS transistors are NM1 to NM8, and the three capacitors are C1, C2, and C3. RAMP In this configuration, the source of transistor PM1 is connected to the power supply voltage, and its gate is connected to the drain of transistor PM1, the gate of transistor PM2, the drain of transistor NM1, and the upper plate of capacitor C2. The source of transistor PM2 is connected to the power supply voltage, and its drain is connected to the drain of transistor NM4, the gate of transistor NM4, and the gate of transistor NM6. The gate of transistor NM1 is connected to the output of operational amplifier OP, and its source is connected to the negative input of operational amplifier OP and the drain of transistor NM2. The positive input of operational amplifier OP is connected to a fixed voltage level V. CM The gate of transistor NM2 is connected to the input clock φ1, and the source of transistor NM2 is connected to the drain of transistor NM3 and the upper plate of capacitor C1. The gate of transistor NM3 is connected to the input clock φ2, and the source of transistor NM3 is grounded. The lower plate of capacitor C1 is grounded, and the lower plate of capacitor C2 is connected to the power supply voltage. The source of transistor NM4 is connected to the drain of transistor NM5, the gate of transistor NM5, and the gate of transistor NM7. The source of transistor NM5 is grounded, the source of transistor NM7 is grounded, the drain of transistor NM7 is connected to the source of transistor NM6, and the drain of transistor NM6 is connected to the output terminal V. RAMP Capacitor C RAMP The upper plate and the source of the NM8 transistor; capacitor C RAMP The lower plate of the NM8 transistor is connected to the power supply voltage; the gate of the NM8 transistor is connected to the control signal SS. ENB The drain of the NM8 transistor is connected to a fixed voltage level V. CM ; The binary MSB-Split CDAC capacitor array includes capacitors C a C Ma C M0 C M1 ~C M5 The DAC consists of C0 to C5 and capacitor C RST C RN C RP Bootstrap sample-and-hold switch S S Switch S CDS S RN S RP Among them, the bootstrap sample-and-hold switch S S The first terminal is connected to the input signal VIN, and the bootstrap sample-and-hold switch S S The second terminal is connected to capacitor C a C Ma C M0 ~C M5 The upper plates of C0 to C5 and switch S CDS The first terminal and the input terminal VN of the four-input dynamic comparator; capacitor C a The lower plate of capacitor C is always grounded; Ma C M0 ~C M5 Connect the lower electrode plates of C0 to C5 to a bidirectional switch, and connect the bidirectional switch to V. REF and ground; switch S CDS The second terminal is connected to capacitor C RST The upper plate and the input terminal VP of the four-input dynamic comparator; capacitor C RST The lower electrode is grounded; capacitor C RN The upper plate is connected to the input terminals VRN of a four-input dynamic comparator and the switch S. RN The first terminal; capacitor C RP The upper plate is connected to the input terminals VRP of a four-input dynamic comparator and the switch S. RP The first terminal; capacitor C RN and C RP The lower electrode plates are all connected to the output terminal V of the ramp generation module. RAMP Switch S RN and S RP The second terminal is connected to a fixed voltage level V. CM ; The SAR / SS logic control circuit generates a switch control signal to control the connection switch of the DAC capacitor array and the switching mode from SARADC conversion stage to SSADC conversion stage.

2. The SAR / SS ADC for implementing CDS differential quantization operation in the analog domain according to claim 1, characterized in that, The SAR / SS logic control circuit implements the following switching method: During the sampling phase, the reset signal output by the pixel is sampled first: bootstrap sample-and-hold switch S. S Keep the switch S closed. CDS Keep closed, all capacitors C of the DAC a C Ma C M0 C M1 ~C M5 The lower plates of C0 to C5 are grounded, and capacitor C... RST The upper plate of the DAC and the upper plate of all capacitors sample the reset signal; Secondly, the integral signal output by the sampled pixel: bootstrap sample-and-hold switch S S Keep the switch S closed. CDS When disconnected, the lower plates of all capacitors in the DAC are grounded, and the upper plates of all capacitors in the DAC sample the integrated signal. During the conversion phase, the SAR ADC conversion phase begins first, with switch S... RN and S RP Closed, bootstrap sample-and-hold switch S S Disconnect; disconnect capacitor C Ma and C M0 ~C M5 The lower electrode plate is connected to V REF The four-input dynamic comparator maintains the voltage VN and C on the upper plate of the DAC capacitor. RST The voltage VN held at the top is compared to obtain the highest-order digit code D9. MSB represents the highest-order digit code, MSB-1 represents the second-highest-order digit code, denoted by D8, and so on, with D7 to D0 representing the digit codes of the corresponding bits. If VP > VN, the four-input dynamic comparator outputs a high value, indicating that the highest-order digit D9 = 1, and then the lower plate of C5 is switched to V. REF The lower plates of other capacitors remain unchanged; if VN > VP, the four-input dynamic comparator outputs a low value, indicating that the highest bit D9 = 0, then C... M5 The lower plate of C4 is switched to GND, while the lower plates of other capacitors remain unchanged. The four-input dynamic comparator compares again to obtain the second-highest bit D8. If VP > VN, the four-input dynamic comparator outputs a high value, indicating that the second-highest bit D8 = 1. Then, the lower plate of C4 is switched to VND. REF The lower plates of other capacitors remain unchanged; if VN > VP, the four-input dynamic comparator outputs a low value, indicating that the second highest bit D8 = 0, then C... M4 The lower plate of the capacitor is switched to GND, while the lower plates of the other capacitors remain unchanged; the remaining bits can be generated similarly until D3 is generated. If D3 = 1, then switch S is switched. RP Disconnect; otherwise, switch S RN Disconnect; enter the SS ADC conversion stage, the ramp generated by the ramp generation module is controlled by V RAMP The asynchronous clock module provides a clock for the counter, and the counting stops when the comparison result of the four-input dynamic comparator flips, thus obtaining the count codes D2 to D0. At this point, the conversion of all digital codes is complete.

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