A resource-saving short-chain time-to-digital converter and its conversion method

Abstract

This invention belongs to the field of time measurement technology and discloses a resource-saving short-chain time-to-digital converter and its conversion method. It utilizes a delay unit and conversion circuit to build a local oscillator, which flips the output state at fixed time intervals during a continuous high-level input signal. The time at which the local oscillator causes the level to flip is known. The time of the last flip is obtained using TDL and TDC, and the start and last flip times are obtained by recording the number of flips of the local oscillator. The resource-saving short-chain time-to-digital converter provided by this invention has good linearity, completely avoiding nonlinearity problems caused by inconsistent line lengths introduced across multiple resource blocks. The resource-saving short-chain time-to-digital converter has a simple and flexible structure, low resource consumption, and high utilization rate. It has good robustness and can be directly ported between different channels or even devices, and can correct temperature-induced drift online.

Description

Technical Field

[0001] This invention belongs to the field of time measurement technology, and in particular relates to a resource-saving short-chain time-to-digital converter and its conversion method. Background Technology

[0002] Currently, Time-to-Digital Converters (TDCs), as time measurement tools with picosecond-level accuracy, are widely used in various fields, including biomedicine and communications engineering. A simple TDC can be implemented by directly counting the changes in a high-frequency clock, but this method is limited by the clock frequency, typically in the nanosecond range.

[0003] Existing time-to-amplitude (TDC) converters can be categorized into analog-based and digital-based TDCs based on their implementation methods. Analog-based TDCs include time-to-amplitude conversion (TTC) or time stretching. These methods introduce analog quantities, which are susceptible to noise interference, making the test results vulnerable to noise-induced interference. Furthermore, these methods often have a longer single-measurement time than the time interval to be measured, resulting in excessively long dead times and hindering high-frequency measurements. Therefore, although analog-based TDCs can achieve good nonlinear performance, even sub-picosecond time resolution, they are not common. Conversely, digital-based TDCs are more popular because they can be deployed and iterated more quickly (on FPGAs), have more compact hardware structures, offer greater flexibility, and are more tolerant of noise interference.

[0004] The first digital solution is an interpolation scheme, namely the Nutt method. Its basic idea is to interpolate the system clock using multiple delay units (typically carry modules in FPGAs). In the Nutt method, the time to be measured is divided into two parts: "coarse" time and "fine" time. The "coarse" time is obtained directly using the high-frequency system clock, i.e., by counting the number of changes in the system clock within the measured time interval. The "fine" time is obtained by interpolating a series of delay units in series to form a long chain (also called a tapped delay line, TDL), and interpolating it between system clocks. It is obtained by counting the number of delay units in the chain that are triggered. The "fine" time can be measured by obtaining the delay time caused by each delay unit in the TDL chain through code density testing, and the number of triggers of these units can be directly obtained through measurement, thus yielding the value of the "fine" time. Combining the "coarse" and "fine" times, the final time interval can be directly calculated.

[0005] This method relies on the premise that each delay unit in the TDL chain has the same delay time, which determines the measurement's time resolution. However, the characteristics of these delay units are susceptible to inherent device defects, voltage and temperature dynamics, leading to severe nonlinearity issues. Furthermore, the inherent delay of each delay unit is determined by its manufacturing process and cannot be modified; therefore, once the hardware platform is determined, the time resolution of the TDC is fixed. To address these problems, numerous methods have been proposed, primarily categorized as multi-chain averaging topology, cursor methods, bin-to-bin calibration, and WaveUnion architecture.

[0006] While the aforementioned methods can improve certain aspects of TDC performance, they often come at a cost, leading to other problems. For example, multi-chain average topologies consume more resources. The cursor method, while significantly mitigating inherent nonlinearity in the device and improving time resolution, even exceeding the inherent time delay of the delay cells, requires more logic resources and a longer conversion rate, resulting in longer dead times. The bin-to-bin calibration method only alleviates the nonlinearity of the delay cells and has poor scalability; it requires reprocessing when changing channel positions or hardware platforms, reducing robustness. The WaveUnion method, while resource-efficient, requires complex ring oscillator design, and its performance depends on the non-uniformity between delay cells. However, with advancements in semiconductor manufacturing processes, this non-uniformity is now largely negligible.

[0007] Using Application-Specific Integrated Circuits (ASICs) for TDC designs can significantly solve the above problems and achieve better TDC performance. However, on the one hand, they require longer design cycles and higher manufacturing costs, leading to slow technology iteration and thus greatly limiting the pace of development; on the other hand, they are not reusable, resulting in poor flexibility. Therefore, only groups with rich experience and resources can afford to choose ASIC-based solutions. This phenomenon may, to some extent, stifle the pace of innovation, so many TDC designs are often first verified using FPGAs before being mass-produced using ASICs.

[0008] Traditional time-delay control (TDC) typically strings delay units together in a straight line. For example, in an FPGA-based TDC, the delay unit is chained together using the FPGA's carry unit as the delay unit. To ensure the resources in the TDC chain can fully "interpolate" the system clock, the inherent delay of the entire delay chain must be greater than the counter's clock cycle; this necessary condition is often called the clock condition. The delay of the entire delay chain is determined by the inherent delay of each delay unit and the total number of delay units. Therefore, with a fixed counter clock, when the inherent delay of a delay unit is small, a large number of delay units are needed, resulting in a very long traditional single-chain TDC on the FPGA. This leads to the following technical problems:

[0009] (1) Poor linearity. To ensure high linearity, an ideal TDC requires that the propagation delay between each delay unit be the same. However, in practice, only delay units within the same resource block can guarantee good consistency; delay units between different resource blocks have large inherent delay differences due to the large differences in wiring resources, resulting in serious nonlinearity problems.

[0010] (2) Large error. When the TDC chain is too long, the "bubble" problem will be aggravated. That is, when a signal passes through a chain, theoretically all the delay units it passes through will be triggered, that is, the output should be all "1" (or conversely "0"). However, when the chain is long, there may be many "0" in the trigger segment that is all "1". This will seriously interfere with the measurement results of TDC.

[0011] (3) Poor robustness. The inherent delay time of the delay unit is greatly affected by temperature. When the temperature changes significantly, it will not only affect the linearity of the delay unit in the chain, but also cause the inherent delay of the entire unit to shift, resulting in measurement errors.

[0012] Based on the above analysis, the problems and shortcomings of the existing technology are as follows:

[0013] (1) Existing TDC based on analog schemes introduces analog quantities in implementation, and analog quantities are easily affected by noise, which makes the test results easily affected by noise. The single measurement time is often longer than the time interval to be measured, and the long conversion time leads to an excessively long dead time, thus making it impossible to perform high-frequency measurements.

[0014] (2) The characteristics of the delay units in the existing Nutt method are easily affected by inherent defects in the device, dynamic changes in voltage and temperature, etc., leading to serious nonlinear problems; the inherent delay of each delay unit is determined by the manufacturing process and cannot be modified. Once the hardware platform is determined, the time resolution of TDC is also determined.

[0015] (3) Existing cursor methods require more logic resources and longer conversion rates, resulting in longer dead time; bin-to-bin calibration methods have poor scalability and need to be reprocessed when the channel position is changed or the hardware platform is replaced, which reduces robustness; the WaveUnion method requires a complex ring oscillator design.

[0016] (4) Existing TDC design methods using application-specific integrated circuits require long design cycles and high manufacturing costs, resulting in slow technology iteration and limiting the speed of development; and they cannot be reused, resulting in poor flexibility; while traditional TDC has problems such as poor linearity, large error and poor robustness. Summary of the Invention

[0017] To address the problems existing in the prior art, this invention provides a resource-saving short-chain time-to-digital converter and its conversion method.

[0018] This invention is implemented as follows: a resource-saving short-chain time-to-digital conversion method, which includes: constructing a local oscillator using a delay unit and a conversion circuit; flipping the output state at fixed time intervals during a continuous high-level period of the input signal; and obtaining the start time and the time of the last flip by recording the number of flips of the local oscillator.

[0019] Furthermore, the timing of the level transition caused by the local oscillator is known. A local oscillator refers to a signal level that can be observed to transition regularly during measurement along the delay chain. The timing of each level transition is determined by the time difference of the delay units (not on the delay chain). When the signal begins to arrive on the delay chain, the delay units (not on the delay chain) and the conversion circuit will transition the level signal on the delay chain at regular intervals (specifically, the time difference of the delay units), making the delay units and the conversion circuit appear to function as a local oscillator. The oscillation time or period of the local oscillator can be freely configured and does not necessarily need to be periodic.

[0020] Furthermore, the time of the last flip is obtained using TDL and TDC. The signal end time and the oscillator's last flip time are observed on the delay chain. The time from the start of the signal to the last flip, observed on the delay chain, is determined by the configuration process and is known. However, the time from the last flip to the signal end is uncertain and can be measured through the triggering state on the delay chain, i.e., how many delay units are triggered. Thus, through two-stage measurements, the total fine time components can be obtained.

[0021] Furthermore, in actual implementation, the local oscillator generates more than two flips, the specific number of flips being determined based on clock conditions and the delay chain measurement range.

[0022] Furthermore, resource-saving short-chain structure time-to-digital conversion methods also include:

[0023] A local oscillator is formed by a first delay unit, a second delay unit, and a conversion circuit. The local oscillator is used in conjunction with TDL and TDC to measure the time interval of the signal under test. The delay units in the local oscillator are freely configurable by software and are preferably IDELAY resources in Xilinx FPGA. The delay units in the delay chain have fixed delays and are preferably CARRY4 / 8 resources in Xilinx FPGA.

[0024] Furthermore, resource-saving short-chain structure time-to-digital conversion methods also include:

[0025] The input to the TDL TDC delay chain is the output waveform of the conversion circuit, and the measurement range Mτ satisfies the conditions Mτ>ΔT2-ΔT1 and the clock condition Mτ>T. clk +ΔT1-ΔT2; where M is the number of delay units in the delay chain, τ is the inherent delay of the delay unit, and T clk This is the system's "coarse" clock cycle.

[0026] When a signal with a time interval of Δt is input, the starting time T s =ΔT i +M s *τ+N s *T clk End time T e =ΔT j +M e *τ+N e *T clk Where i and j represent the number of times the local oscillator output signal flips at the rising and falling edges of the input signal, and M... s and M e N represents the number of triggered units on the delay chain. s and N e If the integer value of the coefficient clock is represented, then Δt = T e -T s =(N e -N s )*T clk +(ΔT j -ΔT i )+(M e -M s )*τ.

[0027] Another objective of this invention is to provide a resource-saving short-chain time-to-digital converter that applies the aforementioned resource-saving short-chain time-to-digital conversion method. The resource-saving short-chain time-to-digital converter includes a first delay unit, a second delay unit, and a conversion circuit. The delay times of the first delay unit and the second delay unit are ΔT1 and ΔT2, respectively, and ΔT2>ΔT1. After passing through the first delay unit and the second delay unit, the signal is converted into two delayed signals and directly input into the conversion circuit to be converted into one signal.

[0028] Another object of the present invention is to provide a computer device, the computer device including a memory and a processor, the memory storing a computer program, which, when executed by the processor, causes the processor to perform the steps of the resource-saving short-chain structure time-to-digital conversion method described above.

[0029] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the resource-saving short-chain time-to-digital conversion method described above.

[0030] Another objective of this invention is to provide an information data processing terminal for implementing the aforementioned resource-saving short-chain time-to-digital converter.

[0031] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0032] First, addressing the technical problems existing in the prior art and the difficulty of solving them, this paper closely analyzes, in conjunction with the technical solution to be protected by this invention and the results and data obtained during the research and development process, how the technical solution of this invention solves the technical problems, and the inventive technical effects brought about by solving these problems. The specific description is as follows:

[0033] 1. Excellent linearity. The time-to-digital conversion method proposed in this invention utilizes delay units and conversion circuits to build a local oscillator, further subdividing the system clock cycle, thereby reducing the measurement range of the delay chain in TDL TDC. While ensuring that the inherent delay of the delay unit remains unchanged, it reduces the number of delay units required for the delay chain in TDL TDC, thus realizing that all delay units are placed in a single logic block, completely avoiding the nonlinearity problem caused by inconsistent line lengths introduced across multiple resource blocks.

[0034] 2. Simple and flexible structure, low resource consumption, and high utilization rate. The resource-saving short-chain time-to-digital conversion method proposed in this invention has a simple and flexible structure. It only requires fixed delay units combined with a small number of basic logic gate resources to build a local oscillator to subdivide the system clock cycle. Then, the short delay chain built with a small number of delay units can be used for further measurement, reducing resource consumption. At the same time, due to the use of short delay chains, the layout can be more compact, thereby reducing resource waste caused by layout and improving resource utilization. Conversely, when long chain resources are laid out in a limited space, the unused part may not be able to be laid out again, resulting in resource waste. This is similar to memory allocation in computer systems. Long chains are equivalent to large blocks of contiguous free space, while short chains are equivalent to small segments of memory in different spaces. Large blocks of contiguous memory are well known to be scarce resources and are very limited; while small blocks of free memory are more abundant. Successfully utilizing these memory segments will inevitably improve resource utilization.

[0035] 3. It exhibits good robustness and can be directly ported between different channels and even devices, allowing for online correction of temperature-induced drift. During device manufacturing, resources in adjacent locations exhibit better similarity, i.e., better consistency. This property does not change with channel or device variations. Therefore, the TDC built based on adjacent location resources in this invention has better time delay consistency for each delay unit. When this TDC is ported to other channels or even other devices, this consistency is still preserved, resulting in better robustness of the TDC proposed in this invention. Furthermore, this invention utilizes logic resources with freely configurable delay times, such as IDELAY cells in Xilinx FPGAs. These are typically temperature-insensitive. A local oscillator built using these resources can generate a level signal with a constant switching time interval depending on temperature. Combined with a delay chain, the number of triggered units on the delay chain within the switching time interval can be measured at different temperatures. This allows for the calculation of the inherent delay time of a single delay unit under different temperature conditions, thereby compensating for drift caused by temperature changes.

[0036] Second, considering the technical solution as a whole or from a product perspective, the technical effects and advantages of the technical solution to be protected by this invention are specifically described as follows:

[0037] (1) Technical effect: One of the standards for measuring the performance of TDC is DNL and INL. The smaller the value, the better the linearity and the better the performance. Generally, the DNL and INL of a qualified TDC should be less than 1 LSB. The code density test results of the TDC of this invention show that, without any calibration method, its INL and DNL are both less than 0.6 LSB, which is excellent performance.

[0038] (2) Advantages: When TDC is used, it needs to be able to make accurate time measurements. The accuracy mainly depends on its minimum resolution and linearity. The technical effect of this invention can significantly improve the measurement accuracy when the technology is used.

[0039] Third, as supplementary evidence of the inventive step of the claims of this invention, it is also reflected in the following important aspects:

[0040] (1) The technical solution of this invention fills a technological gap in the domestic and international industry: traditional TDCs suffer from poor linearity, poor robustness, complex structure, and low resource utilization. To solve the problems of linearity and time resolution, either more resources need to be introduced, resulting in higher resource consumption and a more complex structure; or a lot of work needs to be done for calibration, resulting in extremely poor robustness. Although there is an improvement in performance, it comes at a great cost and is difficult to widely apply, especially in multi-channel scenarios, where it is difficult to promote. The resource-saving short-chain structure time-to-digital converter provided by this invention fills this technological gap.

[0041] (2) The technical solution of the present invention solves the technical problem that people have long wanted to solve but have never been able to succeed in: the current TDC based on digital circuits has serious nonlinearity problems. The usual solutions require too much resource cost or time cost, while the TDC structure of the present invention uses very few resources and does not require calibration (i.e. no additional time cost or computing cost) to perfectly solve the nonlinearity problem. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a flowchart of the resource-saving short-chain structure time-to-digital conversion method provided in this embodiment of the invention;

[0044] Figure 2 This is a schematic diagram of the resource-saving short-chain structure time-to-digital conversion method provided in this embodiment of the invention;

[0045] Figure 3 This is a schematic diagram of the "fine" time measurement part provided in an embodiment of the present invention;

[0046] Figure 4A This is an experimental result diagram of TDC in code density testing provided by an embodiment of the present invention;

[0047] Figure 4BThis is an experimental effect diagram of TDC in DNL provided by an embodiment of the present invention;

[0048] Figure 4C This is an experimental result diagram of TDC in INL provided by an embodiment of the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0050] To address the problems existing in the prior art, this invention provides a resource-saving short-chain time-to-digital converter and its conversion method. The invention will be described in detail below with reference to the accompanying drawings.

[0051] like Figure 1 As shown, the resource-saving short-chain structure time-to-digital conversion method provided in this embodiment of the invention includes the following steps:

[0052] S101 uses a delay unit and a conversion circuit to build a local oscillator, which flips the output state at fixed time intervals during the continuous high-level time of the input signal.

[0053] S102, use TDL TDC to obtain the time of the last flip;

[0054] S103, the time when the local oscillator causes the level to flip is known. The start time and the time of the last flip are obtained by recording the number of flips of the local oscillator.

[0055] The core idea of ​​the resource-saving short-chain time-to-digital conversion method of this invention is to build a local oscillator using delay units and conversion circuits. The input signal is flipped at fixed time intervals during its continuous high-level period. Since the time of level flips caused by the local oscillator is known, the start time and the time of the last flip can be obtained by recording the number of flips. The time of the last flip is obtained using TDL and TDC. Because the level flips generated by the local oscillator divide the system's "coarse" clock, the "fine" time measurement range required by TDL and TDC becomes smaller, meaning the measurement range required by the TDC delay chain is smaller. With the delay unit delay size of the delay chain remaining unchanged, fewer delay units are required, resulting in lower resource consumption. This example assumes the local oscillator generates at most two flips. In actual implementation, the local oscillator may need to generate more than two flips; the specific number of flips depends on clock conditions and the measurement range of the delay chain.

[0056] Figure 2 This diagram illustrates the basic principle of measuring the time interval of a signal under test using a local oscillator combined with a TDL (Time Limit Registry) and a TDC (Time Limit Registry) according to an embodiment of the present invention. The diagram shows a first delay unit, a second delay unit, and a conversion circuit constituting a local oscillator. The delay times of the first and second delay units are ΔT1 and ΔT2, respectively, with ΔT2 > ΔT1. After passing through the first and second delay units, the signal is converted into two delayed signals, which are then directly input to the conversion circuit and converted into a single signal. The output waveform is shown by the green line in the diagram. Note that the delay units here are different from the delay units in the TDC delay chain. The delay units here can be freely configured via software, such as the IDELAY resource in a Xilinx FPGA; the delay units in the delay chain have fixed delays, such as the CARRY4 / 8 resource in a Xilinx FPGA.

[0057] The input to the TDL TDC delay chain is the output waveform of the conversion circuit, and its measurement range Mτ should satisfy the conditions Mτ>ΔT2-ΔT1 and the clock condition Mτ>T. clk +ΔT1-ΔT2, where M is the number of delay units in the delay chain, τ is the inherent delay of the delay unit, and T clk This is the system's "coarse" clock cycle.

[0058] When a signal with a time interval of Δt is input, its start time T s =ΔT i +M s *τ+N s *T clk End time T e =ΔT j +M e *τ+N e *T clk Where i and j represent the number of times the local oscillator output signal flips at the rising and falling edges of the input signal, and M s and M e N represents the number of triggered units on the delay chain. s and N e The integer value of the coefficient clock is represented, so Δt = T e -T s =(N e -N s )*T clk +(ΔT j -ΔT i )+(M e -M s )*τ.

[0059] The resource-saving short-chain time-to-digital converter provided in this embodiment of the invention includes a first delay unit, a second delay unit, and a conversion circuit; wherein the delay times of the first delay unit and the second delay unit are ΔT1 and ΔT2, respectively, and ΔT2>ΔT1; after the signal passes through the first delay unit and the second delay unit, it is converted into two delayed signals and directly input into the conversion circuit to be converted into one signal.

[0060] This invention can be applied to numerous fields, including biomedicine, communications engineering, and nuclear physics. Positron emission tomography (PET), as one of the most advanced imaging technologies in biomedicine, can non-invasively diagnose cancer early, enabling timely treatment and improving patient survival rates. The accuracy of PET detectors in measuring the time-of-flight of high-energy particles and calculating their deposition energy is crucial to PET spatial resolution. Currently, the main measurement method uses time-of-flight detection (TDC). The high linearity of this invention can effectively improve the accuracy of measurement results. Furthermore, current PET detectors have dozens of signal readout channels, requiring dozens of TDCs at the back end, and for some specialized methods, even hundreds. The low resource consumption and high robustness of this invention can significantly reduce the complexity of multi-channel integration. In communications engineering, products with high time accuracy requirements, such as lidar, mostly use TDCs for measurement. The high linearity of this invention can make the measurement results more accurate. In nuclear physics, such as particle detection, high-precision TDCs are required for measurement, and this invention can greatly improve measurement accuracy.

[0061] The embodiments of the present invention have achieved some positive results during the research and development or use process, and have indeed great advantages compared with the prior art. The following content describes them in conjunction with the data, charts and other information of the experimental process.

[0062] The specific implementation process of this invention is described using a Xilinx Ultrascale FPGA as an example. The TDC provided by this invention has the same measurement principle as the TDL TDC, that is, it measures "coarse" time through the system clock and measures "fine" time through delay chain resources. The innovation of this invention lies in the creative update of the measurement structure for "fine" time. Therefore, this paper only describes the implementation process of "fine" time measurement.

[0063] like Figure 3The diagram shows the system implementation schematic. The entire system consists of three parts: a signal delay unit, a conversion circuit, and a delay chain. The signal delay unit contains three IDELAY units and three D flip-flops; the conversion circuit contains six basic logic gates; and the delay chain is a short chain composed of 30 CARRY8 units. The measurement range of the IDELAY delay time and the short chain is marked in the diagram. Since each CARRY8 has a delay time of only about 30 ps, ​​the measurement range of the short chain composed of 30 CARRY8 units is only 900 ps. The above settings satisfy the clock conditions: 900 - 0 ≤ 900, 1800 - 900 ≤ 900, 1800 + 30 × 30 = 2700 ps > T. clk = 2.5ns, i.e., a 400MHz system clock. During operation, the time interval to be measured can be obtained by detecting the latching results of the D flip-flops and the triggering state on each chain. Let the delays caused by the delay units before each chain from top to bottom be ΔT1, ΔT2, and ΔT3, respectively, the inherent delay of the delay units on each short chain be τ, and the system clock period be T. clk The measurement process for "fine" time is as follows:

[0064] (1) Detect the result of the D flip-flop. When the result is 001, 011, 111, the measurement result is a rising edge; when the result is 110, 100, 000, the measurement result is a falling edge.

[0065] (2) Based on the results of the D flip-flop, when the results of the D flip-flop are 001, 111, 100, the position of the "01" transition edge on the short chain is P. 01 When the result of the D flip-flop is 011, 110, 000, the position of the "10" transition edge on the short chain is P. 10 .

[0066] (3) Calculate the rise time: T s =ΔT i +P 01(10) ×τ, where i is the number of 1s in the result of the D flip-flop;

[0067] (4) Calculate the fall time: T e =ΔT j +P 01(10) ×τ, where j is the number of 0s in the result of the D flip-flop;

[0068] (5) Determine T s With T e The number of system clock cycles between transition edges is N s and N e Then the pulse interval ΔT = (N e -N s )×T clk +Ts -T e .

[0069] The experimental results of TDC in code density testing are as follows: Figures 4A to 4C As shown.

[0070] One of the standards for measuring the performance of TDC is DNL and INL. The smaller the value, the better the linearity and the better the performance. Generally, the DNL and INL of a qualified TDC should be less than 1 LSB.

[0071] Figures 4A to 4C The code density test results of the TDC provided in this embodiment of the invention show that, without any calibration method, both its INL and DNL are below 0.6 LSB, demonstrating excellent performance.

[0072] It should be noted that embodiments of the present invention can be implemented in hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the above-described devices and methods can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a carrier medium such as a disk, CD, or DVD-ROM, a programmable memory such as read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuitry such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field-programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of the above-described hardware circuitry and software, such as firmware.

[0073] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A resource-saving short-chain structure time-to-digital conversion method, characterized in that, include: A local oscillator is built using a delay unit and a conversion circuit to flip the output state at fixed time intervals during the continuous high-level period of the input signal. The start time and the time of the last flip are obtained by recording the number of flips of the local oscillator. Resource-saving short-chain time-to-digital conversion methods also include: The input to the TDL TDC delay chain is the output waveform of the conversion circuit, and the measurement range Mτ satisfies the conditions Mτ>ΔT2-ΔT1 and the clock condition Mτ>T. clk +ΔT1-ΔT2; where M is the number of delay units in the delay chain, τ is the inherent delay of the delay unit, and T clk This is the system's "coarse" clock cycle; When a signal with a time interval of Δt is input, the starting time T s =ΔT i +M s *τ+N s *T clk End time T e =ΔT j +M e *τ+N e *T clk Where i and j represent the number of times the local oscillator output signal flips at the rising and falling edges of the input signal, and M... s and M e N represents the number of triggered units on the delay chain. s and N e If the integer value of the coefficient clock is represented, then Δt = T e -T s =(N e -N s )*T clk +(ΔT j -ΔT i )+(M e -M s )*τ.

2. The resource-saving short-chain structure time-to-digital conversion method as described in claim 1, characterized in that, The time it takes for the local oscillator to cause the level to flip is known.

3. The resource-saving short-chain structure time-to-digital conversion method as described in claim 1, characterized in that, Use TDLTDC to obtain the time of the last flip.

4. The resource-saving short-chain structure time-to-digital conversion method as described in claim 1, characterized in that, In actual implementation, the local oscillator generates more than two flips, the specific number of flips being determined based on clock conditions and the delay chain measurement range.

5. The resource-saving short-chain structure time-to-digital conversion method as described in claim 1, characterized in that, Resource-saving short-chain time-to-digital conversion methods also include: A local oscillator is formed by a first delay unit, a second delay unit, and a conversion circuit. The local oscillator is used in conjunction with TDL and TDC to measure the time interval of the signal under test. The delay units in the local oscillator are freely configurable by software and are IDELAY resources in the Xilinx FPGA. The delay units in the delay chain have fixed delays and are CARRY4 / 8 resources in the Xilinx FPGA.

6. A resource-saving short-chain time-to-digital converter applying the resource-saving short-chain time-to-digital conversion method as described in any one of claims 1 to 5, characterized in that, The resource-saving short-chain time-to-digital converter includes a first delay unit, a second delay unit, and a conversion circuit. The delay times of the first delay unit and the second delay unit are ΔT1 and ΔT2, respectively, and ΔT2>ΔT1. After passing through the first delay unit and the second delay unit, the signal is converted into two delayed signals and directly input into the conversion circuit to be converted into one signal.

7. A computer device, characterized in that, The computer device includes a memory and a processor. The memory stores a computer program, which, when executed by the processor, causes the processor to perform the steps of the resource-saving short-chain structure time-to-digital conversion method as described in any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the resource-saving short-chain structure time-to-digital conversion method as described in any one of claims 1 to 5.

9. An information data processing terminal, characterized in that, The information data processing terminal is used to implement the resource-saving short-chain structure time-to-digital converter as described in claim 6.

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