A reliability compact model establishment method of semiconductor device

Abstract

The application relates to a reliability compact model establishing method of a semiconductor device, which comprises the following steps: obtaining the degradation pre-test data of the key characteristics of the semiconductor device, establishing a corresponding compact model topology; extracting the parameters of the elements in the compact model topology before degradation, carrying out a reliability experiment, and obtaining the reliability test data after degradation of the key characteristics; characterizing the reliability test data after degradation according to the compact model topology and the parameters before degradation, and determining the sensitive parameters affecting the degradation characteristic characterization of the device; obtaining the degradation amount of the sensitive parameters relative to the degradation before the degradation, establishing a degradation model according to the change rule of the degradation amount with the reliability parameter; and correcting the sensitive parameters by using the degradation model to obtain the reliability compact model of the semiconductor device. The reliability model established by the method provides a basis for the degradation mechanism analysis of the device, is easy to be compatible with the circuit design software, and improves the design efficiency of the reliability integrated circuit.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics and integrated circuit analysis technology, specifically relating to a method for establishing a compact reliability model for semiconductor devices. Background Technology

[0002] As technology nodes continue to advance, device fabrication has gradually evolved from planar to three-dimensional processes, resulting in increasingly complex structures and the emergence of various complex device designs. As a crucial bridge between device fabrication and circuit design, the accuracy of the model directly determines the precision and efficiency of the circuit design, playing a vital role in the entire integrated circuit chip design process. Among these, compact models are simple and efficient models specifically developed for circuit simulation, typically characterized by simple iteration, good repeatability, and circuit design friendliness. By establishing reliability compact models for novel devices, we can delve into the internal physical mechanisms of the devices, laying the foundation for reliability degradation simulation and achieving better simulation speeds when simulating the electrical characteristics and reliability degradation effects of large-scale circuits.

[0003] However, existing device models often cannot accurately characterize the electrical characteristics of novel devices. Physics-based models have long development cycles, slow modeling speed, and are not easily compatible with circuit design software, which restricts the efficiency and accuracy of high-reliability integrated circuit design. In addition, existing reliability model research is still focused on the device physics level and cannot take into account complex influencing factors such as aging and irradiation for reliability analysis and design of large-scale integrated circuits. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a method for establishing a compact reliability model for semiconductor devices. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a method for establishing a compact reliability model for semiconductor devices, comprising:

[0006] Obtain pre-degradation test data of key characteristics of semiconductor devices, and establish corresponding compact model topologies based on the key characteristics;

[0007] Extract the parameters of the components in the compact model topology before degradation;

[0008] Based on the parameters before degradation, a reliability experiment was conducted to obtain the reliability test data after the key characteristics degraded.

[0009] Based on the compact model topology and the parameters before degradation, the reliability test data after degradation are characterized to determine the sensitive parameters that affect the characterization of device degradation characteristics.

[0010] Obtain the degradation amount of the sensitive parameter relative to the original value, and establish a degradation model based on the variation law of the degradation amount with the reliability parameter;

[0011] The degradation model is used to correct the sensitive parameters of the components in the compact model topology to obtain a reliability compact model for semiconductor devices.

[0012] By establishing an interface between the reliability compact model and the reliability parameters, the reliability compact model is embedded into the circuit design software, thereby realizing the establishment of the reliability compact model in the circuit design software.

[0013] In one embodiment of the present invention, the semiconductor device includes HEMT and HBT; the key characteristics of the semiconductor device include radio frequency small-signal characteristics, DC characteristics and noise characteristics, and the corresponding compact model topologies include small-signal model topology, large-signal model topology and noise model topology.

[0014] In one embodiment of the present invention, the reliability parameters include stress magnitude, stress time, and temperature.

[0015] In one embodiment of the present invention, a corresponding radio frequency small signal model topology is established for the radio frequency small signal characteristics of InP HBT, and the parameters of the components in the radio frequency small signal model topology before degradation are extracted, including: parasitic component parameters, external distributed capacitance component parameters and intrinsic component parameters.

[0016] The parasitic element parameters include: parasitic capacitance parameters, lead inductance parameters, and parasitic resistance parameters; the parasitic capacitance parameters include: base-collector parasitic capacitance C. pbc Base-emitter parasitic capacitance C pbe and collector-emitter parasitic capacitance C pce The lead inductance parameters include: collector lead inductance L c Emitter lead inductance L e and base lead inductance L b The parasitic resistance parameters include: collector parasitic resistance R. c Emitter parasitic resistance R e and base parasitic resistance R b ;

[0017] The parameters of the external distributed capacitance element include: base-collector external distributed capacitance C. bcx and the base-emitter external distributed capacitance C bex ;

[0018] The intrinsic element parameters include: intrinsic base resistance R. bi Intrinsic base-collector capacitance C bciIntrinsic base-emitter resistance R be and intrinsic base-emitter capacitance C bei .

[0019] In one embodiment of the present invention, extracting the parasitic element parameters includes the following steps:

[0020] Step 1: Extract the parasitic capacitance parameters and the lead inductance parameters respectively through open-short circuit pad structure testing;

[0021] Step 2: In the off state, obtain the impedance parameters for de-embedding the parasitic capacitance and the lead inductance, and extract the parasitic resistance parameters based on the impedance parameters, wherein,

[0022] R c =real(Z) ex,22 -Z ex,21 );

[0023] R e =real(Z) ex,12 );

[0024] R left =R b +R bi =real(Z) ex,11 -Z ex,12 );

[0025] Among them, Z ex The impedance parameters after removing parasitic capacitance and lead inductance; Z ex，11 The input impedance parameter for an open-circuit two-port network output; Z ex，12 The reverse transmission impedance parameter for an open-circuit two-port network input; Z ex，21 Forward transmission impedance parameters with the output of a two-port network open; Z ex，22 The output impedance parameter for a two-port network with its input open; real represents the real part; R left This represents the sum of the base terminal resistances in the cutoff state.

[0026] In one embodiment of the present invention, extracting the parameters of the external distributed capacitance element includes the following steps:

[0027] Step 1: Obtain the admittance parameters after removing parasitic elements, and extract the base-emitter external distributed capacitance C based on the admittance parameters. bex ,in,

[0028]

[0029] B = Y ex1,12 +Y ex1,22 ;

[0030] C = Y ex1,11 +Y ex1,21 ;

[0031] Among them, Y ex1 Y is the admittance parameter after removing parasitic elements; ex1，11 The input admittance parameter for short-circuiting the output of a two-port network; Y ex1，12 Y is the reverse transmission admittance parameter for a two-port network with its input short-circuited; ex1，21 Y is the forward transmission admittance parameter for a two-port network with the output short-circuited; ex1，22 is the output admittance parameter for a two-port network with the input shorted; B is the first formal parameter; C is the second formal parameter; imag indicates taking the imaginary part; real indicates taking the real part;

[0032] Step 2: Obtain the de-embedded base-emitter external distributed capacitance C bex The admittance parameter after the base-emitter external distributed capacitance is used to extract the base-collector external distributed capacitance C. bcx ,in,

[0033]

[0034] Y L =Y ex2,11 ·Y ex2,22 -Y ex2,12 ·Y ex2,21 ;

[0035] Y total =Y ex2,11 +Y ex2,12 +Y ex2,21 +Y ex2,22 ;

[0036] Y ms =Y ex2,12 +Y ex2,22 ;

[0037] Among them, Y ex2 Y is the admittance parameter after removing the external distributed capacitance of the base-emitter junction; ex2，11 The input admittance parameter for short-circuiting the output of a two-port network; Y ex2，12 Y is the reverse transmission admittance parameter for a two-port network with its input short-circuited; ex2，21 Y represents the forward transmission admittance parameter of a two-port network. ex2，22 Y is the output admittance parameter for a two-port network with its input shorted; L For Y ex2 The difference between the cross-product terms; Y total For Y ex2 The sum of consecutive additions; Y ms For Y ex2The sum of admittance parameters after removing parasitic capacitance and lead inductance from the two-port network output terminal and opening the circuit.

[0038] In one embodiment of the present invention, extracting the intrinsic element parameters includes the following steps:

[0039] Step 1: Obtain the intrinsic impedance parameters and intrinsic admittance parameters after removing parasitic elements and external distributed capacitance, respectively;

[0040] Step 2: Obtain the intrinsic base resistance R based on the intrinsic impedance parameter and the intrinsic admittance parameter. bi Intrinsic base-collector capacitance C bci Intrinsic base-emitter resistance R be and intrinsic base-emitter capacitance C bei ,in,

[0041] R bi =Z in,11 -Z in,12 ;

[0042]

[0043]

[0044]

[0045] Among them, Z in Z represents the intrinsic impedance parameter after removing parasitic elements and external distributed capacitance. in，11 The input impedance parameter for an open-circuit two-port network output of the intrinsic module; Z in，12 The reverse transmission impedance parameter is the one where the input of the intrinsic module's two-port network is open; Y in Y represents the intrinsic admittance parameter after removing parasitic elements and external distributed capacitance; in，11 The input admittance parameter for short-circuiting the output of the intrinsic module's two-port network; Y in，12 Y is the reverse transmission admittance parameter when the input of the intrinsic module's two-port network is short-circuited; in，21 Y is the positive transmission admittance parameter when the output of the intrinsic module's two-port network is short-circuited; in，22 The output admittance parameter is the one for short-circuiting the input of the intrinsic module's two-port network; imag indicates taking the imaginary part; real indicates taking the real part.

[0046] In one embodiment of the present invention, for the radio frequency small-signal model topology of InP HBT, the degradation amount of the sensitive parameter relative to the original degradation is obtained, and a degradation model is established based on the variation law of the degradation amount with the reliability parameter, including:

[0047] Using a double exponential function, the degradation amount of the sensitive parameter before degradation is analyzed, and a degradation model is established. The degradation model is as follows:

[0048] P aging (V CB,stress ,t)=ΔP(V CB,stress ,t)+P initial ;

[0049] ΔP(V CB,stress ,t)=A o (1-exp((exp(-μ·V CB,stress )-1)·at));

[0050] Among them, P aging The value of the sensitive parameter after degradation; ΔP is the amount of degradation of the sensitive parameter; P initial The sensitivity parameter value before degradation; V CB,stress A represents the magnitude of the high-field electric stress between the reverse base and collector; t represents the time of the high-field electric stress between the reverse base and collector; A o is the degradation saturation coefficient; a is the degradation acceleration coefficient; μ is the degradation acceleration exponential factor.

[0051] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0052] The present invention provides a method for establishing a compact reliability model for semiconductor devices. This method establishes a compact model topology based on critical pre-degradation test data, extracts the pre-degradation parameters of its components, and conducts reliability experiments. This determines the sensitive parameters affecting the degradation characterization of the device and their relative degradation amounts before degradation. A degradation model is then established based on these degradation amounts to correct the sensitive parameters, resulting in a compact reliability model for the semiconductor device. This method is simple and circuit design-friendly. The reliability model established using this method provides a basis for analyzing device degradation mechanisms and is easily compatible with circuit design software. It allows for simultaneous reliability assessments of devices and circuits, including aging and irradiation, without increasing design complexity or requiring additional computing power. This enables reliability-aware design and improves the design efficiency of reliability-critical integrated circuits.

[0053] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0054] Figure 1 This is a flowchart of a method for establishing a compact reliability model of a semiconductor device according to an embodiment of the present invention;

[0055] Figure 2 An equivalent circuit model topology for a reliability compact model provided in an embodiment of the present invention;

[0056] Figure 3 Simulation results of the parasitic resistance sensitive parameter degradation model of the reliability compact model provided in the embodiments of the present invention;

[0057] Figure 4 Simulation results of the external distributed capacitance sensitive parameter degradation model for the reliability compact model provided in the embodiments of the present invention;

[0058] Figure 5 Simulation results of the intrinsic capacitance sensitivity parameter degradation model for the reliability compact model provided in the embodiments of the present invention;

[0059] Figure 6 Simulation results of the intrinsic resistance sensitive parameter degradation model for the reliability compact model provided in the embodiments of the present invention;

[0060] Figure 7 Simulation results of the transconductance and delay time-sensitive parameter degradation model of the reliability compact model provided in the embodiments of the present invention;

[0061] Figure 8 A schematic diagram of the interface control and simulation principle diagram of the reliability compact model provided in the embodiments of the present invention in ADS;

[0062] Figure 9 A schematic diagram of the embedding of sensitive parameter elements in ADS in the reliability compact model provided in the embodiments of the present invention;

[0063] Figure 10 A comparison of simulation and test results of the small-signal characteristics of a reliability compact model provided in this embodiment of the invention before being subjected to high field electric stress in ADS, from 0.1 to 40 GHz.

[0064] Figure 11 A comparison of simulation and test results of the small-signal characteristics of a reliability compact model provided in this embodiment of the invention after being subjected to a 4.3V high-field electric stress for 100 minutes in ADS, and the characteristics of the small signal from 0.1 to 40 GHz.

[0065] Figure 12 A comparison of simulation and test results of the small-signal characteristics of a reliability compact model provided in this embodiment of the invention before being subjected to high field electric stress in ADS;

[0066] Figure 13 The simulation results and test results of a reliability compact model provided in this embodiment of the invention after being subjected to a 3.4V high field electric stress for 250 minutes in ADS are compared. Detailed Implementation

[0067] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail a method for establishing a reliability compact model of a semiconductor device according to the present invention, in conjunction with the accompanying drawings and specific embodiments.

[0068] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0069] Example 1

[0070] Please see Figure 1 , Figure 1 This is a flowchart of a method for establishing a compact reliability model of a semiconductor device according to an embodiment of the present invention;

[0071] As shown in the figure, this invention provides a method for establishing a compact reliability model for semiconductor devices, including:

[0072] S1: Obtain pre-degradation test data of key characteristics of semiconductor devices, and establish corresponding compact model topologies based on key characteristics;

[0073] S2: Extract the parameters of components in the compact model topology before degradation;

[0074] S3: Conduct reliability experiments based on the parameters before degradation to obtain reliability test data after the degradation of key characteristics;

[0075] S4: Based on the compact model topology and the parameters before degradation, characterize the reliability test data after degradation to determine the sensitive parameters that affect the characterization of device degradation characteristics;

[0076] S5: Obtain the degradation amount of the sensitive parameters relative to the original degradation, and establish a degradation model based on the variation law of degradation amount with reliability parameters;

[0077] S6: The sensitive parameters of the components in the compact model topology are corrected using the degradation model to obtain a compact reliability model for semiconductor devices.

[0078] S7: By establishing an interface between the reliability compact model and the reliability parameters, the reliability compact model is embedded into the circuit design software, thus realizing the establishment of the reliability compact model in the circuit design software.

[0079] In one alternative implementation, the semiconductor device includes HEMT and HBT; the key characteristics of the semiconductor device include radio frequency small-signal characteristics, DC characteristics and noise characteristics, and the corresponding compact model topologies include small-signal model topology, large-signal model topology and noise model topology.

[0080] In one alternative implementation, reliability parameters include stress magnitude, stress duration, and temperature.

[0081] Taking the RF small-signal characteristics of InP HBT as an example to establish the corresponding RF small-signal model topology, the reliability compact model establishment method of this embodiment will be specifically explained. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This invention provides an equivalent circuit model topology for a reliability compact model.

[0082] As shown in the figure, a corresponding RF small-signal model topology is established for the RF small-signal characteristics of InP HBT. The parameters of the components in the RF small-signal model topology before degradation are extracted, including: parasitic component parameters, external distributed capacitance component parameters, and intrinsic component parameters.

[0083] The parasitic element parameters include: parasitic capacitance parameters, lead inductance parameters, and parasitic resistance parameters; the parasitic capacitance parameters include: base-collector parasitic capacitance C. pbc Base-emitter parasitic capacitance C pbe and collector-emitter parasitic capacitance C pce Lead inductance parameters include: collector lead inductance L c Emitter lead inductance L e and base lead inductance L b Parasitic resistance parameters include: collector parasitic resistance R c Emitter parasitic resistance R e and base parasitic resistance R b ;

[0084] External distributed capacitance element parameters include: base-collector external distributed capacitance C bcx and the base-emitter external distributed capacitance C bex ;

[0085] Intrinsic component parameters include: intrinsic base resistance R. bi Intrinsic base-collector capacitance C bci Intrinsic base-emitter resistance R be and intrinsic base-emitter capacitance C bei .

[0086] In an optional implementation, extracting parasitic element parameters includes the following steps:

[0087] Step 1: Extract parasitic capacitance and lead inductance parameters respectively through open-short circuit pad structure testing;

[0088] Step 2: In the off state, obtain the impedance parameters of the de-embedded parasitic capacitance and lead inductance, and extract the parasitic resistance parameters based on the impedance parameters.

[0089] R c =real(Z) ex,22 -Z ex,21 (1)

[0090] R e =real(Z) ex,12 (2)

[0091] R left =R b +R bi =real(Z) ex,11 -Z ex,12 (3)

[0092] Among them, Z ex The impedance parameters after removing parasitic capacitance and lead inductance; Z ex，11 The input impedance parameter for an open-circuit two-port network output; Z ex，12 The reverse transmission impedance parameter for an open-circuit two-port network input; Z ex，21 Forward transmission impedance parameters with the output of a two-port network open; Z ex，22 The output impedance parameter for a two-port network with its input open; real represents the real part; R left This represents the sum of the base terminal resistances in the cutoff state.

[0093] In an optional implementation, extracting the parameters of the external distributed capacitance element includes the following steps:

[0094] Step 1: Obtain the admittance parameters after removing parasitic elements, and extract the base-emitter external distributed capacitance C based on the admittance parameters. bex ,in,

[0095]

[0096] B = Y ex1,12 +Y ex1,22 (5)

[0097] C = Y ex1,11 +Y ex1,21 (6)

[0098] Among them, Y ex1 Y is the admittance parameter after removing parasitic elements; ex1，11 The input admittance parameter for short-circuiting the output of a two-port network; Yex1，12 Y is the reverse transmission admittance parameter for a two-port network with its input short-circuited; ex1，21 Y is the forward transmission admittance parameter for a two-port network with the output short-circuited; ex1，22 is the output admittance parameter for a two-port network with the input shorted; B is the first formal parameter; C is the second formal parameter; imag indicates taking the imaginary part; real indicates taking the real part;

[0099] Step 2: Obtain the external distributed capacitance C of the base-emitter junction. bex The admittance parameter after the base-emitter external distributed capacitance is used to extract the base-collector external distributed capacitance C. bcx ,in,

[0100]

[0101] Y L =Y ex2,11 ·Y ex2,22 -Y ex2,12 ·Y ex2,21 (8)

[0102] Y total =Y ex2,11 +Y ex2,12 +Y ex2,21 +Y ex2,22 (9)

[0103] Y ms =Y ex2,12 +Y ex2,22 (10)

[0104] Among them, Y ex2 Y is the admittance parameter after removing the external distributed capacitance of the base-emitter junction; ex2，11 The input admittance parameter for short-circuiting the output of a two-port network; Y ex2，12 Y is the reverse transmission admittance parameter for a two-port network with its input short-circuited; ex2，21 Y represents the forward transmission admittance parameter of a two-port network. ex2，22 Y is the output admittance parameter for a two-port network with its input shorted; L For Y ex2 The difference between the cross-product terms; Y total For Y ex2 The sum of consecutive additions; Y ms For Y ex2 The sum of admittance parameters after removing parasitic capacitance and lead inductance from the two-port network output terminal and opening the circuit.

[0105] In an optional implementation, extracting intrinsic element parameters includes the following steps:

[0106] Step 1: Obtain the intrinsic impedance parameters and intrinsic admittance parameters after removing parasitic elements and external distributed capacitance, respectively;

[0107] Step 2: Obtain the intrinsic base resistance R based on the intrinsic impedance and intrinsic admittance parameters. bi Intrinsic base-collector capacitance C bci Intrinsic base-emitter resistance R be and intrinsic base-emitter capacitance C bei ,in,

[0108] R bi =Z in,11 -Z in,12 (11)

[0109]

[0110]

[0111]

[0112] Among them, Z in Z represents the intrinsic impedance parameter after removing parasitic elements and external distributed capacitance. in，11 The input impedance parameter for an open-circuit two-port network output of the intrinsic module; Z in，12 The reverse transmission impedance parameter is the one where the input of the intrinsic module's two-port network is open; Y in Y represents the intrinsic admittance parameter after removing parasitic elements and external distributed capacitance; in，11 The input admittance parameter for short-circuiting the output of the intrinsic module's two-port network; Y in，12 Y is the reverse transmission admittance parameter when the input of the intrinsic module's two-port network is short-circuited; in，21 Y is the positive transmission admittance parameter when the output of the intrinsic module's two-port network is short-circuited; in，22 The output admittance parameter is the one for short-circuiting the input of the intrinsic module's two-port network; imag indicates taking the imaginary part; real indicates taking the real part.

[0113] In an optional implementation, the intrinsic element parameters further include: DC gain transconductance g. m0 The delay time τ is extracted using the following formula:

[0114] g m0 =mag(Y in,21 -Y in,12 (15)

[0115]

[0116] Where imag represents the imaginary part; real represents the real part; and mag represents the amplitude.

[0117] In one alternative implementation, the parameters of the components in the compact model topology before degradation are shown in Table 1.

[0118]

[0119]

[0120] Table 1. Extracted parameter values ​​of topological elements in the InP HBT small-signal model before degradation.

[0121] In an optional implementation, for the RF small-signal model topology of the InP HBT, the degradation amount of the sensitive parameters relative to the original degradation is obtained, and a degradation model is established based on the variation law of the degradation amount with the reliability parameters, including:

[0122] Using a double exponential function, the degradation of the sensitive parameter before degradation is analyzed, and a degradation model is established. The degradation model is as follows:

[0123] P aging (V CB,stress ,t)=ΔP(V CB,stress ,t)+P initial (17)

[0124] ΔP(V CB,stress ,t)=A o (1-exp((exp(-μ·V CB,stress) -1)·at)); (18)

[0125] Among them, P aging The value of the sensitive parameter after degradation; ΔP is the amount of degradation of the sensitive parameter; P initial The sensitivity parameter value before degradation; V CB,stress A represents the magnitude of the high-field electric stress between the reverse base and collector; t represents the time of the high-field electric stress between the reverse base and collector; A o is the degradation saturation coefficient; a is the degradation acceleration coefficient; μ is the degradation acceleration exponential factor.

[0126] A o a and μ have different values ​​for different sensitive parameter values. In this embodiment, the values ​​are shown in Table 2.

[0127]

[0128] Table 2. Sensitive parameters of the InP HBT small-signal model and parameter extraction values ​​of the degradation model.

[0129] As can be seen from the above formula and Table 2, the difference between the degraded sensitive parameter value and the original sensitive parameter value is the amount of degradation of the sensitive parameter value. After applying high field electric stress, the amount of degradation of the sensitive parameter is a function of the reliability parameter (magnitude of high field electric stress and time). As the value of the reliability parameter changes, the amount of degradation of the sensitive parameter changes accordingly.

[0130] Please refer to the above. Figures 3-7 , Figure 3 Simulation results of the parasitic resistance sensitive parameter degradation model of the reliability compact model provided in the embodiments of the present invention; Figure 4 Simulation results of the external distributed capacitance sensitive parameter degradation model for the reliability compact model provided in the embodiments of the present invention; Figure 5 Simulation results of the intrinsic capacitance sensitivity parameter degradation model for the reliability compact model provided in the embodiments of the present invention; Figure 6 Simulation results of the intrinsic resistance sensitive parameter degradation model for the reliability compact model provided in the embodiments of the present invention; Figure 7 The simulation results are for the transconductance and delay time-sensitive parameter degradation model of the reliability compact model provided in the embodiments of the present invention.

[0131] The simulation results of the parameter extraction values ​​of the sensitive parameter degradation model of the component in the InP HBT small signal model are shown in the figure. As can be seen from the figure, the established model can reflect the degradation trend of the sensitive parameter well.

[0132] In this embodiment, the modified reliability compact model is embedded into the circuit design software. By establishing an interface between the established reliability model and the corresponding reliability parameters, the degradation of the key characteristics of the device is simulated and predicted, thereby reflecting the impact of device-level degradation on the overall circuit performance during the integrated circuit design process.

[0133] Please refer to the above. Figure 8 and Figure 9 , Figure 8 A schematic diagram of the interface control and simulation principle diagram of the reliability compact model provided in the embodiments of the present invention in ADS; Figure 9 This is a schematic diagram of the embedding of sensitive parameter elements in ADS in the reliability compact model provided in the embodiments of the present invention.

[0134] As shown in the figure, this control can be used to adjust the reliability parameter V in the figure. CB,stress The values ​​were modified to align with the established reliability compact model. Using the component library provided by ADS software, capacitors, resistors, and controlled sources in the RF small-signal model topology were connected using link lines. Then, the degradation function was written into these components. Finally, the created simulation project was used to simulate and predict the degradation of the RF small-signal scattering parameter characteristics of the InP HBT.

[0135] Please refer to the following: Figure 10 , Figure 11 , Figure 12 and Figure 13 , Figure 10 A comparison of simulation and test results of the small-signal characteristics of a reliability compact model provided in this embodiment of the invention before being subjected to high field electric stress in ADS, from 0.1 to 40 GHz. Figure 11 A comparison of simulation and test results of the small-signal characteristics of a reliability compact model provided in this embodiment of the invention after being subjected to a 4.3V high-field electric stress for 100 minutes in ADS, and the characteristics of the small signal from 0.1 to 40 GHz. Figure 12 A comparison of simulation and test results of the small-signal characteristics of a reliability compact model provided in this embodiment of the invention before being subjected to high field electric stress in ADS; Figure 13 The simulation results and test results of a reliability compact model provided in this embodiment of the invention after being subjected to a 3.4V high field electric stress for 250 minutes in ADS are compared.

[0136] As shown in the figure, different batches of InP HBT devices have different bias points at V. ce =1.6V; I b =200μA; Under different high-field electric stress magnitudes and stress durations, comparing the results of manual measurement of small-signal characteristics using instruments and the results of simulation using a reliability compact model established by the reliability compact model establishment method, it can be seen that the measurement results and test results have a high degree of agreement in terms of variation trend and have good fitting accuracy. That is, the establishment of a reliability compact model can meet the needs of reliability testing.

[0137] The method for establishing a compact reliability model for semiconductor devices according to embodiments of the present invention establishes a compact model topology based on critical pre-degradation test data, extracts the pre-degradation parameters of the components, and conducts reliability experiments to determine the sensitive parameters affecting the degradation characterization of the device and their relative degradation amount before degradation. Then, a degradation model is established based on the degradation amount, and the sensitive parameters are corrected to obtain a compact reliability model for the semiconductor device. This method is simple in process and friendly to circuit design. The reliability model established by this method provides a basis for the analysis of device degradation mechanisms and is easily compatible with circuit design software. It allows for simultaneous reliability assessments of devices and circuits, such as aging and irradiation, without increasing the complexity of the design process or requiring additional computing power. This achieves circuit reliability-aware design and improves the design efficiency of reliability integrated circuits.

[0138] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0139] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for establishing a compact reliability model for semiconductor devices, characterized in that, include: Obtain pre-degradation test data of key characteristics of semiconductor devices, and establish corresponding compact model topologies based on the key characteristics; Extract the parameters of the components in the compact model topology before degradation; Based on the parameters before degradation, a reliability experiment was conducted to obtain the reliability test data after the key characteristics degraded. Based on the compact model topology and the parameters before degradation, the reliability test data after degradation are characterized to determine the sensitive parameters that affect the characterization of device degradation characteristics. Obtain the degradation amount of the sensitive parameter relative to the original degradation, and establish a degradation model based on the variation law of the degradation amount with the reliability parameter; The degradation model is used to correct the sensitive parameters of the components in the compact model topology to obtain a reliability compact model for semiconductor devices. By establishing an interface between the reliability compact model and the reliability parameters, the reliability compact model is embedded into the circuit design software, thereby realizing the establishment of the reliability compact model in the circuit design software.

2. The method for establishing a compact reliability model for semiconductor devices according to claim 1, characterized in that, The semiconductor devices include HEMT and HBT; the key characteristics of the semiconductor devices include radio frequency small-signal characteristics, DC characteristics and noise characteristics, and their corresponding compact model topologies include small-signal model topology, large-signal model topology and noise model topology.

3. The method for establishing a compact reliability model for semiconductor devices according to claim 1, characterized in that, The reliability parameters include stress magnitude, stress time, and temperature.

4. The method for establishing a compact reliability model for semiconductor devices according to claim 2, characterized in that, For the RF small-signal characteristics of InP HBT, a corresponding RF small-signal model topology is established, and the parameters of the components in the RF small-signal model topology before degradation are extracted, including: parasitic component parameters, external distributed capacitance component parameters, and intrinsic component parameters. The parasitic element parameters include: parasitic capacitance parameters, lead inductance parameters, and parasitic resistance parameters; the parasitic capacitance parameters include: base-collector parasitic capacitance C. pbc Base-emitter parasitic capacitance C pbe and collector-emitter parasitic capacitance C pce The lead inductance parameters include: collector lead inductance L c Emitter lead inductance L e and base lead inductance L b The parasitic resistance parameters include: collector parasitic resistance R. c Emitter parasitic resistance R e and base parasitic resistance R b ; The parameters of the external distributed capacitance element include: base-collector external distributed capacitance C. bcx and the base-emitter external distributed capacitance C bex ; The intrinsic element parameters include: intrinsic base resistance R. bi Intrinsic base-collector capacitance C bci Intrinsic base-emitter resistance R be and intrinsic base-emitter capacitance C bei .

5. The method for establishing a compact reliability model for semiconductor devices according to claim 4, characterized in that, Extracting the parasitic element parameters includes the following steps: Step 1: Extract the parasitic capacitance parameters and the lead inductance parameters respectively through open-short circuit pad structure testing; Step 2: In the off state, obtain the impedance parameters for de-embedding the parasitic capacitance and the lead inductance, and extract the parasitic resistance parameters based on the impedance parameters, wherein, R c =real(Z ex,22 -Z ex,21 ); R e =real(Z ex,12 ); R left =R b +R bi =real(Z ex,11 -Z ex,12 ); Among them, Z ex The impedance parameters after removing parasitic capacitance and lead inductance; Z ex，11 The input impedance parameter for an open-circuit two-port network output; Z ex，12 The reverse transmission impedance parameter for an open-circuit two-port network input; Z ex，21 Forward transmission impedance parameters with the output of a two-port network open; Z ex，22 The output impedance parameter for a two-port network with its input open; real represents the real part; R left This represents the sum of the base terminal resistances in the cutoff state.

6. The method for establishing a compact reliability model for semiconductor devices according to claim 4, characterized in that, Extracting the parameters of the external distributed capacitance element includes the following steps: Step 1: Obtain the admittance parameters after removing parasitic elements, and extract the base-emitter external distributed capacitance C based on the admittance parameters. bex ,in, B=Y ex1,12 +And ex1,22 ; C / Y ex1,11 +And ex1,21 ; Among them, Y ex1 Y is the admittance parameter after removing parasitic elements; ex1，11 The input admittance parameter for short-circuiting the output of a two-port network; Y ex1，12 Y is the reverse transmission admittance parameter for a two-port network with its input short-circuited; ex1，21 Y is the forward transmission admittance parameter for a two-port network with the output short-circuited; ex1，22 is the output admittance parameter for a two-port network with the input shorted; B is the first formal parameter; C is the second formal parameter; imag indicates taking the imaginary part; real indicates taking the real part; Step 2: Obtain the de-embedded base-emitter external distributed capacitance C bex The admittance parameter after the base-emitter external distributed capacitance is used to extract the base-collector external distributed capacitance C. bcx ,in, AND L =Y ex2,11 ·AND ex2,22 -AND ex2,12 ·AND ex2,21 ; AND total =Y ex2,11 +And ex2,12 +And ex2,21 +And ex2,22 ; AND ms =Y ex2,12 +And ex2,22 ; Among them, Y ex2 Y is the admittance parameter after removing the external distributed capacitance of the base-emitter junction; ex2，11 The input admittance parameter for short-circuiting the output of a two-port network; Y ex2，12 Y is the reverse transmission admittance parameter for a two-port network with its input short-circuited; ex2，21 Y represents the forward transmission admittance parameter of a two-port network. ex2，22 Y is the output admittance parameter for a two-port network with its input shorted; L For Y ex2 The difference between the cross-product terms; Y total For Y ex2 The sum of consecutive additions; Y ms For Y ex2 The sum of admittance parameters after removing parasitic capacitance and lead inductance from the two-port network output terminal and opening the circuit.

7. The method for establishing a compact reliability model for semiconductor devices according to claim 4, characterized in that, Extracting the intrinsic element parameters includes the following steps: Step 1: Obtain the intrinsic impedance parameters and intrinsic admittance parameters after removing parasitic elements and external distributed capacitance, respectively; Step 2: Obtain the intrinsic base resistance R based on the intrinsic impedance parameter and the intrinsic admittance parameter. bi Intrinsic base-collector capacitance C bci Intrinsic base-emitter resistance R be and intrinsic base-emitter capacitance C bei ,in, R bi =Z in,11 -Z in,12 ; Among them, Z in Z represents the intrinsic impedance parameter after removing parasitic elements and external distributed capacitance. in，11 The input impedance parameter for an open-circuit two-port network output of the intrinsic module; Z in，12 The reverse transmission impedance parameter is the one where the input of the intrinsic module's two-port network is open; Y in Y represents the intrinsic admittance parameter after removing parasitic elements and external distributed capacitance; in，11 The input admittance parameter for short-circuiting the output of the intrinsic module's two-port network; Y in，12 Y is the reverse transmission admittance parameter when the input of the intrinsic module's two-port network is short-circuited; in，21 Y is the positive transmission admittance parameter when the output of the intrinsic module's two-port network is short-circuited; in，22 The output admittance parameter is the one for short-circuiting the input of the intrinsic module's two-port network; imag indicates taking the imaginary part; real indicates taking the real part.

8. The method for establishing a compact reliability model for semiconductor devices according to claim 4, characterized in that, For the RF small-signal model topology of InP HBT, the degradation amount of the sensitive parameters relative to the original degradation is obtained, and a degradation model is established based on the variation law of the degradation amount with the reliability parameters, including: Using a double exponential function, the degradation amount of the sensitive parameter before degradation is analyzed, and a degradation model is established. The degradation model is as follows: P aging (V CB,stress ,t)=ΔP(V CB,stress ,t)+P initial ; ΔP(V CB,stress ,t)=A o (1-exp((exp(-μ·V CB,stress )-1)·at)); Among them, P aging The value of the sensitive parameter after degradation; ΔP is the amount of degradation of the sensitive parameter; P initial The sensitivity parameter value before degradation; V CB,stress A represents the magnitude of the high-field electric stress between the reverse base and collector; t represents the time of the high-field electric stress between the reverse base and collector; A o is the degradation saturation coefficient; a is the degradation acceleration coefficient; μ is the degradation acceleration exponential factor.

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