storage device

Abstract

The present disclosure provides a storage device, comprising: at least one first storage area, at least one driving module and at least one amplification module; wherein two sides of each first storage area in the word line direction are arranged with driving modules, and two sides of each first storage area in the bit line direction are arranged with amplification modules; each first storage area contains at least one mixed storage block arranged side by side in the word line direction, and the mixed storage block is used for storing data and on-chip check codes. The mixed storage block for storing mixed data and on-chip check codes is arranged in the first storage area, and a storage area for the on-chip check codes is not needed separately, the number of storage areas is reduced, and thus the number of driving modules can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory device. Background Technology

[0002] As market demands for higher performance in semiconductor memory devices increase, the size of these devices is becoming increasingly smaller. To adapt to this trend, further optimization of the memory device structure is necessary. Summary of the Invention

[0003] This disclosure provides a storage device, including: at least one first storage area, at least one driving module, and at least one amplification module;

[0004] In this configuration, driving modules are arranged on both sides of the word line direction of each first storage region, and amplification modules are arranged on both sides of the bit line direction of each first storage region.

[0005] Each first storage region contains at least one hybrid storage block arranged side-by-side in the word line direction, the hybrid storage block being used to store data and on-chip checksums.

[0006] In one embodiment, the storage device includes a second storage area;

[0007] Among them, driving modules are arranged on both sides of the word line direction of the second storage area, and amplification modules are arranged on both sides of the bit line direction of the second storage area.

[0008] The second storage area has a system check code sub-area, which includes at least one system check code storage block arranged side by side in the word line direction. The system check code storage block is used to store the system check code.

[0009] In one embodiment, at least one first storage region is arranged side by side in the word line direction, and a second storage region is located between the two first storage regions;

[0010] Furthermore, only one driver module is arranged between any two adjacent first storage areas, and only one driver module is arranged between adjacent second storage areas and first storage areas.

[0011] In one embodiment, the second storage region further includes a first redundant sub-region and a second redundant sub-region;

[0012] The first redundant sub-region includes at least one first redundant memory block arranged side-by-side on the word line, and the second redundant sub-region includes at least one second redundant memory block arranged side-by-side on the word line.

[0013] The first redundant storage block is used to store the system checksum, and the second redundant storage block is used to store the data and the on-chip checksum.

[0014] In one embodiment, the second storage area further includes three first virtual storage blocks;

[0015] The system check code area is located between the two first virtual storage blocks, and the continuously arranged first and second redundant sub-regions are located between the two first virtual storage blocks.

[0016] In one embodiment, the first storage region further includes two second virtual storage blocks; wherein at least one contiguously arranged hybrid storage block is located between the two second virtual storage blocks.

[0017] In one embodiment, the hybrid memory block includes: a plurality of first memory structures arranged side-by-side in the word line direction;

[0018] Each first storage structure includes a first substructure and a second substructure arranged side-by-side in the word line direction; the first substructure is used to store data and on-chip check codes; the second substructure is used to store data and on-chip check codes.

[0019] In one embodiment, the first substructure includes a plurality of memory cells, nine consecutively arranged bit lines, and a plurality of consecutively arranged word lines; each memory cell includes a transistor and a capacitor, the source of the transistor being connected to the capacitor; each bit line is connected to the drain of a transistor arranged in the bit line direction; each word line is connected to the gate of a transistor arranged in the word line direction.

[0020] In this configuration, the word line direction and the bit line direction are perpendicular to each other, and the nine bit lines are controlled by the same column select line. The bit line located at the edge of the nine consecutively arranged bit lines is called the first check bit line, and each of the remaining eight consecutively arranged bit lines is called the first data bit line. The memory cell connected to the first data bit line is used to store data, and the memory cell connected to the first check bit line is used to store on-chip check codes.

[0021] In one embodiment, the second substructure includes a plurality of memory cells, nine consecutively arranged bit lines and a plurality of consecutively arranged word lines; each bit line is connected to the drain of a transistor arranged in the bit line direction; each word line is connected to the gate of a transistor arranged in the word line direction.

[0022] In this configuration, the word line direction and the bit line direction are perpendicular to each other, and the nine bit lines are controlled by the same column select line. The bit line located at the edge of the nine consecutively arranged bit lines is called the second check bit line, and each of the remaining eight consecutively arranged bit lines is called the second data bit line. The memory cell connected to the second data bit line is used to store data, and the memory cell connected to the second check bit line is used to store on-chip check codes. The first check bit line and the second check bit line are arranged adjacent to each other.

[0023] In one embodiment, the amplification module includes a plurality of sensitive amplifiers;

[0024] The first check code bit line in the first substructure is connected to the first sensitive amplifier; the second check code bit line in the second substructure is connected to the second sensitive amplifier.

[0025] The first and second sensitive amplifiers are arranged on different sides of the first substructure in the bit line direction.

[0026] In one embodiment, the sensitive amplifiers connected to any two adjacent bit lines in the first substructure are labeled as the third sensitive amplifier and the fourth sensitive amplifier; the third sensitive amplifier and the fourth sensitive amplifier are arranged on different sides of the first substructure in the bit line direction;

[0027] The sensitive amplifiers connected to any two adjacent bit lines in the second substructure are designated as the fifth sensitive amplifier and the sixth sensitive amplifier; the fifth and sixth sensitive amplifiers are arranged on different sides of the second substructure in the bit line direction.

[0028] In one embodiment, the system checksum storage block includes multiple second storage structures arranged side by side;

[0029] The second memory structure includes multiple memory cells, eight consecutive bit lines, and multiple consecutive word lines. Each memory cell includes a transistor and a capacitor, with the source of the transistor connected to the capacitor. Each of the eight consecutive bit lines is called a third data bit line.

[0030] Each third data bit line is connected to the drain of a transistor arranged in the bit line direction; each word line is connected to the gate of a transistor arranged in the word line direction; the word line direction and the bit line direction are perpendicular to each other, and the eight bit lines are controlled by the same column select line; the memory cells connected to the eight third data bit lines are used to store the system check code.

[0031] In one embodiment, the structure of the second redundant storage block is the same as that of the hybrid storage block.

[0032] In one embodiment, the first redundant storage block includes a plurality of third storage structures arranged side by side on word lines; the structure of the third storage structures is the same as that of the second storage structures.

[0033] In one embodiment, each first virtual memory block includes multiple fourth memory structures arranged side-by-side on word lines, and each second virtual memory block includes multiple fifth memory structures arranged side-by-side on word lines; the structure of the fourth memory structure is the same as the structure of the second memory structure, and the structure of the fifth memory structure is the same as the structure of the second memory structure.

[0034] This disclosure provides a storage device in which a hybrid storage block for storing data and on-chip checksums is provided in a first storage area, eliminating the need for a separate storage area for on-chip checksums, reducing the number of storage areas, thereby reducing the number of driver modules. Furthermore, using a second storage area to store system checksums can further reduce the number of storage areas, thereby further reducing the number of driver modules and reducing the layout area of ​​the storage device. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0036] Figure 1 This is a schematic diagram of the structure of a storage device provided in an embodiment of the present disclosure;

[0037] Figure 2 For this disclosure Figure 1 A schematic diagram of the data storage area in the storage device provided in the illustrated embodiment;

[0038] Figure 3 A schematic diagram of the structure of a storage device provided in another embodiment of this disclosure;

[0039] Figure 4 For this disclosure Figure 3 A schematic diagram of the structure of the first storage area in the storage device provided in the embodiment shown;

[0040] Figure 5 For this disclosure Figure 3 A schematic diagram of the structure of the first substructure in the storage device provided in the embodiment shown;

[0041] Figure 6 For this disclosure Figure 3 A schematic diagram of the structure of the second substructure in the storage device provided in the illustrated embodiment;

[0042] Figure 7 For this disclosure Figure 3 A schematic diagram of the structure of the second storage area in the storage device provided in the embodiment shown;

[0043] Figure 8 For this disclosure Figure 7 A schematic diagram of the second storage structure in the storage device provided in the illustrated embodiment.

[0044] Figure label:

[0045] 101 - First storage structure; 102 - First substructure; 103 - Second substructure;

[0046] 110—First storage area; 111—Hybrid storage block; 112—Second virtual storage block;

[0047] 120—Driver module; 130—Amplification module; 140—Second storage area;

[0048] 141—Check code storage block; 142—First redundancy storage block;

[0049] 143—Second redundant storage block; 144—First virtual storage block; 151—Storage cell;

[0050] 152—First check bit line; 153—First data bit line; 154—Second check bit line;

[0051] 155—Second data bit line; 156—First sensitive amplifier; 157—Second sensitive amplifier;

[0052] 158—Third sensitive amplifier; 159—Fourth sensitive amplifier; 160—Word line;

[0053] 161—Fifth Sensitive Amplifier; 162—Sixth Sensitive Amplifier;

[0054] 165—Third data bit line; 166—Seventh sensitive amplifier;

[0055] 167—Eighth sensitive amplifier; 202—Second memory structure;

[0056] 203—Sixth storage structure; 204—Third substructure; 205—Fourth substructure;

[0057] 401—System checksum sub-region; 402—First redundancy sub-region; 403—Second redundancy sub-region;

[0058] 501—First storage submodule; 510—First data storage area; 511—First storage block;

[0059] 520—First hybrid storage area; 521—First storage sub-area; 522—Second storage sub-area;

[0060] 523—Second storage block; 524—Third storage block; 530—Second hybrid storage area;

[0061] 531—Third storage sub-region; 532—Fourth storage sub-region; 533—Fourth storage block;

[0062] 534—Fifth storage block; 540—Third hybrid storage area; 541—Fifth storage sub-area;

[0063] 542—Sixth storage sub-region; 543—Sixth storage block; 544—Seventh storage block;

[0064] 550—Fourth Hybrid Storage Area; 551—Seventh Storage Sub-area; 552—Eighth Storage Sub-area;

[0065] 553—Eighth memory block; 554—Ninth memory block; 560—Amplification unit;

[0066] 570—Drive unit.

[0067] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0068] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0069] like Figure 1 As shown, one embodiment of this disclosure provides a storage device including at least one data storage area 510, at least one first hybrid storage area 520, at least one second hybrid storage area 530, at least one third hybrid storage area 540, and at least one fourth hybrid storage area 550. The data storage area 510 is used to store data, the first hybrid storage area 520 is used to store data and an on-die error correcting code (OD-ECC), the second hybrid storage area 530 is used to store data and an OD-ECC, the third hybrid storage area 540 is used to store data and a system error correcting code, and the fourth hybrid storage area 550 is used to store data and a system error correcting code.

[0070] The storage device also includes multiple drive units 570 and multiple amplification units 560. The word line direction refers to the direction in which word lines extend, and the bit line direction refers to the direction in which bit lines extend. The word line direction and the bit line direction are perpendicular to each other. Each data storage region 510 has a drive unit 570 on both sides of the word line direction, and each storage region has an amplification unit 560 on both sides of the bit line direction. Each storage region refers to any one of the data storage region 510, the first hybrid storage region 520, the second hybrid storage region 530, the third hybrid storage region 540, and the fourth hybrid storage region 550.

[0071] In one embodiment, the data storage area 510, the first hybrid storage area 520, the second hybrid storage area 530, the third hybrid storage area 540, and the fourth hybrid storage area 550 are arranged continuously in the word line direction, and only one drive unit 570 is provided between any two adjacent storage areas. The storage area in any two adjacent storage areas refers to one or two of the data storage area 510, the first hybrid storage area 520, the second hybrid storage area 530, the third hybrid storage area 540, and the fourth hybrid storage area 550.

[0072] In one embodiment, reference Figure 1 The storage device includes six consecutively arranged data storage areas 510, one first hybrid storage area 520, one second hybrid storage area 530, one third hybrid storage area 540, one fourth hybrid storage area 550, and 11 drive units. The arrangement order in the word line direction is as follows: two data storage areas 510, one first hybrid storage area 520, one data storage area 510, one third hybrid storage area 540, one fourth hybrid storage area 550, one data storage area 510, one second hybrid storage area 530, and two data storage areas 510. Only one drive unit 570 is provided between any two adjacent storage areas, and one drive unit 570 is also arranged on the side of the data storage areas 510 located at both ends that is furthest from the other data storage areas 510.

[0073] refer to Figure 2 Each data storage area 510 includes multiple first storage blocks 511, and each first storage block 511 includes multiple first storage sub-modules 501. The structures of each first storage sub-module 501 are the same. The structure of one of the first storage sub-modules 501 is described as an example.

[0074] The first storage submodule 501 includes eight consecutively arranged bit lines, multiple consecutively arranged word lines, and multiple storage cells. The eight bit lines are controlled by the same column select line, and each storage cell is used to store data.

[0075] Each memory cell includes a transistor and a capacitor. The source of the transistor is connected to one end of the capacitor, and the other end of the capacitor is connected to a power supply. Multiple memory cells are arranged in an array, as are the transistors and capacitors within each memory cell. Each bit line in the first memory submodule 501 is connected to the drain of a transistor arranged in the bit line direction, and each word line in the first memory submodule 501 is connected to the gate of a transistor arranged in the word line direction.

[0076] Continue to refer to Figure 1 The first hybrid storage region 520 includes a first storage sub-region 521 and a second storage sub-region 522. The first storage sub-region 521 includes multiple second storage blocks 523, each second storage block 523 including multiple second storage sub-modules, each second storage sub-module being used to store on-chip checksums. The second storage sub-region 522 includes multiple third storage blocks 524, each third storage block 524 including multiple third storage sub-modules, each third storage sub-module being used to store data. The structure of the second storage sub-modules is the same as the structure of the first storage sub-modules, and the structure of the third storage sub-modules is the same as the structure of the first storage sub-modules.

[0077] The second hybrid storage region 530 includes a third storage sub-region 531 and a fourth storage sub-region 532. The third storage sub-region 531 includes multiple fourth storage blocks 533, each fourth storage block 533 including multiple fourth storage sub-modules, each fourth storage sub-module being used to store on-chip checksums. The fourth storage sub-region 532 includes multiple fifth storage blocks 534, each fifth storage block 534 including multiple fifth storage sub-modules, each fifth storage sub-module being used to store data. The structure of the fourth storage sub-modules is the same as the structure of the first storage sub-modules, and the structure of the fifth storage sub-modules is the same as the structure of the first storage sub-modules.

[0078] The third hybrid storage region 540 includes a fifth storage sub-region 541 and a sixth storage sub-region 542. The fifth storage sub-region 541 includes multiple sixth storage blocks 543, each sixth storage block 543 including multiple sixth storage sub-modules, each sixth storage sub-module being used to store data. The sixth storage sub-region 542 includes seventh storage blocks 544, each seventh storage block 544 including multiple seventh storage sub-modules, each seventh storage sub-module being used to store system checksums. The structure of the sixth storage sub-module is the same as that of the first storage sub-module, and the structure of the seventh storage sub-module is the same as that of the first storage sub-module.

[0079] The fourth hybrid storage region 550 includes a seventh storage sub-region 551 and an eighth storage sub-region 552. The seventh storage sub-region 551 includes multiple eighth storage blocks 553, each eighth storage block 553 including multiple eighth storage sub-modules, each eighth storage sub-module being used to store data. The eighth storage sub-region 552 includes a ninth storage block 554, each ninth storage block 554 including multiple ninth storage sub-modules, each ninth storage sub-module being used to store system checksums. The structure of the eighth storage sub-modules is the same as that of the first storage sub-modules, and the structure of the ninth storage sub-modules is the same as that of the first storage sub-modules.

[0080] exist Figure 1 The storage device shown includes a data storage area for storing data, a first storage sub-area 521 and a third storage sub-area 531 for storing on-chip checksums, and a sixth storage sub-area 542 and an eighth storage sub-area 552 for storing system checksums. That is, both on-chip checksums and system checksums use separate storage sub-areas, increasing the storage area in the storage device. Each storage area requires a drive unit 570 on both sides in the word line direction, further increasing the number of drive units 570, thus making the layout area of ​​the storage device larger.

[0081] In one embodiment, redundant storage blocks are provided in the data storage area 510, the first hybrid storage area 520, the second hybrid storage area 530, the third hybrid storage area 540, and the fourth hybrid storage area 550, which are used as backup storage blocks when other storage blocks in each storage area fail. By setting it up in this way, the length of the word line or bit line is increased, which makes the parasitic capacitance and / or parasitic resistance on the word line or bit line larger, thus prolonging the data storage response time of the storage cell.

[0082] In view of the above problems, another embodiment of this disclosure provides a storage device with a smaller layout area and a shorter data storage response time.

[0083] like Figure 3 As shown, another embodiment of this disclosure provides a storage device, which includes at least one first storage area 110, a second storage area 140, at least one drive module 120, and at least one amplification module 130.

[0084] Each first storage region 110 has a driver module 120 arranged on both sides in the word line direction and an amplifier module 130 arranged on both sides in the bit line direction. The second storage region 140 has a driver module 120 arranged on both sides in the word line direction and an amplifier module 130 arranged on both sides in the bit line direction.

[0085] In this arrangement, at least one first storage region 110 is arranged sequentially in the word line direction, and a second storage region 140 is located between two first storage regions 110. With this arrangement, only one drive module 120 is arranged between any two adjacent first storage regions 110, which ensures that a drive module 120 is arranged on both sides of the first storage region 110 in the middle. Similarly, only one drive module 120 is arranged between the adjacent second storage regions 140 and the first storage regions 110, which ensures that a drive module 120 is arranged on both sides of the second storage region 140. This reduces the number of drive modules 20 and the layout area of ​​the storage device.

[0086] In one embodiment, the storage device is symmetrically arranged about the second storage region 140. This arrangement is beneficial for manufacturing the storage device and improves the yield of the storage device.

[0087] Each first storage region 110 includes at least one hybrid storage block 111 arranged side-by-side in the word line direction, the hybrid storage block 111 being used to store data and on-chip parity codes. A second storage region 140 is provided with a system parity code sub-region 401, the system parity code sub-region 401 including at least one system parity code storage block 141 arranged side-by-side in the word line direction, the system parity code storage block 141 being used to store system parity codes.

[0088] In the above technical solution, a hybrid storage block 111 for mixed storage of data and on-chip check codes is set up, eliminating the need to set up a separate storage sub-region for on-chip check codes, reducing the number of storage regions, thereby reducing the number of driver modules 120. Furthermore, placing the storage sub-region for storing system check codes in the same storage region can further reduce the number of storage regions, thereby further reducing the number of driver modules 120 and reducing the layout area of ​​the storage device.

[0089] The following example illustrates this. Figure 3 The storage device shown is relative to Figure 1 The improvements shown are in the storage device. For example: Figure 1 The storage device shown includes 6 data storage areas 510, 1 first hybrid storage area 520, 1 second hybrid storage area 530, 1 third hybrid storage area 540 and 1 fourth hybrid storage area 550, for a total of 10 storage areas, which requires 11 drive modules 120.

[0090] The following is a summary of the storage blocks used for storing data. Data storage area 510 includes four first storage blocks 511. The second storage sub-area 522 within the first mixed storage area 520 includes two third storage blocks 524; the fourth storage sub-area 532 within the second mixed storage area 530 includes two fifth storage blocks 534; the fifth storage sub-area 541 within the third mixed storage area 540 includes two sixth storage blocks 543; and the seventh storage sub-area 551 within the fourth mixed storage area 550 includes two eighth storage blocks 553. That is, in... Figure 1 The storage device shown has a total of 4×6+4×2=32 storage blocks for storing data. The storage blocks used to store on-chip checksums include two fourth storage blocks 533 and two second storage blocks 523, and the storage blocks used to store system checksums include one seventh storage block 544 and one ninth storage block 554.

[0091] exist Figure 3 The storage device shown includes eight first storage regions 110 and one second storage region 140. With a total of nine storage regions, ten drive modules 120 are required. Each first storage region 110 includes four hybrid storage blocks 111. Figure 3 The storage device shown has a total of 4 × 8 = 32 storage blocks for storing data. There is no need to set up separate storage blocks for storing on-chip checksums; two system checksum storage blocks 141 are provided in the second storage area 140 for storing system checksums.

[0092] That is Figure 1 The number of storage blocks used to store data and Figure 3 The same type of data can store the same amount of data. Figure 1 The number of storage blocks used to store system checksums and Figure 3 The same system checksum can store the same amount of data. Figure 3 There is no need to set up a separate storage block for storing on-chip checksums, which reduces the number of storage areas by one and the number of driver modules by one. Figure 3 The layout area of ​​the storage device shown is smaller.

[0093] In one embodiment, the second storage region 140 further includes a first redundant sub-region 402 and a second redundant sub-region 403. The first redundant sub-region 402 includes at least one first redundant storage block 142 arranged side-by-side on word lines. The first redundant storage block 142 is used to store a system checksum and serves as a backup storage block when the system checksum storage block 141 in the system checksum sub-region 401 fails. The second redundant sub-region 403 includes at least one second redundant storage block 143 arranged side-by-side on word lines. The second redundant storage block 143 is used to store data and on-chip checksums. The second redundant storage block 143 serves as a backup storage block when the hybrid storage block 111 in the first storage region 110 fails.

[0094] In the above technical solution, the redundant storage blocks that were originally distributed in various storage areas are concentrated in the second storage area 140, which can reduce the word line and bit line length in the first storage area 110, reduce the parasitic capacitance and / or parasitic resistance on the word lines and bit lines, shorten the data or check code storage response time of the storage cell, and improve the response rate.

[0095] In one embodiment, the second storage area 140 further includes three first virtual storage blocks 144, with a system check code sub-region 401 located between two first virtual storage blocks 144, and a first redundant sub-region 402 and a second redundant sub-region 403 arranged consecutively between two first virtual storage blocks 144. That is, the arrangement order on the word line is 1 first virtual storage block 144, 1 system check code sub-region 401, 1 first virtual storage block 144, 1 first redundant sub-region 402, 1 second redundant sub-region 403, and 1 first virtual storage block 144.

[0096] In the above technical solution, by setting the first virtual storage block 144 on both sides of the system check code sub-region 401, the system check code storage block 141 located at the edge of the system check code sub-region 401 has storage blocks on both sides, which is the same as the surrounding layout of the system check code storage block 141 located in the middle of the system check code sub-region 401. This is beneficial to the production and manufacturing of storage devices and improves the yield of storage devices.

[0097] In one embodiment, the first storage region 110 further includes two second virtual storage blocks 112. At least one contiguous hybrid storage block 111 is located between the two second virtual storage blocks 112.

[0098] In the above technical solution, by setting second virtual storage blocks 112 on both sides of the first storage area 110, the hybrid storage block 111 located at the edge of the first storage area 110 can have storage blocks on both sides, which is the same as the surrounding layout of the hybrid storage block 111 located in the middle of the first storage area 110. This is beneficial to the manufacturing of storage units and improves the yield of storage devices.

[0099] like Figure 4 As shown, the hybrid memory block 111 includes a plurality of first memory structures 101 arranged side-by-side in the word line direction. Each first memory structure 101 includes a first substructure 102 and a second substructure 103 arranged side-by-side in the word line direction. The first substructure 102 is used to store data and on-chip checksums. The second substructure 103 is used to store data and on-chip checksums.

[0100] refer to Figure 5 , Figure 5 The diagram only shows the specific structure of the first substructure 102 within a single hybrid storage block 111. The first substructure 102 includes multiple storage cells 151, nine consecutively arranged bit lines, and multiple consecutively arranged word lines 160. One bit line located at the edge of the nine consecutively arranged bit lines is called the first check bit line 152, and each of the remaining eight consecutively arranged bit lines is called a first data bit line 153. It should be noted here that... Figure 5 Only 6 character lines 160 are drawn in the text, but the number of character lines 160 is only for illustration and is not limited here.

[0101] The multiple memory cells 151 in the first substructure 102 are arranged in an array. Each memory cell 151 includes a transistor and a capacitor, so that the transistors in each memory cell 151 are also arranged in an array, and the capacitors in each memory cell 151 are also arranged in an array.

[0102] In the first substructure 102, a capacitor is connected to the source of the transistor in each memory cell 151. Each bit line is connected to the drain of the transistor arranged in the bit line direction and adjacent to that bit line. That is, the first data bit line 153 is connected to the drain of the transistor arranged in the bit line direction and adjacent to that first data bit line 153. The first check bit line 152 is connected to the drain of the transistor arranged in the bit line direction and adjacent to that first check bit line 152. Each word line 160 is connected to the gate of the transistor arranged in the word line direction and adjacent to that word line.

[0103] In the first substructure 102, nine bit lines are controlled by the same column select line. This column select line is referred to as the first column select line (not shown in the figure), and will not be discussed further here. Figure 5The diagram shows the connection relationship between the first column select line and the first check bit line 152, as well as the connection relationship between the first column select line and the first data bit line 153.

[0104] The storage unit 151 connected to the first data bit line 153 is used to store data, and the storage unit 151 connected to the first check bit line 152 is used to store on-chip check codes.

[0105] refer to Figure 6 The second substructure 103 includes multiple storage cells 151, nine consecutively arranged bit lines, and multiple consecutively arranged word lines 160. One of the nine consecutively arranged bit lines located at the edge is called the second check bit line 154, and each of the remaining eight consecutively arranged bit lines is called a second data bit line 155. The first check bit line 152 and the second check bit line 154 are arranged adjacent to each other. It should be noted here that... Figure 6 Only 6 character lines 160 are drawn in the text, but the number of character lines 160 is only for illustration and is not limited here.

[0106] The multiple memory cells 151 in the second substructure 103 are arranged in an array. Each memory cell 151 includes a transistor and a capacitor, so that the transistors in each memory cell 151 are also arranged in an array, and the capacitors in each memory cell 151 are also arranged in an array.

[0107] In the second substructure 103, the source of the transistor in each memory cell 151 is connected to a capacitor. Each bit line is connected to the drain of the transistor arranged in the bit line direction and adjacent to that bit line. That is, the second data bit line 155 is connected to the drain of the transistor arranged in the bit line direction and adjacent to that second data bit line 155. The second check bit line 154 is connected to the drain of the transistor arranged in the bit line direction and adjacent to that second check bit line 154. Each word line 160 is connected to the gate of the transistor arranged in the word line direction and adjacent to that word line 160.

[0108] In the second substructure 103, nine bit lines are controlled by the same column select line. This column select line is referred to as the second column select line (not shown in the figure), and will not be discussed further here. Figure 6 The diagram shows the connection relationship between the second column select line and the second check bit line 154, as well as the connection relationship between the second column select line and the second data bit line 155.

[0109] The storage unit 151 connected to the second data bit line 155 is used to store data, and the storage unit 151 connected to the second check bit line 154 is used to store on-chip check codes.

[0110] In one embodiment, the amplification module 130 includes a plurality of sensitive amplifiers. The sensitive amplifier connected to the first check bit line 152 in the first substructure 102 is called the first sensitive amplifier 156. The sensitive amplifier connected to the second check bit line 154 in the second substructure 103 is called the second sensitive amplifier 157. The first sensitive amplifier 156 and the second sensitive amplifier 157 are arranged on different sides of the first substructure 102 and the second substructure 103 in the bit line direction.

[0111] In one embodiment, the sensitive amplifiers connected to any two adjacent bit lines in the first substructure 102 are designated as the third sensitive amplifier 158 and the fourth sensitive amplifier 159, respectively. The third sensitive amplifier 158 and the fourth sensitive amplifier 159 are arranged on different sides of the first substructure 102 in the bit line direction. Taking the two outermost adjacent first data bit lines 153 in the first substructure 102 as an example, the outermost first data bit line 153 is connected to the third sensitive amplifier 158 located on the upper side, and the next outermost first data bit line 153 is connected to the fourth sensitive amplifier 159 located on the lower side.

[0112] In one embodiment, the sensitive amplifiers connected to any two adjacent bit lines in the second substructure 103 are designated as the fifth sensitive amplifier 161 and the sixth sensitive amplifier 162. The fifth sensitive amplifier 161 and the sixth sensitive amplifier 162 are arranged on different sides of the second substructure 103 in the bit line direction. Taking the two outermost adjacent second data bit lines 155 in the second substructure 103 as an example, the outermost second data bit line 155 is connected to the fifth sensitive amplifier 161 located on the upper side, and the next outermost second data bit line 155 is connected to the sixth sensitive amplifier 162 located on the lower side.

[0113] In the above technical solution, the first check bit line 152 is placed at the edge of the first substructure 102, and the second check bit line 154 is placed at the edge of the second substructure 103. The first check bit line 152 and the second check bit line 154 are arranged adjacent to each other, and the sensitive amplifiers connected to the first check bit line 152 and the second check bit line 154 are located on different sides, so that the hybrid memory block 111 is arranged symmetrically, which is beneficial to the production and manufacturing of the hybrid memory block 111 and improves the yield of the memory device.

[0114] In one embodiment, such as Figure 7As shown, the second storage area 140 includes a system checksum sub-area 401, a first redundancy sub-area 402, and a second redundancy sub-area 403. The system checksum sub-area 401 includes at least one system checksum storage block 141 arranged side-by-side on word lines, used to store the system checksum. The first redundancy sub-area 402 includes at least one first redundancy storage block 142 arranged side-by-side on word lines, used to store the system checksum. The first redundancy storage block 142 serves as a backup storage block when the system checksum storage block 141 in the system checksum sub-area 401 fails. The second redundancy sub-area 403 includes at least one second redundancy storage block 143 arranged side-by-side on word lines. The second redundancy storage block 143 stores data and on-chip checksums. The second redundancy storage block 143 serves as a backup storage block when the hybrid storage block 111 in the first storage area 110 fails.

[0115] Continue to refer to Figure 7 The system checksum storage block 141 includes multiple second storage structures 202 arranged side-by-side. (See reference) Figure 8 Each second storage structure 202 includes multiple storage cells 151, eight consecutively arranged bit lines, and multiple consecutively arranged word lines 160. The bit line among the eight consecutively arranged bit lines is referred to as the third data bit line 165. It should be noted here that... Figure 8 Only 6 character lines 160 are drawn in the text, but the number of character lines 160 is only for illustration and is not limited here.

[0116] In the second storage structure 202, multiple storage cells 151 are arranged in an array. Each storage cell 151 includes a transistor and a capacitor, so that the transistors in each storage cell 151 are also arranged in an array, and the capacitors in each storage cell 151 are also arranged in an array.

[0117] In the second memory structure 202, the source of the transistor in each memory cell 151 is connected to a capacitor, each third data bit line 165 is connected to the drain of the transistor arranged in the bit line direction and adjacent to the bit line, and each word line 160 is connected to the gate of the transistor arranged in the word line direction and adjacent to the word line 160.

[0118] Eight third data bit lines 165 are controlled by the same column select line, which is referred to as the third column select line (not shown in the figure). This will not be discussed further here. Figure 8 The diagram shows the connection between the third column selection line and the third data bit line 165 in the second storage structure 202. The storage cell 151 connected to the third data bit line 165 is used to store the system check code.

[0119] The sensitive amplifiers connected to any two adjacent third data bit lines 165 in the second memory structure 202 are designated as the seventh sensitive amplifier 166 and the eighth sensitive amplifier 167. The seventh sensitive amplifier 166 and the eighth sensitive amplifier 167 are arranged on different sides of the second memory structure 202 in the bit line direction. Taking the two outermost adjacent third data bit lines 165 in the second memory structure 202 as an example, the outermost third data bit line 165 is connected to the seventh sensitive amplifier 166 located on the upper side, and the next outermost third data bit line 165 is connected to the eighth sensitive amplifier 167 located on the lower side.

[0120] In the above technical solution, the system check code storage block 141 stores only the system check code. The system check code storage block 141 uses 8 third data bit lines 165, and the sensitive amplifiers connected to two adjacent third data bit lines 165 are located on different sides, so that the system check code storage block 141 is arranged symmetrically, which is beneficial to the production and manufacturing of the system check code storage block 141 and improves the yield of the storage device.

[0121] In one embodiment, the second redundant storage block 143 serves as a backup storage block when the hybrid storage block 111 in the first storage area 110 fails. Therefore, the structure of the second redundant storage block 143 is the same as that of the hybrid storage block 111. That is, the second redundant storage block 143 includes a sixth storage structure 203. Each sixth storage structure 203 includes a third substructure 204 and a fourth substructure 205. The structure of the third substructure 204 is the same as that of the first substructure 102, and the structure of the fourth substructure 205 is the same as that of the second substructure 103.

[0122] In one embodiment, the first redundant storage block 142 includes a plurality of third storage structures arranged side by side on word lines. The first redundant storage block 142 serves as a backup storage block when the system check code storage block 141 in the system check code sub-region 401 fails. Therefore, the structure of the third storage structure is the same as that of the second storage structure 202.

[0123] In the above technical solution, the number of hybrid storage blocks 111 is much greater than the number of checksum storage blocks 141. The structure of the second redundant storage block 143 is identical to that of the hybrid storage block 111, meaning it completely replicates the structure of the hybrid storage block 111. This ensures that even if the hybrid storage block 111 fails, data and checksums can still be stored through the second redundant storage block 143. The structure of the third storage structure in the first redundant storage block 142 is identical to the structure of the second storage structure 202 of the checksum storage block 141. In other words, the first redundant storage block 142 partially replicates the checksum storage block 141. This provides a backup storage structure while reducing the layout area of ​​the storage device.

[0124] In one embodiment, each first virtual memory block 144 includes multiple fourth memory structures arranged side-by-side on word lines, and each second virtual memory block 112 includes multiple fifth memory structures arranged side-by-side on word lines. The second virtual memory block 112 is used to ensure that the storage cells at the edges and in the middle of the hybrid memory block 111 have the same surrounding environment. The first virtual memory block 144 is used to ensure that the storage cells at the edges and in the middle of the system checksum storage block 141, the first redundant storage block 142, and the second redundant storage block 143 have the same surrounding environment. Since the first virtual memory block 144 and the second virtual memory block 112 are not used to store data, on-chip checksums, or system checksums, the second memory structure 202 occupies a smaller layout area. Therefore, making the structure of the fourth memory structure the same as the structure of the second memory structure 202, and the structure of the fifth memory structure the same as the structure of the second memory structure 202, can reduce the layout area of ​​the storage device.

[0125] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0126] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A storage device, characterized in that, include: At least one first storage area (110), at least one drive module (120), and at least one amplification module (130). The driving module (120) is arranged on both sides of the word line direction of each first storage area (110), and the amplification module (130) is arranged on both sides of the bit line direction of each first storage area (110). Each of the first storage areas (110) includes at least one hybrid storage block (111) arranged side by side in the word line direction, the hybrid storage block (111) being used to store data and on-chip check codes; The storage device includes a second storage area (140). The driving module (120) is arranged on both sides of the word line direction of the second storage area (140), and the amplification module (130) is arranged on both sides of the bit line direction of the second storage area (140). The second storage area (140) is provided with a system check code sub-area (401), the system check code sub-area (401) includes at least one system check code storage block (141) arranged side by side in the word line direction, the system check code storage block (141) is used to store the system check code.

2. The storage device according to claim 1, characterized in that, The at least one first storage area (110) is arranged side by side in the word line direction, and the second storage area (140) is located between the two first storage areas (110); Furthermore, only one drive module (120) is arranged between any two adjacent first storage areas (110), and only one drive module (120) is arranged between adjacent second storage areas (140) and first storage areas (110).

3. The storage device according to claim 1 or 2, characterized in that, The second storage area (140) is further provided with a first redundant sub-region (402) and a second redundant sub-region (403). The first redundant sub-region (402) includes at least one first redundant storage block (142) arranged side by side on the word line, and the second redundant sub-region (403) includes at least one second redundant storage block (143) arranged side by side on the word line. The first redundant storage block (142) is used to store the system check code, and the second redundant storage block (143) is used to store the data and the on-chip check code.

4. The storage device according to claim 3, characterized in that, The second storage area (140) also includes three first virtual storage blocks (144); The system check code sub-region is located between the two first virtual storage blocks (144), and the first redundant sub-region (402) and the second redundant sub-region (403) arranged consecutively are located between the two first virtual storage blocks (144).

5. The storage device according to claim 4, characterized in that, The first storage area (110) further includes two second virtual storage blocks (112); wherein the at least one hybrid storage block (111) arranged consecutively is located between the two second virtual storage blocks (112).

6. The storage device according to claim 1, characterized in that, The hybrid storage block (111) includes: a plurality of first storage structures (101) arranged side by side in the word line direction; Each of the first storage structures (101) includes a first substructure (102) and a second substructure (103) arranged side by side in the word line direction; the first substructure (102) is used to store the data and the on-chip check code; the second substructure (103) is used to store the data and the on-chip check code.

7. The storage device according to claim 6, characterized in that, The first substructure (102) includes a plurality of memory cells, nine consecutively arranged bit lines and a plurality of consecutively arranged word lines; each memory cell includes a transistor and a capacitor, the source of the transistor being connected to the capacitor; each bit line is connected to the drain of the transistors arranged in the bit line direction; Each of the word lines is connected to the gate of the transistors arranged in the word line direction; Wherein, the word line direction and the bit line direction are perpendicular to each other, and the nine bit lines are controlled by the same column select line; one bit line located at the edge of the nine consecutively arranged bit lines is called the first check bit line, and each of the remaining eight consecutively arranged bit lines is called the first data bit line. The storage unit connected to the first data bit line is used to store the data, and the storage unit connected to the first check bit line is used to store the on-chip check code.

8. The storage device according to claim 7, characterized in that, The second substructure (103) includes a plurality of memory cells, nine consecutively arranged bit lines and a plurality of consecutively arranged word lines; each bit line is connected to the drain of a transistor arranged in the bit line direction; each word line is connected to the gate of a transistor arranged in the word line direction. Wherein, the word line direction and the bit line direction are perpendicular to each other, and the nine bit lines are controlled by the same column select line; one bit line located at the edge of the nine consecutively arranged bit lines is called the second check bit line, and each of the remaining eight consecutively arranged bit lines is called the second data bit line. The storage unit connected to the second data bit line is used to store the data, and the storage unit connected to the second check bit line is used to store the on-chip check code; and the first check bit line and the second check bit line are arranged adjacent to each other.

9. The storage device according to claim 8, characterized in that, The amplification module includes multiple sensitive amplifiers; The first check code bit line in the first substructure (102) is connected to the first sensitive amplifier; the second check code bit line in the second substructure (103) is connected to the second sensitive amplifier; The first sensitive amplifier and the second sensitive amplifier are arranged on different sides of the first substructure (102) in the bit line direction.

10. The storage device according to claim 9, characterized in that, The sensitive amplifiers connected to any two adjacent bit lines in the first substructure (102) are labeled as the third sensitive amplifier and the fourth sensitive amplifier; the third sensitive amplifier and the fourth sensitive amplifier are arranged on different sides of the first substructure (102) in the bit line direction; The sensitive amplifiers connected to any two adjacent bit lines in the second substructure (103) are labeled as the fifth sensitive amplifier and the sixth sensitive amplifier; the fifth sensitive amplifier and the sixth sensitive amplifier are arranged on different sides of the second substructure (103) in the bit line direction.

11. The storage device according to claim 6, characterized in that, The system check code storage block (141) includes multiple second storage structures (202) arranged side by side; The second memory structure (202) includes multiple memory cells, eight consecutively arranged bit lines, and multiple consecutively arranged word lines. Each memory cell includes a transistor and a capacitor, with the source of the transistor connected to the capacitor. Each of the eight consecutively arranged bit lines is referred to as a third data bit line. Each of the third data bit lines is connected to the drain of a transistor arranged in the bit line direction; Each word line is connected to the gate of a transistor arranged in the word line direction; the word line direction and the bit line direction are perpendicular to each other, and the eight bit lines are controlled by the same column select line; the eight third data bit lines are connected to a memory cell used to store the system checksum.

12. The storage device according to claim 6, characterized in that, The structure of the second redundant storage block (143) is the same as that of the hybrid storage block (111).

13. The storage device according to claim 11, characterized in that, The first redundant storage block (142) includes a plurality of third storage structures arranged side by side on the word line; the structure of the third storage structure is the same as that of the second storage structure (202).

14. The storage device according to claim 11, characterized in that, Each first virtual storage block (144) includes multiple fourth storage structures arranged side by side on the word line, and each second virtual storage block (112) includes multiple fifth storage structures arranged side by side on the word line; the structure of the fourth storage structure is the same as that of the second storage structure (202), and the structure of the fifth storage structure is the same as that of the second storage structure (202).

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