Memory detection method, device and simulation detection method
By writing the first data into the storage cell and then rewriting different data and shortening the amplification time of the sensitive amplifier, the problem of anomaly detection that is not easily manifested in the memory manufacturing process is solved, and the detection accuracy and efficiency are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-17
- Publication Date
- 2026-06-05
Smart Images
Figure CN116486881B_ABST
Abstract
Description
Technical Field
[0001] This application relates to semiconductor manufacturing technology, and to, but is not limited to, a method, apparatus, and analog testing method for memory. Background Technology
[0002] In the research and development and manufacturing of memory, extensive testing is often required to identify any anomalies arising during the manufacturing process. These anomalies can include leakage current or read / write errors caused by short circuits, poor connections, or other issues during manufacturing. Because memory products have a precise and complex structure, a series of electrical tests are necessary to identify these anomalies. However, some anomalies are not easily apparent under normal read / write conditions but can affect lifespan and product reliability. Therefore, more reliable detection methods are needed to accurately identify these subtle anomalies. Summary of the Invention
[0003] In view of this, embodiments of this application provide a method and apparatus for detecting a memory.
[0004] In a first aspect, embodiments of this application provide a method for detecting a memory, comprising:
[0005] The first data is written to the memory cell to be detected through a sense amplifier (SA);
[0006] The second data is written to the storage unit through the sensitive amplifier. The second data is different from the first data. When writing the second data, the amplification time of the sensitive amplifier is shortened.
[0007] Read the data stored in the storage unit and determine whether the storage unit is abnormal based on the read data.
[0008] In some embodiments, shortening the amplification duration of the sensitive amplifier when writing the second data includes:
[0009] Select the bit line coupled to the memory cell so that the write voltage to be written is transmitted to the bit line;
[0010] After the bit line is selected, the amplification function of the sensitive amplifier is activated after a predetermined first time delay; wherein, after the sensitive amplifier activates the amplification function, the second data is written to the memory cell based on the write voltage.
[0011] In some embodiments, the sensitive amplifier includes: a power supply node; the step of activating the amplification function of the sensitive amplifier after a predetermined first duration following gating of the bit line includes:
[0012] After the bit line is selected, an enable voltage is applied to the power node after a first delay to enable the amplification function of the sensitive amplifier.
[0013] In some embodiments, shortening the amplification duration of the sensitive amplifier when writing the second data includes:
[0014] Select the bit line coupled to the memory cell so that the write voltage to be written is transmitted to the bit line;
[0015] After the bit line is selected, the amplification function of the sensitive amplifier is turned off for a predetermined second duration; wherein, after the sensitive amplifier turns on the amplification function, it writes second data to the memory cell based on the write voltage.
[0016] In some embodiments, the sensitive amplifier includes: a power node; the step of disabling the amplification function of the sensitive amplifier for a predetermined second duration after strobing the bit line includes:
[0017] After the bit line is selected, a shutdown voltage is applied to the power node after a predetermined second delay to disable the amplification function of the sensitive amplifier.
[0018] In some embodiments, the first write duration when writing the first data is equal to the second write duration when writing the second data;
[0019] When writing the first data, the first amplification duration of the sensitive amplifier is greater than the second amplification duration of the sensitive amplifier when writing the second data.
[0020] In some embodiments, selecting the bit line coupled to the memory cell to transmit the write voltage to the bit line includes:
[0021] During the second write duration, the bit line coupled to the memory cell is selected so that the write voltage to be written is transmitted to the bit line; wherein the second write duration is longer than the second amplification duration of the sensitive amplifier.
[0022] In some embodiments, the memory includes at least one memory block, and the memory block includes a plurality of memory cells; the method further includes:
[0023] During the process of writing first data to the memory cell to be tested, the word line coupled to the memory cell to be tested is selected, and multiple bit lines connected to the word line are selected simultaneously. The first data is then written simultaneously to the multiple bit lines and the multiple memory cells coupled to the word line.
[0024] During the process of writing the second data to the memory cell to be detected, the second data is simultaneously written to the multiple memory cells coupled to the multiple bit lines and the word lines.
[0025] In some embodiments, the memory includes the memory cell to be detected on each of a plurality of memory blocks; the word line that is selected and coupled to the memory cell to be detected includes:
[0026] Simultaneously select word lines on multiple memory blocks that are coupled to the memory cell to be detected.
[0027] Secondly, embodiments of this application also provide a memory detection device, comprising:
[0028] The write module is configured to write data to the memory cell to be detected via a sensitive amplifier;
[0029] The control module is configured to control the amplification duration of the sensitive amplifier;
[0030] The reading module is configured to read the data stored in the storage unit and determine whether the storage unit is abnormal based on the read data.
[0031] In some embodiments, the control module includes:
[0032] The timing control module is configured to shorten the amplification duration of the sensitive amplifier.
[0033] In some embodiments, the timing control module includes:
[0034] The delay module is configured to delay the activation of the amplification function of the sensitive amplifier.
[0035] In some embodiments, the timing control module includes:
[0036] The shutdown module is configured to prematurely disable the amplification function of the sensitive amplifier.
[0037] Thirdly, embodiments of this application also provide a simulation detection method, the method comprising:
[0038] The process of writing the first data to the memory cell to be tested is simulated by controlling a sensitive amplifier;
[0039] The process of writing second data, different from the first data, to the storage unit is simulated by controlling the sensitive amplifier. When writing the second data, the amplification time of the sensitive amplifier is shortened by adjusting the control signal of the sensitive amplifier.
[0040] Read the data stored in the storage unit and determine whether the storage unit is abnormal based on the read data.
[0041] In some embodiments, shortening the amplification duration of the sensitive amplifier by adjusting the control signal of the sensitive amplifier when writing the second data includes:
[0042] After selecting the bit line of the memory cell, the amplification time of the sensitive amplifier is shortened by providing a delayed-on control signal.
[0043] In some embodiments, shortening the amplification duration of the sensitive amplifier by adjusting the control signal of the sensitive amplifier when writing the second data includes:
[0044] After selecting the bit line of the memory cell, the amplification duration of the sensitive amplifier is shortened by providing a control signal to turn it off in advance.
[0045] The technical solution of this application embodiment first writes first data into the storage unit, and then rewrites second data, which is different from the first data. Furthermore, the amplification time of the sensitive amplifier is shortened when writing the second data. In this way, on the one hand, shortening the amplification time of the sensitive amplifier increases the difficulty of writing, making it more difficult to write correct data into a storage unit with an anomaly; on the other hand, if writing the second data fails, the data stored in the storage unit remains the first data, making it easier to detect and thus improving the detection accuracy. Attached Figure Description
[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0047] Figure 1 A flowchart of a memory detection method according to an embodiment of this application. Figure 1 ;
[0048] Figure 2 This is a structural block diagram of a memory detection device according to an embodiment of this application;
[0049] Figure 3 A flowchart of a memory detection method according to an embodiment of this application. Figure 2 ;
[0050] Figure 4 This is a schematic diagram illustrating the principle of a memory detection method according to an embodiment of this application;
[0051] Figure 5A A timing diagram of writing second data to a memory cell in a memory detection method according to an embodiment of this application;
[0052] Figure 5B A memory detection method according to an embodiment of this application includes a writing schematic diagram based on a circuit structure.
[0053] Figure 6A In a memory detection method according to an embodiment of this application, a signal timing diagram is shown when the second data "0" is written to the memory cell and SA is normally enabled;
[0054] Figure 6B In a memory detection method according to an embodiment of this application, a signal timing diagram is shown when the second data "0" is written to the memory cell and the amplification function of SA is delayed in being turned on.
[0055] Figure 6C In a memory detection method according to an embodiment of this application, a signal timing diagram is shown when the second data "0" is written to the memory cell and the amplification function of SA is turned off in advance;
[0056] Figure 6D In a memory detection method according to an embodiment of this application, a signal timing diagram is shown when the second data "1" is written to the memory cell and the amplification function of SA is normally enabled.
[0057] Figure 6E In a memory detection method according to an embodiment of this application, a signal timing diagram is shown when the second data "1" is written to the memory cell and the amplification function of SA is delayed in being turned on.
[0058] Figure 6F This is a timing diagram of a memory detection method according to an embodiment of the present application, in which a second data "0" is written to a memory cell and the amplification function of SA is turned off in advance.
[0059] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0060] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0061] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims. The technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments.
[0062] like Figure 1 The present application provides a method for detecting a memory, comprising:
[0063] Step S101: Write the first data to the memory cell to be detected through a sensitive amplifier;
[0064] Step S102: Write second data to the storage unit through the sensitive amplifier. The second data is different from the first data. When writing the second data, shorten the amplification time of the sensitive amplifier.
[0065] Step S103: Read the data stored in the storage unit and determine whether the storage unit is abnormal based on the read data.
[0066] The memory involved in the embodiments of this application can be a semiconductor memory, which is a solid-state electronic device for storing data information manufactured using semiconductor integrated circuit technology. The memory can include multiple storage surfaces, and each storage surface can further include multiple storage blocks. Each storage block consists of multiple storage cells arranged in an array. Each storage cell can be connected to peripheral circuits via word lines and bit lines, and read, write, and detection operations are implemented based on signal control from the peripheral circuits.
[0067] Taking Dynamic Random Access Memory (DRAM) as an example, each memory cell is connected to a bit line (BL) and a complementary bit line ( / BL). A sensitive amplifier is connected between the bit line and the complementary bit line via various control devices. When data reading or writing is required, activating the sensitive amplifier at the appropriate time amplifies the slight voltage difference between the bit line and the complementary bit line, thereby ensuring that the data in the memory cell is correctly read or that the input signal is converted into charge and correctly stored in the memory cell.
[0068] During memory testing, a predetermined first data is written into the memory cell using a sensitive amplifier, and then the memory cell is read back to determine if it is functioning correctly. However, some memory cells have structural defects from the manufacturing process. For example, the resistance of the bit line contact (BLC) connecting the memory cell to the bit line may be too high, even though the cell can still be charged during normal data writing and read correctly. This situation is not easily detected, leading to anomalies in later stages or reduced product reliability.
[0069] Therefore, in this embodiment, a two-stage write operation is employed: first, first data is written to the storage unit, and then second data, different from the first data, is written back to the storage unit. Furthermore, the amplification time of the sensitive amplifier is shortened during the writing of the second data.
[0070] Shortening the amplification duration of the sensitive amplifier worsens the detection conditions during the write process. If an anomaly exists in the memory cell, data may be difficult to write correctly within the shorter amplification duration. Therefore, by shortening the amplification duration of the sensitive amplifier, anomalies that would otherwise be difficult to detect can be made apparent.
[0071] The process of writing the first data can be used as an initialization process for the storage unit under test. Its purpose is to reset the charge of the storage unit when writing the second data, so as to prevent the failure of the above-mentioned deterioration conditions caused by the storage unit itself storing the same data as the second data. This ensures that the second data is written under deterioration conditions, thereby reducing the chance of missed detection.
[0072] It is understandable that the time for writing the first data can be the same as the amplification time used when writing data during normal use of the memory, or the amplification time used during general detection; or an extended amplification time can be used to write the first data into the memory cell as much as possible.
[0073] For example, the first data "0" is written to the storage cell, and then the data "1" is written using the shortened amplification time of the sensitive amplifier as the writing condition. If the storage cell is faulty, it is difficult to write the data "1" correctly within the shortened amplification time of the sensitive amplifier, so the data "0" may still be read when reading data. In this way, faulty storage cells can be accurately identified.
[0074] In some embodiments, shortening the amplification duration of the sensitive amplifier when writing the second data includes:
[0075] Select the bit line coupled to the memory cell so that the write voltage to be written is transmitted to the bit line;
[0076] After the bit line is selected, the amplification function of the sensitive amplifier is activated after a predetermined first time delay; wherein, after the sensitive amplifier activates the amplification function, the second data is written to the memory cell based on the write voltage.
[0077] In this embodiment of the application, the amplification time of the sensitive amplifier can be shortened by delaying the amplification time of the sensitive amplifier when writing the second data.
[0078] Here, a first duration can be set as the time required to delay the activation of the sensitive amplifier's amplification function. Based on the normal data writing amplification time, the sensitive amplifier's amplification function is activated after this first duration. In this way, if a memory cell malfunctions, the second data to be written will not have enough time to be stored in the memory cell, thus preventing the correct second data from being read.
[0079] Correspondingly, if there is no abnormality in the storage unit, the second data can be written correctly within the shortened amplification period, so it can be determined to be normal.
[0080] It should be noted that the method for determining the aforementioned first duration can be based on empirical values obtained through experimentation, and then set according to these empirical values. Alternatively, based on the structural characteristics of the memory, such as its product size, the relationship between the sensitivity amplifier's amplification duration and whether data can be written normally can be calculated, and the required first delay duration can be determined based on the amplification duration of the threshold value for normal data writing or slightly greater than the threshold value.
[0081] In some embodiments, the sensitive amplifier includes: a power supply node; the step of activating the amplification function of the sensitive amplifier after a predetermined first duration following gating of the bit line includes:
[0082] After the bit line is selected, an enable voltage is applied to the power node after a first delay to turn on the sensitive amplifier.
[0083] As an active device, the sensitive amplifier requires a voltage input from the power supply node to amplify the signal. During use, the power supply node of the memory can be connected to an external constant voltage power supply to maintain fast read and write capabilities.
[0084] In this embodiment of the application, the detection process can be performed by adjusting the signal waveform of the power supply node to control the amplification duration of the sensitive amplifier.
[0085] Regarding the implementation of the amplification function of the sensitive amplifier after a first delay, the amplification function of the sensitive amplifier can be activated by applying a voltage pulse delayed by the first delay to the power supply node as the activation voltage. For example, the voltage applied to the power supply node during the first delay before activation is 0.5V, and then switched to 5V as the activation voltage, enabling the sensitive amplifier to amplify the signal.
[0086] In some embodiments, shortening the amplification duration of the sensitive amplifier when writing the second data includes:
[0087] Select the bit line coupled to the memory cell so that the write voltage to be written is transmitted to the bit line;
[0088] After the bit line is selected, the amplification function of the sensitive amplifier is turned off for a predetermined second duration; wherein, after the sensitive amplifier turns on the amplification function, it writes the second data to the memory cell based on the write voltage.
[0089] Similar to the delay method in the above embodiments, in this embodiment, the amplification time of the sensitive amplifier can be shortened by turning off the amplification function of the sensitive amplifier in advance, and the second data can be written to the storage unit during the period when the amplification function of the sensitive amplifier is turned on.
[0090] The second duration mentioned above can be the same as or different from the first duration.
[0091] In some embodiments, the sensitive amplifier includes: a power node; the step of disabling the amplification function of the sensitive amplifier for a predetermined second duration after strobing the bit line includes:
[0092] After the bit line is selected, a shutdown voltage is applied to the power node after a predetermined second delay to disable the amplification function of the sensitive amplifier.
[0093] Here, the amplification duration of the sensitive amplifier can also be controlled by adjusting the signal waveform of the power supply node.
[0094] This involves switching the voltage signal applied to the power node to a shutdown voltage a second time interval in advance, preventing the sensitive amplifier from amplifying the signal. For example, applying a startup voltage, such as 5V, during the period when the sensitive amplifier's amplification function is enabled, and then switching the startup voltage to a shutdown voltage, such as 0.5V, a second time interval in advance, will disable the sensitive amplifier's amplification function. This shortens the time it takes for the charge written to the second data to be charged into the memory cell, thereby making the abnormality of the memory cell apparent.
[0095] Understandably, during the testing process, the sensitive amplifier can remain normally connected to the bit line, with the voltage of the power supply node adjusted by externally input pulses, thereby changing the amplification capability of the sensitive amplifier. This ensures that, apart from the varying amplification duration of the sensitive amplifier, other parameters remain consistent with the normal writing process, preventing the introduction of other variables and achieving accurate testing. Furthermore, the testing process does not damage the device, facilitating online testing.
[0096] In some embodiments, the first write duration when writing the first data is equal to the second write duration when writing the second data;
[0097] When writing the first data, the first amplification duration of the sensitive amplifier is greater than the second amplification duration of the sensitive amplifier when writing the second data.
[0098] Here, when writing data, the bit line is selected via the strobe signal YS, and the voltage corresponding to the data to be written is transmitted to the bit line via the data input bus connected to the bit line. The duration of the bit line selection is the duration of writing data into the memory cell. During this period, the charge on the bit line is transferred to the storage capacitor through the control switch of the memory cell to achieve data storage.
[0099] Correspondingly, during the data writing process, the amplification function of the sensitive amplifier is turned on, which can amplify the small voltage difference between the bit line and the complementary bit line, facilitating the charging or discharging of the storage capacitor.
[0100] In this embodiment, the same writing duration can be used for writing the first data and the second data, while different amplification durations of the sensitive amplifier are used during the writing process. That is, the amplification duration of the sensitive amplifier is shorter when writing the second data than when writing the first data. In this way, the testing objective can be achieved without adjusting other signal waveforms during the testing process, facilitating the setting and modification of test parameters.
[0101] In some embodiments, selecting the bit line coupled to the memory cell to transmit the write voltage to the bit line includes:
[0102] During the second write duration, the bit line coupled to the memory cell is selected so that the write voltage to be written is transmitted to the bit line; wherein the second write duration is longer than the second amplification duration of the sensitive amplifier.
[0103] Here, the second write duration is the amplification duration of the bit line selection signal YS mentioned above. During the second duration, the bit line is selected, and the write voltage to be written will be transmitted to the bit line, so that there is a voltage difference between the bit line and the complementary bit line.
[0104] When the amplification function of the sensitive amplifier is turned on, the voltage difference between the bit line and the complementary bit line will be amplified, so that the voltage on the bit line can charge or discharge the memory cell, and then write the corresponding data.
[0105] In some embodiments, the memory includes at least one memory block, and the memory block includes a plurality of memory cells; the method further includes:
[0106] During the process of writing first data to the memory cell to be tested, the word line coupled to the memory cell to be tested is selected, and multiple bit lines connected to the word line are selected simultaneously. The first data is then written simultaneously to the multiple bit lines and the multiple memory cells coupled to the word line.
[0107] During the process of writing the second data to the memory cell to be detected, the second data is simultaneously written to the multiple memory cells coupled to the multiple bit lines and the word lines.
[0108] In this embodiment of the application, multiple bit lines can be selected simultaneously during detection, so that multiple memory cells on the same word line can be detected.
[0109] For example, the word line coupled to the memory cell under test is selected, and the adjacent 8 bit lines are simultaneously selected, and the first data is written. In this way, 8 bits of data can be written at a time. Then, the second data is written to these memory cells, thus realizing the update of 8 bits of data.
[0110] Of course, multiple bit lines can be selected simultaneously during reading to read data from multiple memory cells at the same time. For example, after writing 8 bits of the second data, these 8 memory cells can be read, and the read data can be checked to see if it matches the written second data. If the data read from any memory cell is inconsistent with the second data, it indicates that there is an anomaly in that memory cell.
[0111] This allows for fast writing and detection, saving detection time and improving detection efficiency.
[0112] In some embodiments, the memory includes the memory cell to be detected on each of a plurality of memory blocks; the word line that is selected and coupled to the memory cell to be detected includes:
[0113] Simultaneously select word lines on multiple memory blocks that are coupled to the memory cell to be detected.
[0114] In this embodiment of the application, multiple memory blocks on the memory can be detected synchronously. For example, a word line can be selected and detected synchronously on multiple memory blocks.
[0115] In some embodiments, detecting all memory cells of a memory can simultaneously select one word line on multiple memory blocks (e.g., n) and simultaneously select multiple bit lines on each memory block (e.g., m). In this way, synchronous detection of n×m memory cells can be achieved, greatly improving detection efficiency.
[0116] like Figure 2 As shown in the figure, this application embodiment also provides a memory detection device 200, including:
[0117] The write module 201 is configured to write data to the memory cell to be detected via a sensitive amplifier;
[0118] Control module 202 is configured to control the amplification duration of the sensitive amplifier;
[0119] The reading module 203 is configured to read the data stored in the storage unit and determine whether the storage unit is abnormal based on the read data.
[0120] The aforementioned writing module, control module, and reading module can be located in a detection device independent of the memory, can be connected to the peripheral circuits of the memory, and can realize the read and write control of the memory by providing various signals, thereby realizing the detection of the memory.
[0121] In another embodiment, the detection device described above may also be located in the memory and directly connected to the memory unit via an external circuit.
[0122] Of course, the aforementioned detection device can also be located in any host system that can connect to and control the memory.
[0123] In some embodiments, the control module includes:
[0124] The timing control module is configured to shorten the amplification duration of the sensitive amplifier.
[0125] In some embodiments, the timing control module includes:
[0126] The delay module is configured to delay the activation of the amplification function of the sensitive amplifier.
[0127] In some embodiments, the timing control module includes:
[0128] The shutdown module is configured to prematurely disable the amplification function of the sensitive amplifier.
[0129] The modules mentioned above can be independent hardware modules, or they can be the same hardware module with different functions. In practical applications, the modules can be split or combined, which is not limited here.
[0130] like Figure 3 As shown in the embodiments of this application, a simulation detection method is also provided, the method comprising:
[0131] Step S301: Simulate the process of writing the first data to the memory cell to be tested by controlling the sensitive amplifier;
[0132] Step S302: Simulate the process of writing second data different from the first data to the storage unit by controlling the sensitive amplifier, wherein, when writing the second data, the amplification time of the sensitive amplifier is shortened by adjusting the control signal of the sensitive amplifier;
[0133] Step S303: Read the data stored in the storage unit and determine whether the storage unit is abnormal based on the read data.
[0134] In this embodiment, software can be used to simulate and detect read / write anomalies in memory cells. The simulation detection method can be applied to actual memory products or to virtual testing of analog memory. For example, software can simulate the memory and memory cell circuit parameters in the design under test, then write first data using analog signals, and write second data using a sensitive amplifier with shortened amplification time. In this way, abnormalities such as data reading defects in the memory cell, contact structure design defects, leakage current, or excessive impedance can be detected using analog signals, thus identifying corresponding product design anomalies.
[0135] During the aforementioned simulation testing, the amplification time of the sensitive amplifier can be shortened using software. For example, the signal waveform of the sensitive amplifier can be adjusted using software, and the data writing process can be simulated based on a simulated memory and storage unit circuit, thereby simulating the situation where the amplification time of the sensitive amplifier is shortened during the writing process.
[0136] In this way, on the one hand, design defects can be easily and quickly found by using simulation circuits and analog signals, saving testing costs and product development costs; on the other hand, during the simulation testing process, the amplification duration of the sensitive amplifier can be adjusted multiple times according to requirements, and a suitable amplification duration that can detect predetermined abnormalities can be found, and the amplification duration obtained from the simulation testing can be applied to the online testing of the product.
[0137] In some embodiments, shortening the amplification duration of the sensitive amplifier by adjusting the control signal of the sensitive amplifier when writing the second data includes:
[0138] After selecting the bit line of the memory cell, the amplification time of the sensitive amplifier is shortened by providing a delayed-on control signal.
[0139] In some embodiments, shortening the amplification duration of the sensitive amplifier by adjusting the control signal of the sensitive amplifier when writing the second data includes:
[0140] After selecting the bit line of the memory cell, the amplification duration of the sensitive amplifier is shortened by providing a control signal to turn it off in advance.
[0141] The above-mentioned methods for controlling the amplification duration of the sensitive amplifier can also include two cases: delaying the start-up control signal and prematurely turning off the control signal.
[0142] In addition, in other embodiments, a periodic signal with a certain duty cycle can be provided as a control signal to repeatedly switch the amplification function of the sensitive amplifier between on and off states. Thus, by adjusting the duty cycle of this control signal, the amplification duration of the sensitive amplifier can be adjusted.
[0143] This application also provides the following examples in its embodiments:
[0144] Extensive product testing is required during the development and production of DRAM to identify defects and facilitate improvements.
[0145] In this embodiment, a "Y-Page" approach can be used to perform write and read operations on the DRAM memory array to achieve detection. Here, the "Y-Page" read / write method means that multiple bit lines are selected simultaneously in a single write or read operation, and once the same word line is selected, it can remain open until all write or read operations have been performed on that word line.
[0146] Furthermore, a compression mode can be used to test multiple storage blocks simultaneously, that is, to select a word line on multiple storage blocks at the same time, and to perform read and write operations using the "Y-Page" method described above. This can significantly reduce testing time and lower development costs.
[0147] like Figure 4 In this embodiment, the "Y-Page" method (which can be combined with the compression mode) is used to write the first data "1" to the storage unit under test, thus ensuring that there is no unknown data in any of the storage units under test. The amplification time of the sensitive amplifier is adjusted, and the second data "0" is rewritten to each storage unit within the shortened amplification time of the sensitive amplifier. Finally, the data in each storage unit is read using the "Y-Page" method, and the presence of any anomalies is determined based on the reading results.
[0148] After reading this information, the amplification function of the sensitive amplifier can be restored to normal operation, allowing for further subsequent operations.
[0149] Finally, the data can be reset and the above test can be performed again. For example, the first data "0" can be rewritten to the memory cell under test, and then the second data "1" can be rewritten to each memory cell within a shortened amplification time of the sensitive amplifier. In this way, the test results can be further improved and the number of missed detections can be reduced.
[0150] Taking writing the second data as "0" as an example, the signal timing on bit line BL and the complementary bit line / BL is as follows: Figure 5A As shown, Figure 5B This is a schematic diagram for writing data to the circuit structure. Writing the second data "0" includes the following process:
[0151] 1. After the ACT command is activated, BLEQ (Bit Line Equalization) is turned off. After BLEQ is turned off, bit line BL and complementary bit line / BL are not subject to the equal voltage V. BLE It is subject to constraints and will be affected by storage cells and write signals.
[0152] 2. When the word line is turned on (WL on), charge sharing begins between the memory cell and the BL, causing the voltage of the BL to rise to V. BLE There is a voltage difference ΔV between +ΔV and / BL.
[0153] 3. In the MOS (Metal-Oxide-Semiconductor) device of the sensitive amplifier SA, both NMOS devices M1 and M2 are turned on, but M2 is turned on to a greater extent than M1. Therefore, the potential on / BL is pulled down to V. ss Because M1 was briefly turned on, BL was briefly lowered, which in turn caused M1 to be turned off again.
[0154] 4. The voltage of / BL is V. ss This causes the control electrode potential of PMOS device M3 to be V. ss This is then turned on, further pulling the voltage on BL down to V. ary .
[0155] 5. When YS is turned on, the external input signal (i.e., the voltage corresponding to the second input data "0") is transmitted to BL, quickly pulling the potential of BL low and the potential of / BL high. Then, when YS is turned off, PMOS device M4 is turned on, NMOS device M1 is turned on, and M3 and M2 are turned off. At this time, the potential on / BL is pulled high again to V. ary BL was lowered to V. ss This allows the storage cell to store the charge corresponding to the second data "0".
[0156] 6. After storing the second data "0", WL is turned off, the amplification function of the sensitive amplifier SA is turned off, BLEQ is re-inputted with the signal to turn on NMOS, turning on NMOS devices M5, M6 and M7, so that the voltage of BL and / BL is pulled back to V. BLE Until the entire circuit is accessed again.
[0157] also, Figure 5A The timing involved includes several key timing parameters for performing write operations on memory cells, including:
[0158] tRCD (DRAM RAS to CAS Delay): RAS signal is the Row Address Strobe signal; CAS signal is the Column Address Strobe signal. tRCD defines the time required for memory to operate on a row address after an Active (ACT) command is issued within a memory rank (memory plane). Each memory cell is an address that can store data, and each address has a corresponding row number and column number. Each row contains 1204 column addresses. When a row address is activated, multiple CAS requests are sent for read and write operations. Simply put, knowing the row address location, finding the corresponding column address within that row completes the addressing, allowing read and write operations. The time from the known row address to the column address is tRCD. When a row address in memory is activated, it is called "opening a page." At any given time, the same rank can open 8 row addresses (8 banks, or one for each of the 8 memory chips). Figure 5A In this context, the time interval between issuing the row address activation command (ACT) and finding the column address and issuing the write command is called tRCD.
[0159] tWR (DRAM Write Recovery Time): Used to define the memory write recovery time from a command (such as...) Figure 5A The WR command in the memory (starting from the start of writing) is issued within the time interval before the next precharge interval, which is the operation preceding the memory row address controller precharge time. If this time is set too short, the next precharge may begin before the previous write is completed, and addressing may occur, resulting in incomplete data from the previous write and data loss. In this embodiment, this can be achieved by... Figure 5A During the time period corresponding to tWR shown, the amplification time of the signal amplification function of the sensitive amplifier SA is shortened by adjusting the power node signal waveform of the sensitive amplifier SA.
[0160] tRP (DRAM RAS Precharge Time): tRP defines the time between the completion of the previous row address operation and the row address close command (e.g., ...). Figure 5A The WL shutdown command is issued and a precharge command is issued (e.g., ...). Figure 5A After the RPE command in the memory management system, the system prepares to operate on the next row address in the same bank. tRP is the precharge time given before the next row address activation signal is issued. Since multiple row addresses in a rank may be being read from or written to before the row address close command is issued, tRP has a smaller impact on memory performance than tRCD. The impact of tRP increases with frequent operations on a bank by multiple row address activation and close signals, and relaxing tRP can help improve stability.
[0161] tRAS (DRAM Active to Precharge Delay): Generally, it is the sum of tRCD and tWR mentioned above. If the tRAS period is too long, the system will experience performance degradation due to excessive waiting time. If the tRAS is too short, the activated row address will enter the inactive state earlier, leading to data loss or corruption.
[0162] The case of writing the second data as "1" is similar to the case of writing the second data as "0" as described above, and will not be repeated here.
[0163] In steps 3 and 4 above, turning on the MOS device of the sensitive amplifier SA enables the sensitive amplifier to amplify the signal. In this embodiment, the sensitive amplifier can be flexibly adjusted by changing the duration of the power supply voltage provided on the power nodes (including the PCS node and the NCS node). For example, by shortening the duration of the power supply voltage, the actual signal amplification time of the sensitive amplifier SA can be shortened. This reduces the time required to store charge in the memory cell, increases the difficulty of writing the second data, and makes it easier to detect anomalies in the memory cell.
[0164] If the amplification duration of the sensitive amplifier SA is not shortened when the second data is written as "0", then the waveform timing on its bit line BL and complementary bit line / BL is as follows: Figure 6A As shown, after the bit line strobe signal YS is turned on, the voltages on bit line BL and the complementary bit line / BL rapidly flip. This allows the memory cell to be charged normally to store the corresponding data. Even if there are defects in the contact structure of the memory cell, such as excessive impedance of the BLC connecting the memory cell to the bit line, the correct data can be written within a sufficiently long charging time, making it difficult to detect.
[0165] If the amplification function of the sensitive amplifier SA is delayed when the second data "0" is written, the waveform timing diagrams on bit line BL and the complementary bit line / BL are as follows. Figure 6B As shown, after the bit line strobe signal YS is turned on, the voltage on bit line BL and complementary bit line / BL cannot flip quickly. After the amplification function of SA is turned on, the voltage on bit line BL and complementary bit line / BL is amplified. However, since the voltage on bit line BL and complementary bit line / BL is insufficient when the amplification function of SA is normally turned off, the voltage and duration for storing data in the memory cell are insufficient, making it difficult to store the correct data and making it easier to be detected.
[0166] Correspondingly, such as Figure 6C As shown, after the bit line strobe signal YS is turned on, the voltages on bit line BL and complementary bit line / BL flip rapidly and are amplified after the amplification function of SA is turned on. However, because the amplification function of SA is turned off prematurely, the voltages on bit line BL and complementary bit line / BL fail to reach the required potential and return to the same potential prematurely. This also results in insufficient voltage and insufficient time for storing data in the memory cell, making it difficult to store the correct data and making it easier to be detected.
[0167] When the second data is written as "1", if the amplification duration of the sensitive amplifier SA is not shortened, then the waveform timing on its bit line BL and the complementary bit line / BL will be as follows: Figure 6D As shown. If the amplification function of the sensitive amplifier SA is delayed, the corresponding waveform timing is as follows. Figure 6E As shown, if the amplification function of the sensitive amplifier SA is turned off in advance, the corresponding timing waveform is as follows. Figure 6F As shown.
[0168] The above Figures 6A to 6F This is only used as an example to illustrate the situation where the amplification function of the delayed-on and early-off sensitive amplifier under different write data conditions causes insufficient data potential in the write memory cell, and does not represent the actual waveform duration, proportion, etc.
[0169] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.
[0170] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0171] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.
[0172] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.
[0173] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.
[0174] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for detecting a memory, characterized in that, The method includes: The first data is written to the memory cell to be tested through a sensitive amplifier; The second data is written to the storage unit through the sensitive amplifier. The second data is different from the first data. When writing the second data, the amplification time of the sensitive amplifier is shortened. Read the data stored in the storage unit and determine whether the storage unit is abnormal based on the read data.
2. The detection method according to claim 1, characterized in that, The step of shortening the amplification duration of the sensitive amplifier when writing the second data includes: Select the bit line coupled to the memory cell so that the write voltage to be written is transmitted to the bit line; After the bit line is selected, the amplification function of the sensitive amplifier is activated after a predetermined first time delay; wherein, after the sensitive amplifier activates the amplification function, the second data is written to the memory cell based on the write voltage.
3. The detection method according to claim 2, characterized in that, The sensitive amplifier includes: a power supply node; the step of activating the amplification function of the sensitive amplifier after a predetermined first time delay after selecting the bit line includes: After the bit line is selected, an enable voltage is applied to the power node after a first delay to enable the amplification function of the sensitive amplifier.
4. The detection method according to claim 1, characterized in that, The step of shortening the amplification duration of the sensitive amplifier when writing the second data includes: Select the bit line coupled to the memory cell so that the write voltage to be written is transmitted to the bit line; After the bit line is selected, the amplification function of the sensitive amplifier is turned off for a predetermined second duration; wherein, after the sensitive amplifier turns on the amplification function, it writes second data to the memory cell based on the write voltage.
5. The detection method according to claim 4, characterized in that, The sensitive amplifier includes: a power supply node; the step of disabling the amplification function of the sensitive amplifier for a predetermined second duration after selecting the bit line includes: After the bit line is selected, a shutdown voltage is applied to the power node after a predetermined second delay to disable the amplification function of the sensitive amplifier.
6. The detection method according to any one of claims 2 to 5, characterized in that, The first write duration when writing the first data is equal to the second write duration when writing the second data; When writing the first data, the first amplification duration of the sensitive amplifier is greater than the second amplification duration of the sensitive amplifier when writing the second data.
7. The detection method according to claim 6, characterized in that, The selection of the bit line coupled to the memory cell, enabling the write voltage to be written to be transmitted to the bit line, includes: During the second write duration, the bit line coupled to the memory cell is selected so that the write voltage to be written is transmitted to the bit line; wherein the second write duration is longer than the second amplification duration of the sensitive amplifier.
8. The detection method according to claim 1, characterized in that, The memory includes at least one memory block, and the memory block includes multiple memory cells; the method further includes: During the process of writing first data to the memory cell to be tested, the word line coupled to the memory cell to be tested is selected, and multiple bit lines connected to the word line are selected simultaneously. The first data is then written simultaneously to the multiple bit lines and the multiple memory cells coupled to the word line. During the process of writing the second data to the memory cell to be detected, the second data is simultaneously written to the multiple memory cells coupled to the multiple bit lines and the word lines.
9. The detection method according to claim 8, characterized in that, The memory contains multiple memory blocks, each containing a memory cell to be detected; the word line that is selected and coupled to the memory cell to be detected includes: Simultaneously select word lines on multiple memory blocks that are coupled to the memory cell to be detected.
10. A memory detection apparatus for performing the detection method according to any one of claims 1-9, characterized in that, include: The write module is configured to write data to the memory cell to be detected via a sensitive amplifier; The control module is configured to control the amplification duration of the sensitive amplifier; The reading module is configured to read the data stored in the storage unit and determine whether the storage unit is abnormal based on the read data.
11. The detection device according to claim 10, characterized in that, The control module includes: The timing control module is configured to shorten the amplification duration of the sensitive amplifier.
12. The detection device according to claim 11, characterized in that, The timing control module includes: The delay module is configured to delay the activation of the amplification function of the sensitive amplifier.
13. The detection device according to claim 11, characterized in that, The timing control module includes: The shutdown module is configured to prematurely disable the amplification function of the sensitive amplifier.
14. A simulation detection method, characterized in that, The method includes: The process of writing the first data to the memory cell to be tested is simulated by controlling a sensitive amplifier; The process of writing second data, different from the first data, to the storage unit is simulated by controlling the sensitive amplifier. When writing the second data, the amplification time of the sensitive amplifier is shortened by adjusting the control signal of the sensitive amplifier. Read the data stored in the storage unit and determine whether the storage unit is abnormal based on the read data.
15. The method according to claim 14, characterized in that, The step of shortening the amplification duration of the sensitive amplifier by adjusting the control signal of the sensitive amplifier when writing the second data includes: After selecting the bit line of the memory cell, the amplification time of the sensitive amplifier is shortened by providing a delayed-on control signal.
16. The method according to claim 14, characterized in that, The step of shortening the amplification duration of the sensitive amplifier by adjusting the control signal of the sensitive amplifier when writing the second data includes: After selecting the bit line of the memory cell, the amplification duration of the sensitive amplifier is shortened by providing a control signal to turn it off in advance.