A PWM communication interface circuit

Abstract

The application discloses a PWM communication interface circuit, which is used for reducing the manufacturing cost of the communication interface circuit. The application comprises a host computer, a PWM bus, an interface circuit, a ground wire, a PWM_IN signal line, a PWM_OUT signal line and a lower computer. The interface circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a system power supply VS and a triode Q1. The host computer is connected with the PWM bus and the ground wire respectively. The resistor R1 is connected with the PWM bus and the system power supply VS respectively. The resistor R2 is connected with the PWM bus and the PWM_IN signal line respectively. The resistor R3 is connected with the ground wire and the PWM_IN signal line respectively. The resistor R4 is connected with the PWM_OUT signal line and the base of the triode Q1 respectively. The collector of the triode Q1 is connected with the PWM bus, and the emitter is connected with the ground wire. The lower computer is connected with the PWM_IN signal line, the PWM_OUT signal line and the ground wire respectively.

Description

Technical Field

[0001] This application relates to the field of circuit communication technology, and in particular to a PWM communication interface circuit. Background Technology

[0002] In existing technologies, PWM communication is widely used in products such as pumps and generators. Common PWM communication interface circuits are simplex and half-duplex communication interface circuits. In simplex transmission mode, communication is unidirectional; in half-duplex transmission mode, communication is bidirectional, and two connected devices can interchange the communication channel.

[0003] In simplex transmission mode, communication between the sender and receiver occurs only in one direction. The sender can only send data, and the receiver can only receive data; the receiver cannot reply to the sender. Simplex transmission can be considered a one-way road where signals are transmitted only in one direction—information from the opposite direction is not allowed to pass. Taking the relationship between a keyboard and a monitor as an example, the keyboard can only send input to the monitor, and the monitor can only receive input and display it on the screen. The monitor cannot reply to or send any feedback to the keyboard. In half-duplex mode, communication between the sender and receiver occurs bidirectionally on the bus, but only one can do so at a time. Both the sender and receiver can send and receive information, but only one is allowed to send and the other to receive at any given time. Although half-duplex communication only allows time-division multiplexing of information, as long as the frequency of the send and receive switching is fast enough, it can meet the communication requirements of most control systems.

[0004] Whether it's simplex or full-duplex communication, an interface circuit is needed to convert the signals on the bus into signals that the control chip can recognize. Existing half-duplex communication interface circuits are often quite complex and require the use of many high-precision components, which greatly increases production costs. Summary of the Invention

[0005] This application discloses a PWM communication interface circuit for reducing the manufacturing cost of communication interface circuits.

[0006] The first aspect of this application provides a PWM communication interface circuit, including:

[0007] The host computer, PWM bus, interface circuit, ground wire, PWM_IN signal line, PWM_OUT signal line, and slave computer;

[0008] The interface circuit is located between the host computer and the slave computer, and is connected through the PWM bus, ground wire, PWM_IN signal line, and PWM_OUT signal line.

[0009] The interface circuit includes resistors R1, R2, R3, and R4, the system power supply VS, and transistor Q1;

[0010] The output of the host computer is connected to the PWM bus;

[0011] The grounding terminal of the host computer is connected to the ground wire;

[0012] Resistor R1 is a pull-up resistor, and the first end of the pull-up resistor R1 is connected to the PWM bus;

[0013] The second terminal of the pull-up resistor R1 is connected to the system power supply VS;

[0014] Resistor R2 is a voltage divider resistor, and the first end of the voltage divider resistor R2 is connected to the PWM bus;

[0015] The second terminal of the voltage divider resistor R2 is connected to the PWM_IN signal line;

[0016] Resistor R3 is a voltage divider resistor, and the first end of the voltage divider resistor R3 is connected to the PWM_IN signal line;

[0017] The second terminal of the voltage divider resistor R3 is connected to the ground wire;

[0018] The first terminal of resistor R4 is connected to the PWM_OUT signal line;

[0019] The second terminal of resistor R4 is connected to the base of transistor Q1;

[0020] The collector of transistor Q1 is connected to the PWM bus;

[0021] The emitter of transistor Q1 is connected to ground;

[0022] The PWM signal capture interface of the lower-level machine is connected to the PWM_IN signal line;

[0023] The PWM signal sending interface of the lower-level machine is connected to the PWM_OUT signal line;

[0024] The grounding port of the lower-level machine is connected to the ground wire.

[0025] Optionally, the resistance of the voltage divider resistor R2 is greater than that of the pull-up resistor;

[0026] The resistance of the voltage divider resistor R3 is greater than that of the pull-up resistor R1.

[0027] Optionally, the core processor of the lower-level machine is an MCU chip or an FPGA chip;

[0028] When the core processor of the lower-level machine is an MCU chip, the resistance ratio of the pull-up resistor R1, the voltage divider resistor R2, and the voltage divider resistor R3 must satisfy R3 / (R1+R2+R3)≥VIH / VSMIN, where VIH is the threshold value for the digital signal level of the MCU chip to be high, and VSMIN is the minimum operating voltage of the PWM communication interface circuit to maintain system operation.

[0029] Optionally, the interface circuit may also include a Zener diode D2;

[0030] The first terminal of the Zener diode D2 is connected to the PWM_IN signal line;

[0031] The second terminal of the Zener diode D2 is connected to ground.

[0032] Optionally, the clamping voltage of Zener diode D2 can be matched to the high level of the digital signal of the MCU.

[0033] Optionally, the interface circuit may also include a TVS device D1;

[0034] The first terminal of TVS device D1 is connected to the PWM bus;

[0035] The second terminal of TVS device D1 is connected to ground.

[0036] Optionally, the host computer can be an automotive ECM or a PC, and the output of the host computer can be set to an open-drain structure.

[0037] Optionally, the open-drain structure of the host computer's output terminal is MOSFET M1;

[0038] The drain of MOSFET M1 is connected to the PWM bus;

[0039] The source of MOSFET M1 is connected to ground.

[0040] Optionally, the interface circuit may also include a filter capacitor C1;

[0041] The first terminal of the filter capacitor C1 is connected to the PWM bus;

[0042] The second terminal of the filter capacitor C1 is connected to the ground wire;

[0043] Optionally, the interface circuit may also include a filter capacitor C2;

[0044] The first terminal of the filter capacitor C2 is connected to the PWM_IN signal line;

[0045] The second terminal of the filter capacitor C2 is connected to the ground wire.

[0046] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:

[0047] In this application, the PWM communication interface circuit specifically includes a host computer, a PWM bus, an interface circuit, a ground wire, a PWM_IN signal line, a PWM_OUT signal line, and a slave computer. The interface circuit includes resistors R1, R2, R3, and R4, a system power supply VS, and a transistor Q1. The host computer is connected to the PWM bus and the ground wire. Resistor R1 is connected to the PWM bus and the system power supply VS. Resistor R2 is connected to the PWM bus and the PWM_IN signal line. Resistor R3 is connected to the ground wire and the PWM_IN signal line. Resistor R4 is connected to the PWM_OUT signal line and the base of transistor Q1. The collector of transistor Q1 is connected to the PWM bus, and the emitter is connected to the ground wire. The slave computer is connected to the PWM_IN signal line, the PWM_OUT signal line, and the ground wire. When the host computer transmits signals to the slave computer, the PWM_OUT signal line must be set to a low level. When MOSFET M1 in the host computer is turned on, the potential of the PWM bus is pulled low to ground. When MOSFET M1 is turned off, the potential of the PWM bus is pulled high to VS through pull-up resistor R1, thus generating a PWM signal on the PWM bus with a low level of 0 and a high level of VS. The host computer controls the level state on the PWM bus by controlling the on and off states of MOSFET M1 to send PWM signal commands. After the PWM bus signal is divided by voltage divider resistors R2 and R3, it is stepped down to the input signal PWM_IN that can be read by the lower-level machine interface. The PWM_IN signal is in phase with the PWM bus signal. The lower-level machine obtains the commands from the host computer by parsing the PWM_IN signal. When the lower-level machine transmits signals to the host computer, the PWM_OUT signal line is set to a high level. Pull-down transistor Q1 is turned on, and the PWM bus is pulled low. The lower-level machine pulls the PWM bus signal low and transmits the signal to the host computer. The aforementioned signal transmission process, coupled with a corresponding communication protocol, allows the host computer and the slave computer to capture each other's signals in a time-division manner, achieving half-duplex communication. Furthermore, the components and connections of the entire half-duplex communication interface circuit are simple, significantly reducing production costs. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of a design circuit based on a half-duplex communication bus in this application;

[0050] Figure 2This is a schematic diagram of the PWM communication interface circuit in this application;

[0051] Figure 3 This is a schematic diagram of the operating sequence of the PWM_OUT signal line in the PWM communication interface circuit of this application.

[0052] Figure 4 This is a schematic diagram of the PWM bus operation sequence in the PWM communication interface circuit of this application;

[0053] Figure 5 This is a schematic diagram of the PWM_IN signal line operation sequence in the PWM communication interface circuit of this application. Detailed Implementation

[0054] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0055] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0056] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0057] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0058] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0059] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0060] In existing technologies, PWM communication is widely used in products such as pumps and generators. Common PWM communication interface circuits are simplex and half-duplex communication interface circuits. In simplex transmission mode, communication is unidirectional; in half-duplex transmission mode, communication is bidirectional, and two connected devices can interchange the communication channel.

[0061] In simplex transmission mode, communication between the sender and receiver occurs only in one direction. The sender can only send data, and the receiver can only receive data; the receiver cannot reply to the sender. Simplex transmission can be considered a one-way road where signals are transmitted only in one direction—information from the opposite direction is not allowed to pass. Taking the relationship between a keyboard and a monitor as an example, the keyboard can only send input to the monitor, and the monitor can only receive input and display it on the screen. The monitor cannot reply to or send any feedback to the keyboard. In half-duplex mode, communication between the sender and receiver occurs bidirectionally on the bus, but only one can do so at a time. Both the sender and receiver can send and receive information, but only one is allowed to send and the other to receive at any given time. Although half-duplex communication only allows time-division multiplexing of information, as long as the frequency of the send and receive switching is fast enough, it can meet the communication requirements of most control systems.

[0062] Please refer to Figure 1 , Figure 1 This is an example circuit diagram of a conventional half-duplex communication bus design. The state detection circuit 101 includes a NOT gate U2, a first switch K1, and a second switch K2. The input of NOT gate U2 is connected to the controlled terminal of the first switch K1, and the output of NOT gate U2 is connected to the controlled terminal of the second switch K2. The inputs of the first switch K1 and the second switch K2 are connected to the main control circuit 103, and the outputs of the first switch K1 and the second switch K2 are connected to the half-duplex communication bus 20.

[0063] The half-duplex communication interface circuit is quite complex and requires the use of many high-precision components, which greatly increases production costs.

[0064] Based on this, this application discloses a PWM communication interface circuit to reduce the manufacturing cost of the communication interface circuit.

[0065] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0066] Please see Figure 2 , Figure 3 , Figure 4 and Figure 5 This application provides an embodiment of a PWM communication interface circuit, comprising:

[0067] The host computer, PWM bus, interface circuit, ground wire, PWM_IN signal line, PWM_OUT signal line, and slave computer;

[0068] The interface circuit is located between the host computer and the slave computer, and is connected through the PWM bus, ground wire, PWM_IN signal line, and PWM_OUT signal line.

[0069] The interface circuit includes resistors R1, R2, R3, and R4, the system power supply VS, and transistor Q1;

[0070] The output of the host computer is connected to the PWM bus;

[0071] The grounding terminal of the host computer is connected to the ground wire;

[0072] Resistor R1 is a pull-up resistor, and the first end of the pull-up resistor R1 is connected to the PWM bus;

[0073] The second terminal of the pull-up resistor R1 is connected to the system power supply VS;

[0074] Resistor R2 is a voltage divider resistor, and the first end of the voltage divider resistor R2 is connected to the PWM bus;

[0075] The second terminal of the voltage divider resistor R2 is connected to the PWM_IN signal line;

[0076] Resistor R3 is a voltage divider resistor, and the first end of the voltage divider resistor R3 is connected to the PWM_IN signal line;

[0077] The second terminal of the voltage divider resistor R3 is connected to the ground wire;

[0078] The first terminal of resistor R4 is connected to the PWM_OUT signal line;

[0079] The second terminal of resistor R4 is connected to the base of transistor Q1;

[0080] The collector of transistor Q1 is connected to the PWM bus;

[0081] The emitter of transistor Q1 is connected to ground;

[0082] The PWM signal capture interface of the lower-level machine is connected to the PWM_IN signal line;

[0083] The PWM signal sending interface of the lower-level machine is connected to the PWM_OUT signal line;

[0084] The grounding port of the lower-level machine is connected to the ground wire.

[0085] In this embodiment, the PWM bus is the signal bus for PWM communication, and the signals on it have the characteristic of bidirectional time-division transmission.

[0086] The PWM_IN signal is the PWM communication signal received by the lower-level machine. Its phase is the same as that of the PWM bus mentioned above, and it has unidirectional transmission characteristics, but it is only used to be read by the lower-level machine. The PWM_OUT signal is the PWM communication signal sent by the lower-level machine, and it has unidirectional transmission characteristics. In this embodiment, it is sent by the lower-level machine.

[0087] The host computer is the PWM communication command sending and receiving unit, such as an automotive ECM or a PC. In this embodiment, the host computer is characterized by its output port having an open-drain structure. Please refer to [reference needed]. Figure 2 , attached Figure 2 The open-drain structure of the upper-level computer's output interface is composed of MOSFET M1. The lower-level computer is the controlled unit, whose core processor is an MCU chip or FPGA chip, etc. The lower-level computer is characterized by having a PWM signal capture and transmission interface.

[0088] Interface circuit: Located between the host computer and the slave computer, it converts the signals on the PWM bus sent by the host computer into PWM_IN signals that can be read by the slave MCU; it can also convert the PWM_OUT signals sent by the slave computer onto the PWM bus for the host computer to read. The interface circuit connects and transmits signals through the PWM bus, ground wire, PWM_IN signal line, and PWM_OUT signal line.

[0089] In this embodiment, R1 is a pull-up resistor. The pull-up resistor R1 is located between the PWM bus and the system power supply VS, and is used to pull the PWM bus level high to the logic "high level" for the host computer to recognize.

[0090] R2 and R3 are bus voltage divider resistors. Furthermore, the voltage divider resistors R2 and R3 are connected in series and located between the PWM bus and the ground line to divide the PWM bus voltage to adapt to the working voltage of the lower-level machine interface.

[0091] In this embodiment, Q1 is a bus pull-down transistor. Please refer to [reference needed]. Figure 2 The transistor used in the figure is an NPN type. Its collector is connected to the PWM bus, its emitter is connected to ground, and its base is connected to the base resistor. The function of the bus pull-down transistor Q1 is to feed back the signal sent by the lower computer to the PWM bus.

[0092] R4 is the base resistor of the transistor, located between the base of the pull-down transistor Q1 and the PWM_OUT bus, which limits the base current.

[0093] Optionally, the resistance of the voltage divider resistor R2 is greater than that of the pull-up resistor;

[0094] The resistance of the voltage divider resistor R3 is greater than that of the pull-up resistor R1.

[0095] Optionally, the core processor of the lower-level machine is an MCU chip or an FPGA chip;

[0096] When the core processor of the lower-level machine is an MCU chip, the resistance ratio of the pull-up resistor R1, the voltage divider resistor R2, and the voltage divider resistor R3 must satisfy R3 / (R1+R2+R3)≥VIH / VSMIN, where VIH is the threshold value for the digital signal level of the MCU chip to be high, and VSMIN is the minimum operating voltage of the PWM communication interface circuit to maintain system operation.

[0097] Optionally, the interface circuit may also include a Zener diode D2;

[0098] The first terminal of the Zener diode D2 is connected to the PWM_IN signal line;

[0099] The second terminal of the Zener diode D2 is connected to ground.

[0100] In this embodiment, D2 is a Zener diode, which is located between the PWM_IN signal and the ground line. The function of the Zener diode D2 is to prevent voltage pulses on the PWM bus from damaging the lower-level MCU.

[0101] Optionally, the clamping voltage of Zener diode D2 can be matched to the high level of the digital signal of the MCU.

[0102] Optionally, the interface circuit may also include a TVS device D1;

[0103] The first terminal of TVS device D1 is connected to the PWM bus;

[0104] The second terminal of TVS device D1 is connected to ground.

[0105] In this embodiment, D1 is a TVS device. The TVS device D1 is located between the PWM bus and the ground line. Its function is to provide ESD protection for the entire interface circuit and protect the downstream components.

[0106] Optionally, the host computer can be an automotive ECM or a PC, and the output of the host computer can be set to an open-drain structure.

[0107] Optionally, the open-drain structure of the host computer's output terminal is MOSFET M1;

[0108] The drain of MOSFET M1 is connected to the PWM bus;

[0109] The source of MOSFET M1 is connected to ground.

[0110] Optionally, the interface circuit may also include a filter capacitor C1;

[0111] The first terminal of the filter capacitor C1 is connected to the PWM bus;

[0112] The second terminal of the filter capacitor C1 is connected to the ground wire;

[0113] Optionally, the interface circuit may also include a filter capacitor C2;

[0114] The first terminal of the filter capacitor C2 is connected to the PWM_IN signal line;

[0115] The second terminal of the filter capacitor C2 is connected to the ground wire.

[0116] In this embodiment, C1 is a filter capacitor. The filter capacitor C1 is located between the PWM bus and the ground line and is used to filter high-frequency interference signals on the PWM bus.

[0117] C2 is also a filter capacitor, located between the PWM_IN signal and the ground line. Its function is to filter high-frequency interference signals on the PWM_IN signal line.

[0118] Combination Figure 2 , Figure 3 , Figure 4 and Figure 5 The following is an explanation. An example is provided below. In this embodiment, a 12V system is used, with the lower-level device being an MCU chip operating at 5V.

[0119] The normal operating voltage range required for a typical 12V system is generally 9-16V. Based on this, in this PWM communication interface circuit, the operating voltage of TVS device D1 and filter capacitor C1 must be greater than 16V, and the breakdown voltage of TVS device D1 should also be less than the breakdown voltage of bus pull-down transistor Q1.

[0120] Furthermore, in this embodiment, the resistance value of the bus pull-up resistor R1 is typically set to 1–10kΩ. The ratio of the resistance values ​​of the voltage divider resistors R2 and R3 should satisfy R3 / (R1+R2+R3)≥V IH / VS MIN , where V IH The threshold for determining a high digital signal level in the MCU, VS MIN This is the minimum operating voltage of the system. For this system, if V... IH For 3V, VS MIN If the voltage is 9V, then R3 / (R1+R2+R3)≥1 / 3.

[0121] In this embodiment, the clamping voltage of Zener diode D2 should be lower than the breakdown voltage of the MCU's I / O port. For example, if the breakdown voltage of the MCU's I / O port is 6V, then the clamping voltage of D2 should be lower than 6V.

[0122] Meanwhile, the Zener diode D2 should be in normal operating condition and should not be in a breakdown state for an extended period. Specifically, the clamping voltage of the Zener diode D2 should be higher than VS. MAX *R3 / (R1+R2+R3), where VS MAX This represents the maximum value of the system operating voltage. For example: when VS MAX If *R3 / (R1+R2+R3)>6V, then the resistance values ​​of voltage divider resistors R2 and R3 should be adjusted.

[0123] When the host computer transmits signals to the slave computer, PWM_OUT must be set to low level, that is... Figure 3 In stage T2 of the PWM signal, when M1 in the host computer is on, the PWM bus potential is pulled low to ground; when M1 is off, the PWM bus potential is pulled high to VS through pull-up resistor R1. This generates a PWM signal on the PWM bus with a low level of 0 and a high level of VS. The host computer controls the level state on the PWM bus by controlling the on and off states of M1 to send PWM signal commands. The period of the PWM signal sent by the host computer is T3. After the PWM bus signal is divided by voltage divider resistors R2 and R3, it is stepped down to the input signal PWM_IN, which can be read by the MCU interface. The PWM_IN signal is in phase with the PWM bus signal. The MCU chip obtains the host computer's commands by parsing the PWM_IN signal. Zener diode D2 acts as a clamp when the VS voltage is high, ensuring that the amplitude of the high-level PWM_IN does not exceed the normal operating range of the MCU.

[0124] When the lower-level machine transmits signals to the upper-level machine, PWM_OUT is set to high level, that is... Figure 3In the T1 stage, pull-down transistor Q1 is turned on, pulling the PWM bus low. The lower-level computer pulls the PWM bus signal low for a duration T1 and a period T3, transmitting the signal to the upper-level computer. Typically, the period T3 of the PWM_OUT signal should be much longer than the period T4 of the PWM bus signal, such as T3 being 1 second and T4 being 10 ms.

[0125] The above signal transmission process, supplemented by the corresponding communication protocol, allows the host computer and the slave computer to capture each other's signals in a time-division manner, thus realizing half-duplex communication.

[0126] In this application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and other terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only used to describe the relative positional relationship between the components or parts and do not specifically limit the specific installation orientation of each component or part.

[0127] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0128] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0129] Furthermore, the structures, proportions, sizes, etc., drawn in the accompanying drawings of this application are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modification to the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.

Claims

1. A PWM communication interface circuit, characterized in that, include: The host computer, PWM bus, interface circuit, ground wire, PWM_IN signal line, PWM_OUT signal line, and slave computer; The interface circuit is located between the host computer and the slave computer, and is connected through the PWM bus, ground wire, PWM_IN signal line, and PWM_OUT signal line; The interface circuit includes resistors R1, R2, R3, and R4, a system power supply VS, and transistor Q1; The output terminal of the host computer is connected to the PWM bus; The grounding terminal of the host computer is connected to the ground wire; The resistor R1 is a pull-up resistor R1, and the first end of the pull-up resistor R1 is connected to the PWM bus; The second end of the pull-up resistor R1 is connected to the system power supply VS; The resistor R2 is a voltage divider resistor R2, and the first end of the voltage divider resistor R2 is connected to the PWM bus; The second end of the voltage divider resistor R2 is connected to the PWM_IN signal line; The resistor R3 is a voltage divider resistor R3, and the first end of the voltage divider resistor R3 is connected to the PWM_IN signal line; The second end of the voltage divider resistor R3 is connected to the ground wire; The first end of the resistor R4 is connected to the PWM_OUT signal line; The second end of the resistor R4 is connected to the base of the transistor Q1; The collector of transistor Q1 is connected to the PWM bus; The emitter of the transistor Q1 is connected to the ground wire; The PWM signal capture interface of the lower-level machine is connected to the PWM_IN signal line; The PWM signal sending interface of the lower-level machine is connected to the PWM_OUT signal line; The grounding port of the lower-level machine is connected to the ground wire.

2. The PWM communication interface circuit according to claim 1, characterized in that, The resistance value of the voltage divider resistor R2 is greater than that of the pull-up resistor; The resistance of the voltage divider resistor R3 is greater than that of the pull-up resistor R1.

3. The PWM communication interface circuit according to claim 2, characterized in that, The core processor of the lower-level machine is an MCU chip or an FPGA chip; When the core processor of the lower-level machine is an MCU chip, the resistance ratio of the pull-up resistor R1, the voltage divider resistor R2, and the voltage divider resistor R3 satisfies R3 / (R1+R2+R3)≥V IH / VS MIN V IH The threshold for determining a high digital signal level in an MCU chip, VS MIN The minimum operating voltage required to maintain the system operation of the PWM communication interface circuit.

4. The PWM communication interface circuit according to claim 3, characterized in that, The interface circuit also includes a Zener diode D2; The first terminal of the Zener diode D2 is connected to the PWM_IN signal line; The second terminal of the Zener diode D2 is connected to the ground wire.

5. The PWM communication interface circuit according to claim 4, characterized in that, The clamping voltage of the Zener diode D2 is matched with the high-level voltage of the digital signal of the MCU.

6. The PWM communication interface circuit according to any one of claims 1 to 5, characterized in that, The interface circuit also includes a TVS device D1; The first terminal of the TVS device D1 is connected to the PWM bus; The second terminal of the TVS device D1 is connected to the ground wire.

7. The PWM communication interface circuit according to any one of claims 1 to 5, characterized in that, The host computer is an automotive ECM or a PC, and the output terminal of the host computer is configured as an open-drain structure.

8. The PWM communication interface circuit according to claim 7, characterized in that, The open-drain structure of the output terminal of the host computer is MOSFET M1; The drain of the MOSFET M1 is connected to the PWM bus; The source of the MOSFET M1 is connected to ground.

9. The PWM communication interface circuit according to claim 1, characterized in that, The interface circuit also includes a filter capacitor C1; The first terminal of the filter capacitor C1 is connected to the PWM bus; The second terminal of the filter capacitor C1 is connected to the ground wire.

10. The PWM communication interface circuit according to claim 1, characterized in that, The interface circuit also includes a filter capacitor C2; The first terminal of the filter capacitor C2 is connected to the PWM_IN signal line; The second terminal of the filter capacitor C2 is connected to the ground wire.

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