Method of manufacturing a semiconductor device
By employing selective etching formulations and doping techniques, the problem of increased mask layer thickness in the covered area was solved, achieving both mask layer protection and effective removal of etching residues, thus ensuring the integrity and performance of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2022-03-18
- Publication Date
- 2026-06-02
AI Technical Summary
In existing etching processes, the increased thickness of the mask layer can prevent subsequent etching processes from effectively removing the mask, thus affecting the fabrication of semiconductor devices.
Selective etching formulations are used to dop different regions of the mask layer. For example, the first region of the mask layer is p-type doped and the etching residue is n-type doped. The stacked material is covered by a filler layer, and the etching residue and filler layer are removed by selective etching process, which protects the mask layer and controls the etching process.
It effectively removes etching residues, protects the mask layer and stacked materials, avoids excessive etching loss, and ensures the integrity and performance of semiconductor components.
Smart Images
Figure CN116490061B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing semiconductor devices. Background Technology
[0002] In modern semiconductor manufacturing, the fabrication of capacitor structures involves creating openings with high aspect ratios through etching. The etching process essentially involves forming a patterned mask over the stacked structure, and then etching the stacked structure according to the mask pattern. However, because some material removed during etching accumulates on top of the mask layer, increasing the thickness of the area covered by the mask, it becomes impossible to directly remove the mask using a conventional isotropic etching process.
[0003] Therefore, how to propose a method for manufacturing semiconductor devices that can solve the above problems is one of the issues that the industry is currently eager to address by investing research and development resources. Summary of the Invention
[0004] In view of this, one object of the present invention is to provide a method for manufacturing semiconductor devices that can effectively solve the above-mentioned problems.
[0005] The present invention relates to a method for fabricating a semiconductor device, comprising: forming a mask layer on a stacked structure, wherein the mask layer has a first region and a second region, the second region having a patterned structure; etching an opening in the stacked structure by means of the patterned structure, wherein etching residue is deposited on the first region; filling the opening with a filler layer; doping the first region of the mask layer; removing the etching residue and the filler layer by means of a selective etching process; and removing the mask layer.
[0006] In some current embodiments, the stacked structure includes an oxide layer and a nitride layer, and the step of etching openings in the stacked structure by patterning the structure exposes at least one surface of each of the oxide layer and the nitride layer.
[0007] In some current implementations, the step of filling the opening with the filler layer causes the filler layer to cover a second region of the masking layer.
[0008] In some current implementations, the step of filling the opening with the filler layer results in the filler layer and the etch residue having substantially the same height relative to the mask layer.
[0009] In some current embodiments, the step of doping the first region of the masking layer includes forming a p-type dopant in the first region.
[0010] In some current embodiments, a first etching formulation is used in the step of removing etching residues and filler layers by a selective etching process, and the p-type dopant is adapted to resist etching by the first etching formulation.
[0011] In some current embodiments, the first etching formulation includes at least one of HBr, He, and O2.
[0012] In some current embodiments, the method of fabricating a semiconductor device further includes doping the etching residue before the step of removing the etching residue and the filler layer by means of a selective etching process.
[0013] In some current implementations, the step of doping the etching residue includes forming an n-type dopant in the etching residue.
[0014] In some current implementations, the step of removing the mask layer uses a second etching formula, and the second etching formula is different from the first etching formula.
[0015] In summary, in the method for fabricating a semiconductor device according to the present invention, a selective etching formulation is used in conjunction with different types of doping for appropriate regions (e.g., p-type doping of the first region of the mask layer and n-type doping of the etch residue) to more completely remove the etch residue and protect the mask layer, as well as the portion of the mask layer and stacked material covered by the etch residue, avoiding losses caused by over-etching. Furthermore, the first etching formulation does not etch p-type etchants, further strengthening the protective power of the doped mask layer, and the first etching formulation has a significant etching rate for n-type etchants, also increasing the rate of etch residue removal. In addition, by filling a fill layer and covering the stacked material, other portions of the stacked material not covered by etch residue are protected while removing the etch residue. Because of the aforementioned selective etching to remove etch residue and the fill layer, the subsequent non-selective etching to remove the mask layer can be better controlled, avoiding over-etching and damage to the stacked structure. Attached Figure Description
[0016] The best understanding of the invention can be obtained by reading it in conjunction with the accompanying drawings, as described in the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.
[0017] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present invention.
[0018] Figure 2A A cross-sectional schematic diagram illustrating one stage of a method for creating a semiconductor device according to some embodiments of the present invention.
[0019] Figure 2B A cross-sectional schematic diagram illustrating one stage of a method for creating a semiconductor device according to some embodiments of the present invention.
[0020] Figure 2CA cross-sectional schematic diagram illustrating one stage of a method for creating a semiconductor device according to some embodiments of the present invention.
[0021] Figure 2D A cross-sectional schematic diagram illustrating one stage of a method for creating a semiconductor device according to some embodiments of the present invention.
[0022] Figure 2E A cross-sectional schematic diagram illustrating one stage of a method for creating a semiconductor device according to some embodiments of the present invention.
[0023] Figure 2F A cross-sectional schematic diagram illustrating one stage of a method for creating a semiconductor device according to some embodiments of the present invention.
[0024] Figure 2G A cross-sectional schematic diagram illustrating one stage of a method for creating a semiconductor device according to some embodiments of the present invention.
[0025] Figure 2H A cross-sectional schematic diagram illustrating one stage of a method for creating a semiconductor device according to some embodiments of the present invention. Detailed Implementation
[0026] The following description provides numerous different embodiments or instances of various features for implementing the provided objectives. Specific examples of components and arrangements are described below to simplify the invention. These are, of course, merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.
[0027] Additionally, for simplicity, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another (other) element or feature, as shown in the figures. These spatial relative terms are intended to cover different orientations of elements in use or operation, in addition to those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein shall be interpreted accordingly.
[0028] As used herein, “approximately,” “about,” “close to,” or “substantially” generally means falling within twenty percent, or ten percent, or five percent of a given value or range. The numerical values given herein are approximate, and the terms used, such as “approximately,” “about,” “close to,” or “substantially,” can be inferred unless explicitly stated otherwise.
[0029] Figure 1 A flowchart illustrating a method M1 for fabricating a semiconductor device according to some embodiments of the present invention. Please refer to... Figure 1 A method M1 for fabricating a semiconductor device includes: forming a mask layer on a stacked structure, wherein the mask layer has a first region and a second region, the second region having a patterned structure (step S101); etching an opening in the stacked structure through the patterned structure, wherein etching residue is deposited on the first region (step S102); filling the opening with a filler layer (step S103); doping the first region of the mask layer (step S104); removing the etching residue and the filler layer by a selective etching process (step S105); and removing the mask layer (step S106). Details of each step will be described below.
[0030] Figure 2A This is a schematic cross-sectional view illustrating one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present invention. Please refer to... Figure 1 as well as Figure 2A In some embodiments, the stacked structure 110 includes an oxide layer 112 and a nitride layer 114, with the nitride layer 114 formed over the oxide layer 112; however, the invention is not limited thereto. The stacked structure 110 can be composed of multiple layers or different materials as needed. In step S101, a masking layer 120 is formed on the stacked structure 110 and completely covers the top surface of the stacked structure 110. Specifically, in Figure 2A In one embodiment, the masking layer 120 completely covers the top surface of the nitride layer 114. However, the masking layer 120 may also cover only a portion of the top surface of the stacked structure 110 as needed.
[0031] Figure 2B This is a schematic cross-sectional view of one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present invention. Figure 2B In the illustrated embodiment, the mask layer 120 has a first region 120a and a second region 120b, and the second region 120b has a patterned structure. Specifically, when the mask layer 120... Figure 2AAfter being formed on the stacked structure 110, a patterned structure can be formed in a portion of the masking layer 120 (e.g., the second region 120b). The distribution area of the first region 120a and the second region 120b on the masking layer 120 is not limited and can be adjusted as needed. In some embodiments, the patterned structure of the second region 120b will serve as the basis for shaping the underlying stacked structure 110 in subsequent steps.
[0032] Figure 2C This is a schematic cross-sectional view illustrating one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present invention. Please refer to... Figure 1 as well as Figure 2C In step S102, openings 140 are etched into the stacked structure 110, with etching residue 130 deposited on the first region 120a. The stacked structure 110 forms a plurality of openings 140 at patterned structures corresponding to the second region 120b of the masking layer 120. In some embodiments, step S102 exposes at least one surface of each of the oxide layer 112 and the nitride layer 114 through the openings 140, but this is not a limitation of the invention. Specifically, the inner walls of these openings 140 expose a portion of the surfaces of the oxide layer 112 and the nitride layer 114. However, the openings 140 may also expose only a portion of a specific layer in the stacked structure 110 (e.g., the opening 140 may expose only a portion of the surface of the nitride layer 114), and the location of the exposed portion depends on the design requirements of the stacked structure 110. In other embodiments, multiple other layers constituting the stacked structure 110 may be exposed through the openings 140. Figure 2C In step S102, after the etching process is performed, etching residue 130 is generated and deposited on the first region 120a. The etching residue 130 is formed from the portion of the stacked structure 110 that is removed during the etching process. After leaving the opening 140, the removed material is accumulated on the first region 120a and completely or partially covers the first region 120a of the mask layer 120.
[0033] Figure 2D This is a schematic cross-sectional view illustrating one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present invention. Please refer to... Figure 1 as well as Figure 2DIn step S103, the filler layer 150 is filled into the opening 140. In some embodiments, step S103 causes the filler layer 150 to cover the second region 120b of the mask layer 120. Specifically, the filler layer 150 will completely cover the second region 120b of the mask layer 120, but the invention is not limited thereto. In other embodiments, the filler layer 150 may only cover a portion of the second region 120b. Furthermore, in some embodiments, step S103 causes the filler layer 150 and the etch residue 130 to have substantially the same height relative to the mask layer 120. Specifically, the purpose of the filler layer 150 is to make the first region 120a covered by the etch residue 130 of the mask layer 120 flush with the second region 120b, because the filler layer 150 can protect the stacked structure 110 it covers in subsequent steps. In the subsequent step of removing the etch residue 130, the fill layer 150 can minimize the loss of the portion of the mask layer 120 not covered by the etch residue 130 (e.g., the second region 120b) during the removal step.
[0034] Figure 2E This is a schematic cross-sectional view illustrating one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present invention. Please refer to... Figure 1 as well as Figure 2E In step S104, the first region 120a of the masking layer 120 is doped, forming a doped region 122. In some embodiments, step S104 includes forming a p-type dopant in the first region 120a. Specifically, step S104 can be performed by an ion implantation process, but other suitable methods can be used to dope the first region 120a. Ion implantation drives the dopant into a specific depth in the material (e.g., the first region 120a of the masking layer 120 covered by the etch residue 130), thereby doping a region at a specific depth in the material. Any Group III material (e.g., boron, aluminum, gallium, indium, etc.) can be used in ion implantation to form the p-type dopant.
[0035] Figure 2F This is a schematic cross-sectional view illustrating one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present invention. Please refer to... Figure 1 as well as Figure 2FIn step S105, a selective etching process is performed to remove the etching residue 130 and the filler layer 150. In some embodiments, step S105 uses a first etching formulation, and the p-type dopant is adapted to resist etching by the first etching formulation. Further, the first etching formulation includes at least one of HBr, He, and O2. Specifically, the first etching formulation is selective for the etching material and does not etch the p-type dopant; therefore, the stacked structure 110 covered by the doped region 122 will not be damaged by the etching process in step S105. Step S105 removes the etching residue 130 and the filler layer 150, exposing the opening 140 and the first region 120a and the second region 120b of the masking layer 120.
[0036] In some other embodiments, method M1 further includes doping the etching residue 130 prior to step S105. More specifically, the step of doping the etching residue 130 includes forming an n-type dopant in the etching residue 130. Continuing with the first etching formulation described in the preceding paragraph, which includes at least one of HBr, He, and O2, it is particularly suitable for etching n-type dopant. Generally, the etching residue 130 can be doped using an ion implantation process; however, other suitable methods may also be used. Doping the etching residue 130 prior to performing step S105 can further improve the efficiency of removing the etching residue 130 because removing the doped etching residue 130 using the first etching formulation, which has high selectivity for n-type dopant, will increase the etching rate of the etching residue 130.
[0037] Figure 2G This is a schematic cross-sectional view illustrating one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present invention. Please refer to... Figure 1 as well as Figure 2G After removing the etch residue 130 and the filler layer 150, the oxide layer 112 and the nitride layer 114 exposed on the inner wall of the mask layer 120 and the opening 140 are exposed again. In step S106, the mask layer 120 is removed. In some embodiments, step S106 uses a second etching formulation, and the second etching formulation is different from the first etching formulation. Specifically, step S106 is performed using a non-selective etching process. The second etching formulation is not selective for the etching material, and therefore will uniformly remove all portions of the mask layer 120 (e.g., the first region 120a and the second region 120b). Since the etch residue 130 is removed in the aforementioned steps, step S106 can better control the etching process to avoid etch removal or damage to the stacked structure 110.
[0038] Figure 2HA cross-sectional schematic diagram of one stage of a method M1 for creating a semiconductor device according to some embodiments of the present invention. Figure 2H The diagram illustrates a stacked structure 110 with an opening 140. Steps S101 to S106 described above can further reduce the impact of removing the masking layer 120 (see reference). Figures 2A to 2G This results in wear and tear on the stack structure 110, in order to preserve the stack structure 110 more completely and not affect the expected performance of the stack structure 110.
[0039] From the detailed description of the specific embodiments of the present invention above, it is evident that in the method for fabricating semiconductor devices according to the present invention, selective etching formulations are used in conjunction with different types of doping for appropriate regions (e.g., p-type doping of the first region of the mask layer and n-type doping of the etching residue) to more completely remove the etching residue and protect the mask layer, as well as the portion of the mask layer and stacked material covered by the etching residue, avoiding losses caused by over-etching. Furthermore, the first etching formulation does not etch p-type etchants, further strengthening the protective power of the doped mask layer, and the first etching formulation has a significant etching rate for n-type etchants, also increasing the rate of removing etching residue. In addition, by filling a fill layer and covering the stacked material, other portions of the stacked material not covered by etching residue are protected while removing the etching residue. Because of the aforementioned selective etching to remove etching residue and the fill layer, the subsequent non-selective etching to remove the mask layer can be better controlled, avoiding over-etching and damage to the stacked structure.
[0040] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of the invention. Those skilled in the art will understand that they can readily use this invention as the basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention.
[0041] [Symbol Explanation]
[0042] 110: Stacked structure
[0043] 112: Oxide layer
[0044] 114: Nitrided layer
[0045] 120: Masking layer
[0046] 120a: First Zone
[0047] 120b: Second Zone
[0048] 122: Doped region
[0049] 130: Etching Residue
[0050] 140: Opening
[0051] 150: Fill layer
[0052] M1: Method
[0053] S101, S102, S103, S104, S105, S106: Steps.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A mask layer is formed on a stacked structure, wherein the mask layer has a first region and a second region, the second region having a patterned structure; Multiple openings are etched into the stacked structure through the patterned structure, wherein etching residue accumulates on the first region; The filling layer is filled into the openings, wherein the step of filling the filling layer into the openings causes the filling layer to cover the second region of the masking layer; The first region of the masking layer is doped; The etching residue and the filler layer are removed by a selective etching process; as well as Remove the mask layer.
2. The method of fabricating a semiconductor device according to claim 1, wherein the stacked structure comprises an oxide layer and a nitride layer, and the step of etching the openings in the stacked structure by means of the patterned structure exposes at least one surface of each of the oxide layer and the nitride layer.
3. The method of fabricating a semiconductor element according to claim 1, wherein the step of filling the fill layer in the openings results in the fill layer and the etch residue having substantially the same height relative to the mask layer.
4. The method of fabricating a semiconductor device according to claim 1, wherein the step of doping the first region of the masking layer includes forming a p-type dopant in the first region.
5. The method of fabricating a semiconductor device according to claim 4, wherein the step of removing the etch residue and the filler layer by means of the selective etching process uses a first etch formulation, and the p-type dopant is adapted to resist etching by the first etch formulation.
6. The method of fabricating a semiconductor device according to claim 5, wherein the first etching formulation comprises at least one of HBr, He, and O2.
7. The method of fabricating a semiconductor device according to claim 1, further comprising, prior to the step of removing the etching residue and the filler layer by means of the selective etching process, doping the etching residue.
8. The method of fabricating a semiconductor device according to claim 7, wherein the step of doping the etch residue includes forming an n-type dopant in the etch residue.
9. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the etching residue and the filler layer by means of the selective etching process uses a first etching formula, the step of removing the mask layer uses a second etching formula, and the second etching formula is different from the first etching formula.