Parallel polar codes with shared data and cooperative decoding

Abstract

Systems, structures, and methods of encoding and decoding information transmitted over a communication channel are disclosed. The method includes partitioning the information among m parallel polar codes such that each of the m parallel polar codes includes a plurality of information bits, and partitioning the information bits in each of the m parallel polar codes into a private portion and a common portion. The common portion includes an information segment and a repetition segment, where the information bits of the common portion are arranged in the information segment. The bits in the information segment of the common portion of each of the m parallel polar codes are repeated in the repetition segment of the common portion of at least a second one of the m parallel polar codes.

Description

[0001] Cross Reference to Related Applications

[0002] This is the first filing related to the disclosed technology. At the time of filing, there are no related patents or applications. TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of encoding and decoding information for transmission over noisy media, and more particularly, to systems and methods for enhancing data transmission reliability using polar codes. BACKGROUND

[0004] In a data communication system, data is transmitted from a transmitter to a receiver over a channel. The transmitted data can be degraded due to noise in the channel, such that the received data can not be identical to the transmitted data. The implementation of the transmitter and receiver depends on the channel over which the data is to be transmitted, e.g., whether the channel is wireless, cable, or optical fiber.

[0005] Forward error correction codes (FEC) provide reliable communication in a one-way channel by enabling the receiver to detect and correct a limited number of errors. Two basic types of FEC are block FEC and convolutional FEC. In block FEC, data is split into blocks, each of which is independently encoded (i.e., independent of other blocks) before transmission. In convolutional FEC, the encoded data depends on both the current data and the previous data in the digital communication scheme.

[0006] FEC is extremely important in data transmission systems. For example, in high-throughput optical transmission systems, it is not uncommon for forward error correction to consume more than half of the power in optical digital processing (oDSP). Therefore, there is a pressing need to design FECs with high coding gain and low power consumption.

[0007] There are many techniques for designing FEC, and many types of FEC are known in the art (e.g., algebraic codes, convolutional turbo codes, low-density parity-check (LDPC) codes, turbo product codes (TPC), etc.). In 2009, Arikan introduced a block FEC known as “polar codes” in E. Arikan, “Channel Polarization: A method for Constructing Capacity Achieving Codes for Symmetric Binary-Input Memoryless Channels,” IEEE Trans. Inf. Theory, vol. 55, no. 7, pp. 3051-3073 (July 2009). Polar codes are a type of linear block code that “polarizes” the capacity of the bit channels. Polarization of the bit channels causes their capacities to approach either one (i.e., a perfect channel) or zero (a completely noisy channel). Data is then transmitted through the bit channels with capacities approaching one, while predetermined constant bit values are transmitted through the bit channels with capacities approaching zero (these bits are referred to as “frozen” bits because their values do not change). Arikan was able to prove that, when the code length (i.e., the number of bit channels) approaches infinity, the number of bit channels with capacity one divided by the total number of bit channels approaches the channel capacity, i.e., the theoretical maximum rate of the channel (also known as the “Shannon capacity”).

[0008] The decoding algorithm for polar codes proposed by Arikan is known as "successive-cancellation" (SC) decoding, which can be effectively represented as a binary tree search. While SC decoding shows excellent performance when the code length is close to infinity, its performance in medium and short length codes is disappointing. As a result, a number of alternative decoding algorithms have been proposed. One of the most commonly cited of these alternatives is known as "successive-cancellation list" (SCL) decoding, which was introduced in I. Tal and A. Vardy, "List Decoding of Polar Codes," IEEE Trans. Inf. Theory, vol. 61, no. 5, pp. 2213-2226 (May 2015). SCL decoding combines list decoding, a decoding technique known since the 1950s, with SC decoding for polar codes to produce an algorithm that does not look at a single candidate codeword, as is done in SC decoding, but rather examines a "list" of L most likely candidate codewords. SCL decoding for polar codes, combined with a cyclic redundancy check (CRC), a type of error detecting code known since 1961, has been shown to have error correction performance comparable to low-density parity-check codes.

[0009] Polar codes are the first, and currently only, class of codes that can be analytically proven to achieve the channel capacity within achievable complexity. While polar codes have this theoretical advantage over other known FECs, there are still many challenges in practical implementation. Therefore, it is desirable to develop methods that use polar coding techniques with increased coding gain and high throughput. SUMMARY

[0010] Advantageously, the present disclosure provides encoders and decoders that use multiple parallel polar codes and cooperate among them. This cooperation provides an improvement in gain compared to conventional polar codes, and using parallel polar codes increases the total throughput. Thus, the disclosed techniques can be seen as improving the reliability and throughput of digital communications and devices for such communications.

[0011] According to one aspect of the present disclosure, the technology is implemented as a method for encoding p bits for transmission over a communication channel. The method includes partitioning the p bits among m parallel polar codes (using among in the sense of and not intended to indicate two and only two), such that each of the m parallel polar codes includes a plurality of information bits, and splitting or partitioning the information bits in each of the m parallel polar codes into a private portion and a common portion, the common portion including an information segment and a repetition segment, where the information bits of the common portion are arranged in the information segment. The method further includes repeating the bits in the information segment of the common portion of each of the m parallel polar codes in the repetition segment of the common portion of another of the m parallel polar codes, arranging a plurality of frozen bits in each of the m parallel polar codes, and generating a polar-encoded codeword for each of the m parallel polar codes.

[0012] In some implementations, the information bits of the private portion of each of the m parallel polar codes are arranged in the most reliable bit positions of each of the m parallel polar codes. In some implementations, the information bits in the common portion of each of the m parallel polar codes are arranged in bit positions that are less reliable than the bit positions of the private portion of each of the m parallel polar codes. In some implementations, the bits of the repetition segment of the common portion of each of the m parallel polar codes are arranged in bit positions that are less reliable than the bit positions of the information segment of the common portion of each of the m parallel polar codes. The frozen bits are in the least reliable bit positions.

[0013] In some implementations, each of the m parallel polar codes includes a first CRC of the information bits in the parallel polar code. In certain of these implementations, each of the m parallel polar codes further includes a second CRC of the information bits in the common portion of the parallel polar code.

[0014] In some implementations, the method further includes partitioning the information segment of the common portion of each of the m parallel polar codes into blocks, each block including at least one bit. Repeating the bits in the information segment of the common portion of each of the m parallel polar codes includes interleaving the blocks of the information segment of the common portion of each of the m parallel codes in the repetition segment of the other of the m parallel polar codes according to a predetermined interleaving scheme. In some implementations, the predetermined interleaving scheme includes arranging sequential blocks of the information segment of the common portion of a parallel polar code diagonally in the repetition segment of the common portion of a subsequent parallel polar code of the m parallel polar codes.

[0015] In another aspect, the techniques are implemented in a method for iteratively decoding m polar coded codewords received over a communication channel, each of the codewords encoding information bits arranged into a private portion and a common portion, the common portion including an information segment and a repetition segment. The method includes iteratively repeating a horizontal decoding phase and a vertical decoding phase until all m parallel polar codewords have been marked as correctly decoded or a maximum allowed number of iterations is reached. The horizontal decoding phase includes decoding each of the codewords that have not been marked as correctly decoded using a CRC-aided successive cancellation polar decoder that treats any bits in the codewords that have been marked as frozen and frozen bits of the polar code as frozen, and performing at least one CRC check on each of the decoded codewords. The vertical decoding phase includes marking a first codeword that passed at least one CRC check in the horizontal decoding phase as correctly decoded, and marking all bits in at least a second codeword that are repeated from bits in the common portion of the first codword as frozen. In some implementations, decoding each of the codewords that have not been marked as correctly decoded using a CRC-aided successive cancellation polar decoder is performed in parallel.

[0016] In some implementations, marking the first codeword that passed at least one CRC check as correctly decoded further includes determining whether information in the information segment of the common portion of the first codeword matches information in the repetition segment of the common portion of a second codeword that is repeated and passed at least one CRC check, and if the information matches, marking both the first codeword and the second codeword as correctly decoded. In some implementations, performing at least one CRC check on each of the decoded codewords includes performing a first CRC check on information bits of each of the decoded codewords, and performing a second CRC check on bits of the common portion of each of the decoded codewords.

[0017] In another aspect, the disclosed technology is implemented as an encoder that encodes p bits for transmission over a communication channel. The encoder includes circuitry configured to: divide the p bits among m parallel polar codes such that each of the m parallel polar codes includes a plurality of information bits; divide the information bits in each of the m parallel polar codes into a private portion and a common portion, the common portion including an information segment and a repetition segment, wherein the information bits of the common portion are arranged in the information segment; repeat the bits in the information segment of the common portion of each of the m parallel polar codes in the repetition segment of the common portion of at least a second of the m parallel polar codes; arrange a plurality of frozen bits in each of the m parallel polar codes; and generate a polar-encoded codeword for each of the m parallel polar codes. In some implementations, the circuitry includes at least one processor and a memory storing programmed instructions that, when executed by the at least one processor, cause the at least one processor to encode the p bits.

[0018] In some implementations, the encoder further includes first CRC circuitry that computes a first cyclic redundancy check code on the information bits of each of the m parallel polar codes. In some implementations, the encoder includes second CRC circuitry that computes a second cyclic redundancy check code on the information bits in the common portion of each of the m parallel polar codes.

[0019] In another aspect, the disclosed technology is implemented as a decoder to decode m polar coded codewords received over a communication channel, each of the codewords encoding information bits arranged into a private portion and a common portion, the common portion including an information segment and a repetition segment. The decoder includes circuitry configured to iteratively repeat a horizontal decoding phase and a vertical decoding phase until all m parallel polar codewords have been marked as correctly decoded or a maximum number of iterations is reached. The horizontal decoding phase includes decoding each of the codewords that have not been marked as correctly decoded using a CRC-aided successive cancellation polar decoder that treats any bits in the codeword that have been marked as frozen and frozen bits of the polar code as frozen, and performing at least one CRC check on each of the decoded codewords. The vertical decoding phase includes marking a first codeword that passed the CRC check in the horizontal decoding phase as correctly decoded, and marking bits in the other codewords that repeat bits in the common portion of the first codeword as frozen. In some implementations, the circuitry includes at least one processor and a memory storing programmed instructions that, when executed by the at least one processor, cause the at least one processor to decode the m polar coded codewords.

[0020] In some implementations, the circuitry configured to mark a first codeword that passed the CRC check in the vertical phase as correctly decoded is further configured to determine whether information in the information segment of the common portion of the first codeword matches information in the repetition segment of the common portion of a second codeword for which information is repeated and passed at least one CRC check. The circuitry is configured to mark both the first codeword and the second codeword as correctly decoded if the information matches. BRIEF DESCRIPTION OF DRAWINGS

[0021] The features and advantages of the present disclosure will become more apparent from the detailed description in conjunction with the accompanying drawings, in which:

[0022] Figure 1 An encoder for a polar code is shown, for example, that can be used in the disclosed technology;

[0023] Figure 2 is a block diagram of a communication system in which the techniques of the present disclosure can be implemented;

[0024] Figure 3 A structure of a parallel polar code according to an implementation of the disclosed technology is shown;

[0025] Figure 4 An example of an interleaving scheme for a common portion of a parallel polar code of an implementation of the disclosed technology is shown;

[0026] Figure 5 is a flowchart of an encoding method according to an implementation of the disclosed technology;

[0027] Figure 6 is a flowchart of a decoding method according to an implementation of the disclosed technology; and

[0028] Figure 7 shows a graph 700 of simulation results of a parallel polar encoding method according to an implementation of the disclosed technology.

[0029] It should be understood that like numerals refer to like elements throughout the several views and that the drawings and corresponding description are intended to be illustrative and not restrictive.

[0030] DETAILED DESCRIPTION

[0031] Various representative embodiments of the disclosed technology will be described more fully below with reference to the accompanying drawings. The disclosed technology may, however, be embodied in many different forms and should not be construed as limited to the representative embodiments set forth herein. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Like numerals refer to like elements throughout the several views.

[0032] It should be understood that although the terms first, second, third, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). In addition, it should be understood that elements can be "coupled" or "connected" mechanically, electrically, communicatively, wirelessly, optically, etc., depending on the type and nature of the elements being coupled or connected.

[0034] The terminology used herein is for the purpose of describing particular representative embodiments only and is not intended to be limiting of the present technology. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0035] The functions of the various elements shown in the figures, including any functional blocks labeled as "processors", can be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software instructions. When provided by a processor, the functions can be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which can be shared. In some implementations, a processor can be a general purpose processor, such as a central processing unit (CPU), or a special purpose processor, such as a digital signal processor (DSP). Moreover, explicit use of the term "processor" should not be construed to refer exclusively to hardware capable of executing software, and can implicitly include, without limitation, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and / or custom, can also be included.

[0036] Software modules or simply modules or units suggested as software can be represented herein as any combination of flowchart elements or other elements indicating performance of processes and / or textual descriptions of the performance of the processes. Such modules can be executed by hardware that is explicit or implicit. Also, it should be understood that, for example, modules can include, but are not limited to, computer program logic for providing the desired capabilities, computer program instructions, software, stacks, firmware, hardware circuitry, or combinations thereof. It should also be understood that a "module" generally defines a logical grouping of relevant software code or other elements as described above that are associated with a defined function. Accordingly, those of ordinary skill in the art will recognize that a particular item described as a "module" in some implementations can be placed in other modules in other implementations depending on the logical organization of the software code or other elements and that such modifications are within the scope of the disclosure defined by the claims.

[0037] It should also be noted that, as used herein, the term "optimizing" means improving. It is not used to convey that a technically "best" solution is produced, but rather an improved (in at least one respect) solution is produced. In the context of memory access, it generally means that the efficiency or speed of memory access can be improved.

[0038] As used herein, the term "determining" generally means performing a direct or indirect computation, an operation, an identification, a discovery, a measurement, or a detection. In certain cases, such determining can be approximate. Thus, a determination of a value can indicate that the value or an approximation of the value is directly or indirectly computed, operated on, identified, discovered, measured, detected, or the like. If an item is "pre-determined," the item is determined at any time prior to the time it is indicated as being "pre-determined."

[0039] The technology can be implemented as a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions stored therein (or thereon) that, upon execution by a processor, implement various aspects of the disclosed technology. The computer readable storage medium can be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical or visual encoding of information (e.g., punch cards, bar codes), and / or any combination of these. As used herein, a computer readable storage medium does not include a transitory signal. It does not encompass a signal per se. It encompasses a computer and machine readable medium, however.

[0040] It should be understood that the computer readable program instructions can be loaded onto a respective computing device or processing device from a computer readable storage medium or to an external computer or an external storage device via a network, for example, the Internet, a local area network, a wide area network, and / or a wireless network. The network interface in each computing / processing device can receive the computer readable program instructions from the network and forward the computer readable program instructions into the computer readable storage medium within the respective computing or processing device for storage and / or execution. The computer readable program instructions for carrying out operations of the present disclosure can be in assembly code, machine code, firmware code, configuration data for integrated circuitry, or in source code or object code written in any combination of one or more programming languages.

[0041] All statements and specific examples describing the principles, aspects, and implementations of this technology herein are intended to include their structural and functional equivalents, whether they are currently known or will be developed in the future. Therefore, for example, those skilled in the art will understand that any block diagram herein represents a conceptual view of an illustrative circuit system embodying the principles of this technology. Similarly, it should be understood that any flowchart, diagram, state transition diagram, pseudocode, etc., represents various processes that can be substantially represented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor or other programmable data processing apparatus to produce a machine, such that the instructions, executable by the processor of a computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in the flowchart and / or one or more block diagram blocks. These computer-readable program instructions can also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that a computer-readable storage medium having instructions stored therein comprises an article of manufacture containing instructions that implement various aspects of the functions / actions specified in the flowchart, diagram, state transition diagram, pseudocode, etc.

[0042] Computer-readable program instructions can also be loaded onto a computer, other programmable data processing apparatus or other equipment to cause a series of operational steps to be performed on the computer, other programmable apparatus or other equipment, thereby producing a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus or other equipment implement the functions / actions specified in flowcharts, flowcharts, state transition diagrams, pseudocode, etc.

[0043] In some alternative implementations, the functions indicated in flowcharts, diagrams, state transition diagrams, pseudocode, etc., may not occur in the order shown in the diagram. For example, two blocks shown consecutively in a flowchart may actually be executed substantially simultaneously, or, depending on the functions involved, these blocks may sometimes be executed in reverse order. It should also be noted that each function indicated in the figures, as well as combinations of these functions, can be implemented by a dedicated hardware-based system that performs the specified function or action, or by a combination of dedicated hardware and computer instructions.

[0044] Based on these fundamental principles, we will now consider some non-limiting examples to illustrate various implementations of the various aspects of this disclosure.

[0045] Figure 1An encoder 100 for polar codes is shown. As described above, polar codes are linear block codes whose “polarized” bit channels (which may also be called sub-channels) have capacities such that the channel capacity is close to one (i.e., a perfect channel) or zero (a completely noisy channel). Information bits 102 are then transmitted through a bit channel with a capacity close to one, while frozen bits 104—a predetermined constant bit value—are transmitted through a bit channel with a capacity close to zero.

[0046] The polar encoder 100 typically encodes the input bits, including information bits 102 and freeze bits 104, with a total block length of N = 2. n , where n is an integer. This can be called an (N, k) polar code with k information bits (i.e., information bits 102) and N encoded bits (leaving N to k frozen bits 104). Typically, an (N, k) polar code can be defined by an N×N generator matrix G, where:

[0047]

[0048] In the above formula, This represents n times the Kronecker power. The input bits 106 are represented as u = [u1, u2, ..., u...]. N ] T The 108 encoded bits (collectively referred to as "codewords" x) are represented as x = [x1, x2, ..., x...]. N ] T The codeword is given by x = GBu, where B represents an N×N bit inversion permutation matrix. This operation occurs within the polar encoder 100.

[0049] It should be understood that the generator matrix G is only one generator matrix that produces polarization, and other generator matrices are known to produce such polarization as well. Furthermore, although the frozen bits 104 are shown as being placed before the input bits 106, they will actually be distributed throughout the entire input bits 106.

[0050] It should also be understood that complete channel polarization is achieved only in the limit N→∞. For medium to small code lengths N, polar codes will produce channels with a certain capacity range, although these capacity ranges will generally still be polarized towards one (i.e., a perfect channel) or zero (i.e., a completely noisy channel), but will not reach either of these limits. Therefore, for real-world polar coding, we want to place the k information bits 102 in the k most reliable (i.e., highest capacity) positions in u. The N to k frozen bits 104 are placed in the positions with the lowest reliability in u, and are assigned to the encoder 100 and decoder ( Figure 1 (Not shown) Known fixed values. Reliability in the real world is a matter of degree, but it is possible and practical to distinguish between reliable (i.e., more reliable) locations and unreliable (less reliable) locations.

[0051] Figure 2 is a block diagram of a communication system 200 in which the techniques of the present disclosure can be implemented. The communication system includes an encoder 202 and a transmitter 204, a communication channel 220, a receiver 250 and a decoder 252.

[0052] As mentioned above, the communication channel 220 can be, for example, a wireless communication channel, a cable or an optical fiber. It will be appreciated that there can be noise or interference on the communication channel 220. As a result of such noise or interference, some of the bits received at the receiver 250 can have been changed during transmission and thus can not be identical to the bits transmitted by the transmitter 204 on the communication channel 220.

[0053] The encoder 202 receives a block of information to be transmitted at its input 206, encodes the information in accordance with an implementation of the disclosed techniques as described below to produce a codeword for transmission on the communication channel 220, and forwards the codeword to the transmitter 204 for transmission on the communication channel 220. In some implementations, the encoder 202 includes one or more processors 210 and a memory 212 including programmed instructions that cause the processors 210 to encode the information, as described below. It will be appreciated that in some implementations, the encoder 202 can include alternative or additional hardware or circuitry, for example, one or more chipsets, microprocessors, digital signal processors, optical processors, optical digital signal processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated logic circuitry, or combinations of these to encode the information, as described below.

[0054] The transmitter 204 transmits the codeword over the communication channel 220. The configuration of the transmitter 204 will therefore depend on the nature of the communication channel 220. Typically, the transmitter 204 is or can be a conventional transmitter for the communication channel 220. Thus, although not shown, the transmitter 204 can include modules for post-encoding processing; and modules or components of a transmit chain for the communication channel 220, for example, modulators, amplifiers, multiplexers, light sources (for example, for optical communications), antennas (for example, for wireless communications); and / or other modules or components of a conventional transmitter.

[0055] Similarly, receiver 250 receives codewords via communication channel 220. Therefore, the detailed configuration of receiver 250 will depend on the nature of communication channel 220. Receiver 250 is a conventional receiver for communication channel 220 and may include various modules and components of a conventional receiver chain (not shown) as well as components (not shown) for any pre-decoding processing. For example, these modules and components may include antennas (e.g., for wireless communication), optical sensors or detectors (e.g., for optical communication), demodulators, amplifiers, demultiplexers, and / or other modules or components of a conventional receiver chain. Codewords received by receiver 250 are forwarded to decoder 252.

[0056] Decoder 252 receives codewords from receiver 250 and decodes the codewords according to the disclosed technical implementations described below to produce received information provided by the decoder as output 256. In some implementations, decoder 252 includes one or more processors 260 and memory 262, the memory including programming instructions that cause processors 260 to decode information, as described below. It should be understood that in some implementations, decoder 252 may include alternative or additional hardware or circuitry systems, such as one or more chipsets, microprocessors, digital signal processors, optical processors, optical digital signal processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated logic circuitry systems, or combinations thereof, to decode information, as described below.

[0057] Figure 3 The structure 300 of a parallel polar code according to this disclosure is shown. As shown, there are m parallel polar codes 302 (displayed along the vertical axis as polarization 1 to polarization m). The polar-coded information is displayed along the horizontal axis, with the most reliable bit on the left, and the reliability of the position decreasing from left to right. The information bits in each polar code are divided (e.g., separated or distributed) into two parts, referred to as the "private" part 304 (labeled m). 12 to m n2 The private part 304 and the "public" part 306 (which may also be referred to as the "shared" part) are separate parts. Data in the private part 304 appears only in a single parallel polar code within the parallel polar code 302, while each bit in the public part 306 will be repeated in at least the public part 306 of the second parallel polar code within the parallel polar code 302. Therefore, the public part 306 can be considered as being encoded using both polar codes (i.e., along the horizontal axis) and repetition codes (i.e., along the vertical axis). Furthermore, each polar code in the m polar codes 302 includes a frozen bit 308 (labeled f1 to f...). n ).

[0058] From their position along the horizontal axis, it can be seen that the private portion 304 is placed in the most reliable bit positions (i.e., bit channels with capacities closest to one) in each polar code, followed by the common portion 306, and the frozen bits 308, which are placed in the least reliable bit positions (i.e., bit channels with capacities closest to zero). The common portion 306 of each polar code is divided into: an information segment 310 (labeled m 11 to m n1 ), which occupies the more reliable bit positions in the common portion 306; and a repetition segment 312 (labeled m 10 to m n0 ), which is located in the less reliable bit positions in the common portion 306. The information segment 310 contains a common portion of the information encoded in each of the parallel polar codes 302, while the repetition segment 312 contains bits that are repeated from other information segments in the information segment 310 of the common portion 306 of the parallel polar codes 302. In some implementations, this repetition of bits can be accomplished using interleaving, as described below.

[0059] Decoding can require one or more iterations. Advantageously, when one polar code is correctly decoded in one decoding iteration, the decoded information in the common portion 306 can be used to aid in decoding the other parallel polar codes 302 in subsequent decoding iterations. In some implementations, when a check (described below) has been performed to confirm that a polar code has been correctly decoded, the bits of the common portion 306 can be treated as “frozen” (i.e., known) in subsequent decoding iterations, which can improve the error correction capability of each of the parallel polar codes 302. By placing the common portion 306, and in particular the repetition segment 312, in the less reliable bits, the advantage of being able to treat these bits as “frozen” in subsequent iterations is increased, because we can replace a relatively low capacity bit channel with “frozen” information, which is known. It should also be appreciated that when using the SCL decoding algorithm, frozen bits cause the error probability to decrease, further increasing the advantage of being able to treat more bits as “frozen”.

[0060] In addition to the information bits (including the private portion 304 and the common portion 306) and the frozen bits 308, in some implementations, each of the parallel polar codes 302 includes two CRCs: a first CRC 314 (labeled C 11 to C 1n ) for all of the information (i.e., the private portion 304 and the common portion 306) and a second CRC 316 (labeled C 21 to C 2nAs described below, these CRCs are used during decoding to verify whether decoding has been successful. It should be understood that although two CRCs are shown in this implementation, only a single CRC or more than two CRCs may be used. Furthermore, although the first CRC 314 and the second CRC 316 are shown in this implementation as occupying less reliable bits in each of the parallel polar codes 302, the CRCs may be placed in other positions within the polar codes, or they may be distributed or interleaved within each of the parallel polar codes 302.

[0061] Figure 4 An example of an interleaving scheme for the common parts of parallel polar codes is shown. Figure 4 In the example shown, 50 parallel polar codes 402 are illustrated along the vertical axis (i.e., m = 50). The common portion 406 includes an information segment 410 containing 5 bit blocks and a repeating segment 412 containing 5 bit blocks. For the 50 parallel polar codes 402, each parallel polar code contains 5 bit blocks in its information segment 410 of its common portion 406, so there are a total of 250 information bit blocks encoded in the common portion 406 of the parallel polar codes 402.

[0062] exist Figure 4 In the interleaving shown, 250 information blocks b1 to b 250 The information blocks are arranged sequentially (or ordered or placed in order) in the information segments 410 of the parallel polar codes 402, and diagonally in the repeating segments 412 of the parallel polar codes 402. This interleaving ensures that each information block is included in two parallel polar codes within the parallel polar codes 402 (once in the information segment 410 and once in the repeating segment 412 of another parallel polar code within the parallel polar codes 402). Furthermore, the common portion 406 of each polar code shares information with 10 other polar codes out of the 50 parallel polar codes 402.

[0063] It should be understood that Figure 4 Only one example is shown, and other interleaving schemes involving different numbers of parallel polar codes and different numbers of bit blocks can be used according to the disclosed techniques. Generally, an interleaving scheme in which each bit in the information segment of the common part appears in a repeating segment of at least one other parallel polar code will provide at least some advantages in decoding. It should be understood that some interleaving schemes may repeat bits from the information segment of the common part in more than one other parallel polar code. Furthermore, an interleaving scheme can be used in which the common part of each polar code can share information with at least one other polar code in the parallel polar codes, with other polar codes having the same number of bits in the common part, or with any number of other polar codes between these polar codes.

[0064] Figure 5 A flowchart 500 of an encoder in accordance with implementations of the disclosed technology is shown. The encoder accepts p information bits and encodes the information using m parallel polar codes. In block 502, the encoder divides the p information bits to be encoded into m portions, each of which will be encoded in one of the m parallel polar codes. In general, p and m can be chosen so that this division results in an equal number of bits of information to be encoded in each of the parallel polar codes. Alternatively, the p information bits can be padded to achieve this division of bits.

[0065] In block 504, the p / m information bits of each polar code are split into a private portion and a public portion. This split is performed so that the information bits are placed in the information segments of the private and public portions. (As used herein, the concepts of splitting and partitioning are related concepts and can overlap; the different terminology is used for clarity of explanation and is not meant to indicate that the concepts of splitting and partitioning are completely distinct.)

[0066] In block 506, the public portions of the m parallel polar codes are interleaved to repeat each bit in the information segment of the public portion of each of the parallel polar codes in the repetition segment of the public portion of at least one other parallel polar code. To achieve this, in some implementations, the interleaving scheme discussed above with reference to FIG. 4 can be used, but other interleaving schemes can also be used. Figure 4

[0067] In block 508, conventional methods for computing CRCs are used to compute first CRCs for all of the bits in the public and private portions of each of the parallel polar codes. These methods can include, for example, computing CRCs using any known CRC-32 polynomial or any other known CRC method or algorithm, such as the methods described in P. Koopman, “32-bit cyclic redundancy codes for Internet applications,” Proceedings International Conference on Dependable Systems and Networks, Washington, D.C., USA, 2002, pp. 459-468. Similarly, in block 510, conventional methods for computing CRCs are used to compute second CRCs for the public portions of each of the parallel polar codes. These CRCs are appended to the input bits of each of the parallel polar codes.

[0068] ​In block 512, freeze bits are added to each of the parallel polar codes. Typically, these freeze bits can all have the same constant value of "0" or "1", and this value is known to both the encoder and decoder. It should be understood that in some implementations, other patterns of freeze bits can be used, provided that the value of each freeze bit is known to both the encoder and decoder. For each freeze bit in the parallel code, there should be a predetermined size, which is a power of 2 (i.e., the code size is N = 2^3). n (where n is an integer).

[0069] In block 514, a conventional polar coding method is applied to each of the parallel polar codes to generate a coded codeword for each of the parallel polar codes. These codewords can then be transmitted via channels such as wireless channels, cables, or optical fibers. The polar coding method can be as described above. Figure 1 The described coding method, such as that described in E. Arikan, “Channel Polarization: A method for Constructing Capacity Achieving Codes for Symmetric Binary-Input Memoryless Channels,” IEEE Trans. Inf. Theory, Vol. 55, No. 7, pp. 3051-3073 (July 2009), or any other known polarization coding method or algorithm.

[0070] Use reference Figure 5 The encoder described above provides a total of m×(l) private +l public +l CRC1 +l CRC2 +l frozen ) coded bits (where l private It is the number of bits in the private part of each parallel polar code, l public It is the total number of bits in the common part of each parallel polar code, l CRC1 It is the length of the first CRC, l CRC2 It is the length of the second CRC, l frozen (where m is the number of frozen bits in each parallel polar code and m is the number of parallel polar codes) for m×(l private +l pub_inf ) information bits (where l private It is the number of bits in the private part of each parallel polar code, l pub_infis the number of bits in the information segment of the common part of each parallel polar code, m is the number of parallel polar codes) is encoded. The length l public of the common part of each parallel polar code Figure 4 is the sum of the length of the information segment and the length of the repetition segment of the common part. Using the interleaving scheme shown above in and

[0071] , where each block of bits in the information segment of the common part is repeated in the repetition segment of the common part of another parallel polar code, the length of the information segment will be the same as the length of the repetition segment, and l public = 2 x l pub_inf , where l public is the length of the common part of each parallel polar code (in bits), and l pub_inf is the length of the information segment of the common part of each parallel polar code (in bits). In the more general case, where each block of bits in the information segment of the common part is repeated in q repetition segments of q other parallel polar codes, and l public = (q + l) x l pub_inf , where l public is the length of the common part of each parallel polar code (in bits), and l pub_inf is the length of the information segment of the common part of each parallel polar code (in bits).

[0071] Figure 6 is a flowchart 600 of a decoding method according to various implementations of the disclosed technology. Typically, decoding is performed on a codeword received over a noisy channel, with the aim of correctly decoding the information originally encoded and transmitted over the channel from the received codeword. Thus, in block 602, the decoder receives m parallel polar codewords to be decoded. The codewords are received over a channel such as a wireless channel, a cable, or an optical fiber. There can be noise or interference on the channel, which means that some bits of the received codeword can have been changed during transmission and can not be the same as the bits in the codeword transmitted over the channel. Thus, the decoder should be able to detect and (for FEC) correct these errors.

[0072] According to implementations of the disclosed technology, the decoding method is iterative, with each iteration having two phases, a horizontal phase 610 and a vertical phase 612. The horizontal phase 610 decodes the parallel polar codes along the horizontal axis, as shown above in Figure 3 and Figure 4 The vertical phase 612 uses the repetition between the common parts of the parallel polar codes to effectively “freeze” the bits for the next iteration. It is called a “vertical” phase because it processes information from multiple polar codes of the parallel polar codes, i.e., decodes the parallel polar codes along the vertical axis, as shown above in Figure 3 and Figure 4

[0073] In block 620 of horizontal stage 610, any of the m polar codewords that have not been marked as correctly decoded are decoded using a known CRC-aided SCL decoder, such as described in I. Tal and A. Vardy, “List Decoding of Polar Codes,” IEEE Trans. Inf. Theory, vol. 61, no. 5, pp. 2213-2226 (May 2015), although other known CRC-aided SCL decoders can also be used. In some implementations, the CRC-aided SCL decoding of these codewords can be performed in parallel. As will be discussed below, the bits that are considered “frozen” bits will vary for each codeword in each iteration, according to the common portion of the codewords that have been marked as correctly decoded during previous iterations. The marking can be done by any technique such that the marking indicates a correct (or incorrect) decoding, and the decoding can be evaluated as correct by checking the marking. The SCL decoder considers any bits in the codeword that are marked as frozen (see below), as well as the frozen bits of the polar code (i.e., the frozen bits 308 of the polar code 300), as frozen. During the first iteration, all m parallel polar codewords will be decoded using the CRC-aided SCL decoder, and only the frozen bits of the polar code will be considered frozen. Figure 3

[0074] It should be appreciated that for CRC-aided SCL decoding, the CRC check is used to determine which path in the path list is most likely to represent the decoded codeword that corresponds to the transmitted codeword (i.e., which of the several possible decoded codewords is most likely to have been correctly decoded). In some implementations, the CRC check used in the CRC-aided SCL decoding can correspond to the second CRC discussed above (in the context of encoding) in Figure 3

[0075] In block 622, the first CRC and the second CRC are checked. As described above, the first CRC is used to check all the information bits in the codeword, while the second CRC is used to check the information in the common portion of the codeword. Each of the parallel polar codewords in which both CRCs are correct is passed to vertical stage 612. It should be appreciated that in some implementations, only a single CRC (i.e., the CRC used in the CRC-aided SCL decoding) can be used, or more than two CRCs can be used.

[0076] ​​In block 650 of vertical phase 612, each of the CRC-correct polar code words undergoes an additional check to determine whether the code word has been decoded correctly and the information in the common part of the code word can be accepted as valid "frozen" in the next iteration. The additional check is performed by looking at the pair of CRC-correct code words to see if they have information in the information segment of the common part of the first code word that is repeated in the repetition segment of the common part of the second code word. If the information matches in both code words, then both code words are marked as decoded correctly.

[0077] It should be understood that the additional check of block 650 can not be used in some implementations, in which case all code words that are CRC-correct will be marked as decoded correctly. Furthermore, in some implementations that use more than one repetition of the information segment of each block in the common part, the matching of information in the common part of the code words can be performed over a larger subset of the code words than the pair of code words described above.

[0078] While this additional check can be optional, it should be noted that since the bits in the common part of a code word that is marked as decoded correctly will effectively be "frozen" in the other code words that share that information, a high degree of certainty is required. If a code word that has been marked as decoded correctly is in fact not decoded correctly, the error in the common part of the code word can propagate to all other code words that share the information in the common part of the code word.

[0079] In block 652, for each code word that has been marked as decoded correctly, all information in the common part of the code word is marked as "frozen" in all other code words in which it appears for all future iterations. As described above, treating these shared common parts as "frozen" improves the error correction capability of the code. Furthermore, in the SCL decoding algorithm, the additional frozen bits result in a reduction in time and resources used for decoding and a reduction in the error rate of decoding.

[0080] The decoding method iterates continuously, alternating between horizontal phase 610 and vertical phase 612, until all parallel polar code words are marked as decoded correctly, in which case the decoding is successful; or iterates continuously until code words that are not decoded correctly remain and other common parts of the remaining code words cannot be marked as "frozen", in which case the decoding is unsuccessful.

[0081] As an example of a vertical phase of decoding according to various implementations of the disclosed technology, reference is again made to Figure 4 . Assume that m of the polar codes have Figure 4The second and sixth parallel polar codes of the common part shown have been decoded by the CRC-aided SCL decoder during the first iteration, and both CRCs of the two codes are correct. Since the information part of the second code includes block b9, and said block is repeated in the repetition part of the sixth code, an extra check can be performed by determining whether all bits of block b9 in the second and sixth codes match. If they do, both the second and sixth polar codes will be marked as decoded correctly, and all bits of all blocks in the common part of the two codes can be marked as “frozen” and treated as frozen bits in all subsequent decoding iterations. This means that all bits in blocks b6, b7, b8, b9, b 10 , b 237 , b 242 , b 246 , b 249 , and all blocks in the common part of the sixth code, i.e., blocks b 26 , b 27 , b 28 , b 29 , b 30 , b 21 , b 17 , b 13 , b9 (both repeated) and b5 can be treated as “frozen”. Treating bits in all these blocks as frozen will facilitate decoding of, e.g., the first parallel polar code (block b5), the third code (blocks b6 and b 13 ), the fourth code (blocks b7 and b 17 ), the fifth code (blocks b8 and b 21 ), etc.

[0082] Figure 7 A plot 700 of simulation results comparing a parallel polar encoding method according to an implementation of the technology disclosed above (“proposed method” curve 706) with an original polar code (“original polar code” curve 708) is shown. For the simulation, the polar code length N was 1024 bits, and the overhead was 66.8%.

[0083] The horizontal axis 702 shows the normalized signal-to-noise ratio (SNR) in dB, also referred to as the energy per bit to noise power spectral density ratio (Eb / N0), expressed as the ratio of the energy per bit to the noise power spectral density. The vertical axis 704 shows the bit error rate (BER). b

[0084] ​It can be seen that the curve 706 of the proposed method shows an improvement of about 0.4 dB over the original polar code curve 708. As will be appreciated by those skilled in the art, this represents a significant improvement in the performance of the forward error correction code.

[0085] It is to be understood that while the embodiments presented herein have been described with reference to particular features and structures, this is by way of example only and that various modifications and combinations can be effected without departing from the disclosure. Consequently, the description and drawings merely set forth an implementation or example of the concepts disclosed and are not intended to limit the scope of the disclosure which encompass any and all modifications, changes, combinations, or equivalents falling within the scope of the present disclosure.

Claims

1. A method for encoding p bits transmitted through a communication channel, the method comprising: The p bits are divided among the m parallel polar codes, such that each of the m parallel polar codes includes multiple information bits; The information bits in each of the m parallel polar codes are divided into a private part and a public part. The public part includes an information segment and a repetition segment, wherein the information bits of the public part are arranged in the information segment. The bits in the information segment of the common part of each of the m parallel polar codes are repeated in the repeating segment of the common part of at least the second parallel polar code among the m parallel polar codes. In each of the m parallel polar codes, multiple frozen bits are arranged; and For each of the m parallel polar codes, generate a polar-coded codeword.

2. The method according to claim 1, wherein, The information bits in the private portion of each of the m parallel polar codes are arranged at the most reliable bit position in each of the m parallel polar codes.

3. The method according to claim 2, wherein, The information bits in the common part of each of the m parallel polar codes are arranged in unreliable bit positions compared with the bit positions in the private part of each of the m parallel polar codes.

4. The method according to claim 3, wherein, The bits of the repeating segment of the common part of each of the m parallel polar codes are arranged in unreliable bit positions compared with the bit positions of the information segment of the common part of each of the m parallel polar codes.

5. The method according to claim 1, wherein, Each of the m parallel polar codes includes a first cyclic redundancy check (CRC) of the information bits in the parallel polar code.

6. The method according to claim 5, wherein, Each of the m parallel polar codes also includes a second CRC of the information bits in the common part of the parallel polar codes.

7. The method of claim 1, further comprising dividing the information segment of the common part of each of the m parallel polar codes into multiple blocks, each block comprising at least one bit, wherein, Repeating bits in the information segment of the common part of each of the m parallel polar codes includes: according to a predetermined interleaving scheme, interleaving multiple blocks of the information segment of the common part of each of the m parallel codes in the repeated segments of other parallel polar codes in the m parallel polar codes.

8. The method according to claim 7, wherein, The predetermined interleaving scheme includes: arranging sequential blocks of information segments of the common part of parallel polar codes diagonally within repeated segments of the common part of subsequent parallel polar codes of m parallel polar codes.

9. A method for iteratively decoding m polar-decoded codewords received via a communication channel, each of the codewords encoding information bits arranged as a private part and a public part, the public part comprising an information segment and a repetition segment, the method comprising: The horizontal decoding stage and the vertical decoding stage are repeated iteratively until all m parallel polar codewords have been marked as correctly decoded; The horizontal decoding stage includes: A CRC-assisted successive elimination list polar decoder is used to decode each codeword in a codeword that has not yet been marked as correctly decoded to generate a decoded codeword, wherein the CRC-assisted successive elimination list polar decoder treats any bits in the codeword that have been marked as frozen and the frozen bits of the polar code as frozen; and Perform at least one CRC check on each of the decoded codewords; and The vertical decoding stage includes: The first codeword that passed at least one CRC check during the horizontal decoding phase is marked as correctly decoded; and In at least the second codeword, bits that are repeated from the common part of the first codeword are marked as frozen.

10. The method according to claim 9, wherein, Parallel execution uses a CRC-assisted sequential depolarization decoder to decode each codeword that has not yet been marked as correctly decoded.

11. The method according to claim 9, wherein, Marking a first codeword that has passed at least one CRC check as correctly decoded further includes: determining whether the information in the information segment of the common part of the first codeword matches the information in the repeated segment of the common part of the second codeword whose information is repeated and has passed at least one CRC check; and if the information matches, marking both the first codeword and the second codeword as correctly decoded.

12. The method according to claim 9, wherein, Performing at least one CRC check on each of the decoded codewords includes: performing a first CRC check on the information bits of each of the decoded codewords, and performing a second CRC check on the common bits of each of the decoded codewords.

13. The method according to claim 12, wherein, Marking a first codeword that has passed at least one CRC check as correctly decoded further includes: determining whether the information in the information segment of the common part of the first codeword matches the information in the repeated segment of the common part of the second codeword whose information is repeated and has passed at least one CRC check; and if the information matches, marking both the first codeword and the second codeword as correctly decoded.

14. An encoder for encoding p bits transmitted through a communication channel, the encoder comprising a circuit system configured to: The p bits are divided among the m parallel polar codes, such that each of the m parallel polar codes includes multiple information bits; The information bits in each of the m parallel polar codes are divided into a private part and a public part. The public part includes an information segment and a repetition segment. The information bits of the common part are arranged in the information segment; The bits in the information segment of the common part of each of the m parallel polar codes are repeated in the repeating segment of the common part of at least the second parallel polar code among the m parallel polar codes. In each of the m parallel polar codes, multiple frozen bits are arranged; as well as For each of the m parallel polar codes, generate a polar-coded codeword.

15. The encoder according to claim 14, wherein, The circuit system includes at least one processor and a memory storing programming instructions, which, when executed by the at least one processor, cause the at least one processor to encode the p bits.

16. The encoder of claim 14 further includes a first CRC circuit system, wherein the first CRC circuit system calculates a first cyclic redundancy check code on the information bits of each of the m parallel polar codes.

17. The encoder of claim 16 further includes a second CRC circuit system, the second CRC circuit system calculating a second cyclic redundancy check code on the information bits in the common part of each of the m parallel polar codes.

18. A decoder for decoding m polar-decoded codewords received via a communication channel, each of the codewords encoding information bits arranged as a private part and a public part, the public part comprising an information segment and a repetition segment, the decoder comprising a circuit system configured to: The horizontal decoding stage and the vertical decoding stage are repeated iteratively until all m parallel polar codewords have been marked as correctly decoded; in, The horizontal decoding stage includes: A CRC-assisted successive elimination list polar decoder is used to decode each of the codewords that have not yet been marked as correctly decoded to generate a decoded codeword, wherein the CRC-assisted successive elimination list polar decoder treats any bits in the codeword that have been marked as frozen and the frozen bits of the polar code as frozen; and Perform at least one CRC check on each of the decoded codewords; and The vertical decoding stage includes: The first codeword that passed at least one CRC check during the horizontal decoding phase is marked as correctly decoded; and In at least the second codeword, bits that are repeated from the common portion of the first codeword are marked as frozen.

19. The decoder according to claim 18, wherein, The circuit system includes at least one processor and a memory storing programming instructions, which, when executed by the at least one processor, cause the at least one processor to decode the m polarized codewords.

20. The decoder according to claim 18, wherein, The circuit system configured to mark a first codeword that has passed at least one CRC check in the vertical phase as correctly decoded is further configured to: determine whether the information in the information segment of the common part of the first codeword matches the information in the repeated segment of the common part of the second codeword whose information is repeated and has passed at least one CRC check, and if the information matches, mark both the first codeword and the second codeword as correctly decoded.

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