A Hardware Monitor Method and Device for Software Secure Execution

Abstract

The present invention provides a hardware monitor method and apparatus for software secure execution. The apparatus includes a modified core, an information selector, a special out-of-order architecture, a parallel comparator, a monitor register, a data structure, a cache, a rule bypass cache, and a first-in-first-out buffer FIFO. The special out-of-order architecture is used to improve performance. The parallel comparator is used to reduce monitoring latency. The data structure is used to record a security rule table containing security rules. The rule bypass cache is used to reduce redundant monitoring operations. The present invention has high flexibility and can implement a wider range of security policies. The performance overhead of the present invention is similar to that of a dedicated hardware monitor. Thanks to high flexibility and high performance, the present invention can implement security policies with high computing requirements.

Description

Technical Field

[0001] The present invention relates to a hardware monitor method and device for software security execution. Background Art

[0002] A security monitor is a device used to monitor whether a computer is under software attack. The security monitor determines whether a software attack has occurred by monitoring a series of operations in the computer, including the memory access addresses, frequencies, and jumps of branch instructions of the central processing unit (CPU). The security monitor can be implemented through software programming or through hardware circuits on a chip. The monitoring by the monitor causes the program to run slower, and the part of the slowdown time compared to the original program running time is called the performance overhead brought by the security monitoring.

[0003] Nowadays, hardware-based monitors have attracted much attention due to their better performance compared to software-based monitors, especially in fields that require high security such as artificial intelligence, big data, and communication systems.Some classic hardware-based monitors such as CHERI (Reference: Watson R N M, Woodruff J, Neumann P G, et al. CHERI: A hybrid capability-system architecture for scalable software compartmentalization [C] / / 2015 IEEE Symposium on Security and Privacy. IEEE, 2015: 20-37.), HCFI (Reference: Christoulakis N, Christou G, Athanasopoulos E, et al. HCFI: Hardware-enforced control-flow integrity [C] / / Proceedings of the Sixth ACM Conference on Data and Application Security and Privacy. 2016: 38-49.), ABCFI (Reference: Li J, Chen L, Shi G, et al. ABCFI: Fast and lightweight fine-grained hardware-assisted control-flow integrity [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39(11): 3165-3176.), HDFI (Reference: Song C, Moon H, Alam M, et al. HDFI: Hardware-assisted data-flow isolation [C] / / 2016 IEEE Symposium on Security and Privacy(SP). IEEE, 2016: 1-17.), RvDfi (Reference: Feng L, Huang J, Li L, et al. RVDFI: A RISC-V Architecture with Security Enforcement by High Performance Complete Data-Flow Integrity [J]. IEEE Transactions on Computers, 2021.), these monitors can effectively monitor software attacks according to the security policies they implement.However, faced with the increasing security application scenarios, it is not enough to be able to implement only a few security policies. For example, in military applications with high security requirements, and in commercial systems that require a balance between security and performance, and also, for example, on personal computers with very low security requirements, a dedicated hardware monitor can only implement a few specific security policies, far from meeting such extensive requirements. Moreover, compared with software-based monitors, the latter can be easily redesigned and updated, while hardware monitors require a long update cycle and a large design cost.

[0004] To address the above drawbacks, some flexible hardware monitors have been proposed in this field in recent years. These monitors, either using a security rule that can handle multiple security policies or reconfigurable hardware design monitors, can implement multiple security policies with relatively low performance overhead. For example, PUMP (Reference: Dhawan U, Hritcu C, Rubin R, et al. Architectural support for software-defined metadata processing[C] / / Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems. 2015:487-502.) is a label-based flexible monitor that integrates a cache of a security rule into the processor's pipeline and implements multiple security policies by means of designer-configured label checking. The average performance overhead of this monitor is only about 10%. However, in some scenarios, its performance overhead exceeds 50%. CHEx86 (Reference: Sharifi R, Venkat A. CHEx86: Context-sensitive enforcement of memory safety via microcode-enabled capabilities[C] / / 2020 ACM / IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2020:762-775.) is a label-based hardware monitor for the x86 architecture that can check pointers through programming of different microcodes, with an average performance overhead of approximately 14%. PHMon (Reference: Delshadtehrani L, Canakci S, Zhou B, et al. {PHMon}: A Programmable Hardware Monitor and Its Security Use Cases[C] / / 29th USENIX Security Symposium (USENIX Security 20). 2020:807-824.) is an event-based hardware monitor deployed on a reduced instruction set processor (RISC-V processor). After programming the monitor through monitor rules, it can implement multiple security policies with a performance overhead of only 0.9%.However, although these monitors can implement various security policies, their configuration mechanisms and hardware designs can only target security policies within a specific range, such as pointer permission checks or label-based security policies. And these existing flexible hardware monitors do not implement security policies that require a large amount of computational requirements.

[0005] The disadvantages of the existing solutions are summarized as follows:

[0006] Limited flexibility: The existing solutions do not adequately consider the common operations in different security policies, so they can only implement a specific range of security policies, such as only implementing label-based or event-based security policies.

[0007] Limited security: The existing flexible hardware monitor solutions do not implement some security policies with high computational requirements, such as data flow integrity (DFI) which stipulates that the data read by each read instruction can only be written by specific legitimate write instructions. Summary of the Invention

[0008] Object of the Invention: Hardware monitors have received wide attention because they can monitor various software attacks in a computer system in real time with high performance. However, dedicated hardware monitors can only be applied to very few scenarios, and their flexibility is greatly limited. And currently, there are still many limitations in the security and configurability of some flexible hardware monitors. The present invention aims at the above problems and proposes a programmable hardware monitor ProMiSE with a monitor instruction set and various security auxiliary designs. This monitor can not only be applied to a very wide range of scenarios, but also has high performance and security. Its monitoring latency is only 18 - 59 processor cycles, and the performance overhead is between ~0% - 23.4%. The monitor proposed by this invention is the most advanced solution currently.

[0009] The present invention provides a hardware monitor method applied to software security execution, including an offline stage before program execution and an online stage during program execution;

[0010] The offline stage includes writing a monitor program and program instrumentation by the user according to requirements. Program instrumentation means inserting new instructions into the original program;

[0011] The online stage includes obtaining software execution information and monitoring by the software runtime monitor;

[0012] In the offline stage, the user writes a monitor program through the monitor instruction set to implement operations of different security policies and select different software execution information;

[0013] In the offline stage, for the software program to be monitored, specific instructions ExInfo for carrying additional software execution information are inserted into the program. The specific instructions ExInfo are executed in the core, and the instruction encoding other than the opcode for distinguishing different instructions in the specific instructions ExInfo can be user-defined to carry additional information; the user can insert the specific instructions ExInfo at any position in the monitored software program.

[0014] The present invention also provides a hardware monitor device for software secure execution, including a modified core (central processing unit), an information selector, a dedicated out-of-order architecture, a parallel comparator, a monitor register, a data structure, a cache, a rule bypass cache, and a first-in-first-out buffer FIFO;

[0015] The dedicated out-of-order architecture is used to improve performance;

[0016] The parallel comparator is used to reduce monitoring latency;

[0017] The data structure is used to record a security rule table containing security rules;

[0018] The rule bypass cache is used to cut down redundant monitoring operations;

[0019] The first-in-first-out buffer FIFO includes two types, namely a high-bandwidth FIFO with a bit width of 512 bits and a low-bandwidth FIFO with 64 bits;

[0020] The modified core is used to connect the program counter signal for counting the instruction address of the core to the monitor, so that the monitor can obtain the core instruction address information, and is also used to connect the memory controller signal of the functional unit for the core to access memory to the monitor, so that the monitor can obtain the core memory access information;

[0021] The dedicated out-of-order architecture includes a storage unit, a reading unit, an inspection unit, and an arithmetic unit;

[0022] The storage unit is used to store monitor data in memory, the reading unit is used to read data from memory, the inspection unit is used to check whether the software execution information meets the security rules, and the arithmetic unit is used to perform simple arithmetic and logical operations;

[0023] The information selector is used for the monitor to obtain core signals;

[0024] The monitor register is used to temporarily store the data of the monitor;

[0025] The cache is used to accelerate the process of the monitor accessing memory.

[0026] There are 64 monitor registers, each with a bit width of 64 bits. The monitor registers have the same bit width and a larger number compared to the core registers, and can better temporarily store software execution information and intermediate operation data of the monitor.

[0027] The security rule table contains a continuous memory block for storing legal information and security rule mappings. The legal information is used to identify whether software execution is legal, and the security rule mapping is used to query legal information.

[0028] The execution state of the core is called the core state. For example, the program counter value of the core. Setting the core state to 64 bits can better represent the core state in various scenarios. By looking up the security rule mapping based on the core state, the corresponding legal information can be found.

[0029] The 64-bit core state can be used to find legal information. The access mode of the security rule table can support any 64-bit core state. The 64-bit core state is evenly divided into four segments, each with 16 bits. There are a total of four levels of security rule mappings. Each segment of the core state represents the entry of a level of security rule mapping. Except for the first-level security rule mapping which has only one mapping, the security rule mappings of the remaining levels may contain more than two mappings. When querying the security rule table, given a core state, the first segment (lowest 16 bits) will be used to query the first-level security rule mapping. When the highest bit of the value being searched is 1, it indicates that the remaining 63 bits of the value being searched record the length and address of the legal information. When the highest bit of the value being searched is 0, the next higher-level entry will be used to search for the next-level security rule mapping until the highest bit of the value being searched is 1.

[0030] The working modes of the monitor include an offline stage before program execution and an online stage during program execution.

[0031] The offline stage includes writing the monitor program and program instrumentation by the user according to requirements. Program instrumentation means inserting new instructions into the original program.

[0032] The online stage includes obtaining software execution information and monitoring by the monitor during software runtime.

[0033] In the offline stage, the user writes the monitor program through the monitor instruction set to implement operations of different security policies (security policies represent from the top level what specifications the software execution needs to meet), and selects different software execution information.

[0034] In the offline phase, for the software programs to be monitored, specific instructions ExInfo for carrying additional software execution information (such as the types of core instructions) can be inserted into the programs. The specific instructions ExInfo are executed in the core, and the instruction encoding other than the operation code for distinguishing different instructions in the specific instructions ExInfo can be user-defined to carry additional information; the user can insert the specific instructions ExInfo at any position in the monitored software program.

[0035] The monitor instruction set includes read / write arithmetic instructions, control instructions, memory instructions, and security instructions; the instructions in the monitor instruction set have a unified length of 64 bits, where 6 bits are used as the operation code to distinguish different types of monitor instructions. The other parts of the instruction encoding are used as operands. Some typical operands include the immediate number (imm) directly participating in the operation in the instruction, the source register (rs) being operated on, the destination register (rd) storing the operation result, etc.

[0036] The arithmetic instructions include addition, subtraction, AND, comparison instructions, and shift instructions. The addition, subtraction, and AND are used to complete operations between registers and immediate numbers; the comparison instructions are used to complete 4 comparison methods, including greater than, less than, equal to, and not equal to; the shift instructions are used for shift operations, and are also used to combine left shift and right shift, as well as extract the high or low bits of data;

[0037] The control instructions include unconditional control instructions and branch control instructions. The unconditional control instructions are used to directly and unconditionally modify the program counter, and the branch control instructions are used to modify the program counter according to the comparison result of the source register and the immediate number;

[0038] The memory instructions include read instructions and write instructions. The user can select whether to use the cache for memory read / write operations by configuring the cache-valid operand in the instruction encoding; the cache-valid operand is used to identify whether to use the monitor cache;

[0039] The security instructions include information selection instruction, information waiting instruction, information splitting instruction, reset instruction and check instruction. The information selection instruction is used to select different software execution information as a request indication to obtain different software execution information data. After the selection signal is completed, the information waiting instruction is used to wait for valid software execution information. The information waiting instruction will automatically block the execution of subsequent monitor instructions and wait for the first-in-first-out buffer FIFO until valid software execution information. And after successfully waiting for the software execution information, the software execution information is written into the destination register; when the information waiting instruction waits for the high-bandwidth FIFO, the information waiting instruction will automatically write the data into the 56th register to the 63rd register within one clock cycle. Additionally, reading the first-in-first-out buffer FIFO serves as the start of another round of processing. The user clears all registers by setting the reg-clear operand in the instruction encoding to 1, and the reg-clear operand is used to identify clearing the monitor registers.

[0040] The information splitting instruction is used to split two or more pieces of information in a 64-bit into 8 data bits by bit within one clock cycle.

[0041] The reset instruction is used to perform a reset operation on the security bypass cache.

[0042] The check instruction is used to verify whether the software execution information is legal. The check instruction includes a series of operations for security rule checking. The operations include reading the security rule table to obtain legal software execution information, comparing the software execution information and the legal information. By completing two or more monitor instruction operations in one check instruction, the time for the monitor to fetch instructions is saved.

[0043] In the online stage, the software execution information is sent to the monitor in the form of physical signals by modifying the core design.

[0044] The security rule table can be automatically generated in the offline stage during program static analysis (a method of analyzing program code before program execution). The security rule table can find the address and length of legal information in the security rule mapping at the intermediate level, and the security rule table will be optimized offline; when two or more core states correspond to the same legal information, the security rule mappings corresponding to the core states will store the same legal information address and length.

[0045] The rule bypass cache has two levels. The first-level rule bypass cache records the core state and the software execution information to be checked. When a check instruction starts to execute, the first-level rule bypass cache is searched. If there is the same core state and the same software execution information to be checked as in the rule bypass cache, this check instruction will be removed. The second-level rule bypass cache records the memory addresses of legal information and the software execution information to be checked. When the first-level rule bypass cache does not record the same information, the second-level rule bypass cache will be queried. If there is the same legal information as in the second-level rule bypass cache and the legal information is used to check the same software execution information, this check instruction will be removed.

[0046] When a check instruction is executed, the first-level rule bypass cache is searched first. If it is hit, the check instruction will be completed immediately. Otherwise, the second-level rule bypass cache will be searched. If it is hit, the check instruction will also be completed immediately. Otherwise, the uncompleted check instruction will continue to execute. Both levels of the rule bypass cache are updated using the first-in-first-out mechanism, and the search and comparison of the rule bypass cache are performed in parallel.

[0047] The dedicated out-of-order architecture means that only one instruction is issued for execution in one clock cycle, and the execution of arithmetic instructions and control instructions only requires one clock cycle. For memory instructions, the user can configure the OoO-valid operand used to identify whether to use the out-of-order architecture to configure the data dependency problem in read and write instructions. If OoO-valid is 1, the read and write instructions will be executed out of order until the instructions end. If a new read or write instruction is fetched before the previous read or write instruction has finished execution, the monitor will be automatically blocked. If OoO-valid is equal to 0, the execution of read and write instructions will block the monitor until they are completed. For monitor instructions with special functions, the monitor will be automatically blocked until the execution is completed. The execution of check instructions is always out of order and will block the read and write instructions executed after the check instruction.

[0048] The parallel comparator can perform more than two comparison operations in one clock cycle. When a check instruction is executed, the legal information to be compared is read from the security rule table stored in memory or cache. When the bit width of the legal information is 8 bytes, the parallel comparator can compare a total of 8 bytes of information, and the user can configure the parallel comparator through the info-width operand used to identify the data bit width of the legal information.

[0049] The features of this invention that distinguish it from other solutions are as follows:

[0050] (1) Monitor Instruction Set. The present invention summarizes the common operations in different security policies and proposes a monitor instruction set. The monitor completes the operations required by different security policies by executing the instructions in this instruction set. Different from the instruction set of a general-purpose processor, the monitor instruction set is a lightweight and security-monitoring-oriented instruction set.

[0051] (2) Security-Assisted Design. The present invention proposes that security-assisted design includes data structures, hardware design, and architecture, aiming to accelerate the processing process of the monitor.

[0052] Advantages: Through the above new features, the superiority of the present invention compared with other existing solutions is as follows:

[0053] (1) Higher flexibility. It can implement a wider range of security policies.

[0054] (2) Higher performance. The performance overhead of the present invention is similar to that of a dedicated hardware monitor.

[0055] (3) Higher security. Benefiting from the high flexibility and high performance of the system, it can implement security policies with high computational requirements. Brief Description of the Drawings

[0056] The following further specifically describes the present invention in conjunction with the drawings and specific embodiments, and the above and / or other advantages of the present invention will become clearer.

[0057] Figure 1 It is a schematic diagram of the overall overview of the ProMiSE system of the present invention.

[0058] Figure 2 It is a schematic diagram of the rule table structure.

[0059] Figure 3 It is a schematic diagram of an instance of the security rule table.

[0060] Figure 4 It is a schematic diagram of an instance of the rule bypass cache.

[0061] Figure 5a It is a schematic diagram of the program instrumentation and monitor program under the security policy of white-list.

[0062] Figure 5b It is a schematic diagram of the program instrumentation and monitor program under the security policy of white-list. Detailed Embodiments

[0063] The present invention provides a hardware monitor device applied to software security execution. The present invention first summarizes the conditions for security monitoring:

[0064] (1) Security policy. The security policy represents from the top level what specifications the software execution needs to meet. For example, control-flow integrity (CFI) is a security policy that stipulates that the execution of each branch instruction in a program must meet the programmer's intention.

[0065] (2) Security rule. The security rule is a specification of the legality of the execution details of each software program. The security rule describes from the detailed level what conditions the software execution needs to meet. For example, in CFI, the security rule stipulates that the destination address of each branch instruction must be in a set of legal addresses. The method proposed by the present invention will analyze and obtain the set of legal addresses before the program execution. The present invention describes the security rule as a basic correspondence: core state → {legal information 0, legal information 1...}. For example, in CFI, the security rule is expressed as: branch instruction address → {legal destination jump address 0, legal destination jump address 1,...}. Through the core state, the corresponding legal information can be found. The symbol → represents correspondence.

[0066] (3) Software execution information. The software execution information is the information during the real-time execution of the software. For example, the value of a register or the destination address of a memory access at a certain moment. These software execution information can all be obtained from the hardware signals in the system.

[0067] The present invention also provides a hardware monitor method applied to software security execution, including an offline stage before the program execution and an online stage during the program execution. The offline stage includes monitor program writing and program instrumentation performed by the user according to requirements. The online stage includes the acquisition of software execution information and the monitoring of the monitor during software operation.

[0068] In the offline stage, the user can write a monitor program through the monitor instruction set proposed by the present invention, so as to implement operations of different security policies. The monitor instructions not only include basic memory read / write, lightweight control and arithmetic instructions, but also include some security auxiliary instructions that can help the user complete a series of security-related operations more efficiently. This step is shown in Figure 1 Step 1.

[0069] For some software programs that need to be monitored, the present invention provides a method of adding additional information (such as identifying the types of core instructions) by adding additional specific instructions to the program. This instruction is called ExInfo in the present invention. Different from the monitor instructions executed in the monitor, this instruction is executed in the core, and part of its instruction encoding can be defined by the user to carry additional information. The present invention provides a software for automatic program instrumentation, and the user can insert ExInfo at any position in the monitored software program according to needs. At the same time, some security rules will also be obtained through offline analysis of the software program. This step is shown in Figure 1 Step 2 of

[0070] In the online phase, the present invention sends software execution information to ProMiSE in the form of physical signals by modifying the core design, such as core program count values, core memory access destination addresses, core register values, and additional information in ExInfo. This step is shown in Figure 1 Step 3 of. Note that these signals can be easily added according to needs. Through the monitor instruction set proposed by the present invention, the user can easily select different software execution information. And through Figure 1 A series of security-assisted designs shown in Step 4, the user can efficiently implement security policies. These designs include a dedicated out-of-order architecture for improving performance, a data structure of a security rule table for efficiently recording security rules, a monitor cache controllable by monitor instructions, a configurable parallel comparator for reducing monitoring latency, and a rule bypass cache for reducing redundant monitoring operations. At the same time, there are also some infrastructures, such as monitor registers similar to the registers in a general-purpose processor. There are a total of 64 monitor registers, and each bit width is 64 bits.

[0071] Monitor instruction set

[0072] The present invention fully summarizes the common operations in different security policies and proposes a monitor instruction set. This instruction can achieve a good balance between flexibility and performance. The length of the monitor instruction is uniformly 64 bits, and 6 bits of it are used as the operation code to distinguish different types of monitor instructions. The other parts in the instruction encoding are used as operands. Some typical operands include immediate numbers (imm) directly participating in operations, source registers (rs) of the operated registers, destination registers (rd) for storing operation results, etc. These registers are all monitor registers. In addition, there are some special operands, such as a 1-bit imm-valid operand in Add for identifying whether to use an immediate number, as shown in Table 1.

[0073] Table 1

[0074]

[0075]

[0076] Arithmetic instructions. Considering that only some basic arithmetic operations are required for real-time security monitoring, the present invention proposes lightweight arithmetic instructions, including addition, subtraction, and AND (Add, Sub, and And), which can support operations between registers and immediate numbers. There is also a compare instruction, Compare, which can support a total of 4 comparison methods, including greater than, less than, equal to, and not equal to. There is also a shift instruction, Shift, which not only supports conventional shift operations but also supports a combination of left shift and right shift, which is mainly used for extracting high or low bits of data.

[0077] Control instructions. To ensure flexibility, the monitor instruction set proposed by the present invention includes control instructions. One is an unconditional control instruction, Jump, which can directly and unconditionally modify the program counter of the monitor. The other is a branch control instruction, Branch, which can modify the program counter of the monitor according to the comparison result of the source register and the immediate number. The comparison modes support greater than, less than, equal to, and not equal to, and users can select by configuring the mode operand used to flag the comparison mode.

[0078] Memory instructions. The monitor instruction set provides basic memory read and write instructions, including a read instruction, Load, and a write instruction, Store. And users can choose whether to use the monitor cache for memory read and write operations according to the locality of the data to be read and written, through the operand cache-valid.

[0079] Security instructions. This type of instruction is designed to meet the relevant requirements of security monitoring.

[0080] Information selection instruction, Info-select. This instruction can select different software execution information (extra information valid, branch valid) as request indicators to obtain different software execution information data (core program counter value, core memory access destination address, core register value, and extra information). And in order to better meet the requirements of different security policies, the present invention provides a high-bandwidth and a low-bandwidth first-in-first-out buffer (FIFO), as shown in step 4 of Figure 1 . The info-fifo operand indicates which FIFO the instruction writes the software execution information data to. In the present invention, a total of 10 types of software execution information are supported as request indicators, and 47 types of software execution information are supported as data. In addition, in order to be able to select software execution information in a fine-grained manner, the present invention sets the width of each data signal to 16 bits, which provides users with sufficient flexibility to manage different software execution information.

[0081] Info-wait instruction for information waiting. After the selection signal is completed, the Info-wait instruction in the monitor instruction set is designed to wait for valid software execution information. This instruction automatically blocks the execution of subsequent monitor instructions and waits for the FIFO until valid software execution information is available. And after successfully waiting for the software execution information, the software execution information is written into the destination register. Considering the balance between hardware overhead and performance in the present invention, when the FIFO waited by Info-wait is a high-bandwidth FIFO, this instruction can automatically write data into 8 registers (register 56 to register 63) within one clock cycle. Additionally, reading the FIFO serves as the start of another round of processing. The user can clear all registers by setting the reg-clear operand in the instruction encoding, which is used to identify whether to clear the monitor registers, to 1.

[0082] Info-split instruction for information splitting. Considering that usually, multiple types of information are in one register, if the monitor arithmetic instruction is used for splitting operations, it will take many clock cycles and be inefficient. Based on this background, Info-select can split a 64-bit data into 8 data bits by bit within one clock cycle.

[0083] Reset instruction. The user can perform a reset operation on the secure bypass cache through the Reset instruction.

[0084] Check instruction. This instruction is used to check whether the software execution information is legal. In the operation of security monitoring, the most important step is to check whether the software execution information complies with the security rules. This step can be achieved through the combination of different monitor instructions mentioned above. Then, because a series of operations for security rule checking have high correlations and high computing requirements, the present invention proposes the Check instruction to improve the system performance without sacrificing flexibility. This instruction includes a series of operations for security rule checking. By completing multiple monitor instruction operations in one instruction, it can effectively save the time for the monitor to fetch instructions.

[0085] Security auxiliary design

[0086] Security Rule Table

[0087] For some security policies with high requirements, security rules are too large to be stored in memory. However, storing security rules in memory poses two problems. One is that these security rules often have no regularity, making it difficult to store them effectively (the sizes of legal information in security rules are different, and the core states used to find this legal information are also different, which could be any number). The second challenge is how to efficiently access security rules. Based on these two problems, the present invention proposes a new data structure, the security rule table.

[0088] Figure 2 Figure 4 shows the basic structure of the rule table. The rule table contains a continuous memory block for storing legal information and a security rule mapping. By looking up the security rule mapping through the core state, the corresponding legal information can be found. The security rule mapping proposed in the present invention is very similar to the page table of an operating system. In the design of the present invention, a 64-bit core state can be used to find legal information, and the access mode of the security rule table can support a core state with a larger bit width. The 64-bit core state is evenly divided into four segments, each with 16 bits. Similarly, the security rule mapping has a total of four levels, so each segment of the core state represents the entry of the security rule mapping at that level. Except that the first-level security rule mapping has only one mapping, the security rule mappings at the remaining levels may contain multiple mappings. When querying the security rule table, given a core state, its lower 16 bits will be used to query the first-level security rule mapping. When the highest bit of the value being looked up is 1, this indicates that the remaining part of the value records the length and address of the legal information. The entire table lookup process ends here, and this process is shown in Figure 2 the dotted-line table lookup process in Figure 5. On the contrary, the entry at a higher level will be used to look up the next-level security rule mapping until the highest bit of the value being looked up is 1.

[0089] The security rule table can be automatically generated during the static analysis of the program in the offline stage. The process of generating this table is similar to that of the page table, except that the security rule table can find the address and length of the legal information in the security rule mapping at the intermediate levels, while the page table can only find the result at the last level. In addition, the security rule table will be optimized offline. When multiple core states correspond to the same legal information, the security rule mappings corresponding to these core states will all store the same legal information address and length. In the design of the present invention, the security rule table is not always used. For example, in CFI, the security rule table is only used to record the legal addresses of indirect jump instructions, rather than the legal return addresses of functions.

[0090] Figure 3An example of a specific security rule table is shown. In this example, a total of three core states (corresponding to branch 0, branch 1, and branch 2) are shown as examples for querying legal execution information. When the core state is 0x10038, the lower 16 bits of 0x0038 will first be used to query the first-level security rule mapping, and the highest bit of the queried value is 1. Then the address and length of the legal information are 0x0 and 2. The address and length of the legal information will be used to query the legal information {0x100020, 0x100048}. If the core state is 0x100018, because the lower 16 bits of multiple core states are 0x0018, the second core state 0x10 will be used to query the second-level security rule mapping. At this time, the address and length of the security information are 0x10 and 1.

[0091] Through the data structure of the security rule table proposed by the present invention, any legal execution information can be obtained through at most 4 security rule mapping queries. And the security rule table will only be allocated when needed, and thanks to the offline optimization, the memory overhead of the security rules is within a reasonable range.

[0092] Cache

[0093] For modern processors, multi-level caches can greatly reduce the latency of memory access. The present invention also adopts a similar method. The present invention proposes that the cache adopts a write-through and single-way mapping mechanism. Considering that different data has different locality, for example, the security rule table has high locality. However, some data with low locality may interfere with the memory access operations of high-locality data, resulting in a decrease in the hit rate of the monitor cache.

[0094] Based on the above characteristics, according to the lightweight characteristics of the monitor program, when the user uses the Load and Store monitor instructions, they can choose whether to use the monitor cache for memory access by configuring cache-valid. This hardware design can make the monitor cache more efficient.

[0095] Rule bypass cache

[0096] During the software execution process, dense software execution information needs to be checked by looking up the security rule table, which will bring a large performance overhead. However, because there are many similar execution patterns during the software execution process, there are a large number of repeated check operations. To remove the redundancy of the checks, the present invention proposes a rule bypass cache. When Check is executed, the rule bypass cache will be searched first. Once this Check has been recorded in the rule bypass cache, the rule bypass cache is hit, this Check will be completed immediately and the next monitor instruction will start to execute.

[0097] There are two levels of rule bypass caches. The first-level rule bypass cache records the core state and the software execution information to be checked. At the beginning of the Check execution, the first-level rule bypass cache is searched. If there are the same core state and the same software execution information to be checked as in the rule bypass cache, this Check will be removed. The second-level rule bypass cache records the memory addresses of legal information and the software execution information to be checked. When the same information has not been recorded in the first-level rule bypass cache, the second-level rule bypass cache will be queried. If the same legal information in the second-level rule bypass cache is used to check the same software execution information, then this Check will also be removed.

[0098] When the Check is executed, the first-level rule bypass cache is searched first. If it is hit, the Check will be completed immediately. Otherwise, the second-level rule bypass cache will be searched. If it is hit, the Check will also be completed immediately. Otherwise, the subsequent operations of the Check will continue to be executed. The two-level rule bypass cache is updated using the First-In-First-Out (FIFO) mechanism. And the search and comparison of the rule bypass cache are carried out in parallel. This design enables the search and comparison of the rule bypass cache to only require one clock cycle. During the execution process, the rule bypass cache is dynamically updated. To avoid interference caused by historical information left during the execution of the previous monitor program, the user can reset the security bypass cache through Reset.

[0099] Figure 4 An example of a rule bypass cache is shown. This example shows the process of searching the rule bypass cache three times. The software execution information of the first Check is 0x1400, and the core state is 0x1000. At this time, the first-level bypass cache is not hit, and 0x8010, 0x1400 are also not hit in the second-level bypass cache. Therefore, the subsequent Check operations will continue to be executed. The second Check hits in the second-level bypass cache, so the time for the subsequent Check operations will be saved. Similarly, the third Check hits in the first-level bypass cache. From this example, it can be seen that the rule bypass cache proposed in this invention can improve performance by removing duplicate Check instruction operations.

[0100] Dedicated out-of-order architecture

[0101] In modern processor designs, out-of-order execution is adopted to increase performance, and a similar method is also taken in this invention. However, the out-of-order architecture in general-purpose processors often consumes a large amount of hardware resources and greatly increases the complexity of the entire system. To address this problem, this invention proposes a dedicated out-of-order architecture that achieves a good balance between performance and hardware overhead.

[0102] In the out-of-order structure of a general-purpose processor, a large amount of hardware resources are required to implement hardware structures such as reordering caches, reservation stations, and general data buses. However, due to the lightweight characteristics of the monitor program, users can configure the dependencies between different data, so unnecessary hardware overhead is saved in this invention. The architecture proposed in this invention issues only one instruction for execution in one clock cycle. Among the different types of monitor instructions shown in Table 1, the execution of arithmetic instructions and control instructions only requires one clock cycle, so there is no data dependency problem in these instructions. For memory instructions, users can configure the data dependency problem in read instructions and write instructions by configuring the OoO-valid operand used to identify whether to use the out-of-order architecture; if OoO-valid is 1, Load and Store instructions will be executed out of order until the instructions end. In the design of this invention, if a new Load or Store is fetched while a previous Load or Store instruction has not been completed, the monitor will be automatically blocked. On the contrary, if OoO-valid is equal to 0, the execution of Load and Store will block the monitor until it is completed. For some monitor instructions with special functions, such as Info-select and Info-wait, they will automatically block ProMiSE until their execution is completed. The execution of Check is always out of order and will block Load and Store executed after it.

[0103] Parallel comparator

[0104] When using Check to check whether software information meets security rules, it is necessary to compare the software execution information with legal information. There may be multiple pieces of legal information (which means multiple comparisons need to be made), and each comparison operation is carried out independently. Therefore, this invention proposes Figure 1 the parallel comparator in Figure 1 , which can perform multiple comparison operations in one clock cycle.

[0105] When Check is executed, the legal information to be compared is read from memory or cache, and the data bit width is 8 bytes. To meet this situation, the parallel comparator designed in this invention can compare a total of 8 bytes of information. Due to different security policies, these 8 bytes of information may contain multiple parts to be compared, and users can configure the parallel comparator through the info-width operand used to identify the bit width of legal information. For example, when info-width is 2, it means that each part to be compared is 2 bytes at this time, and there are 4 parts to be compared in the 8 bytes of information in total. At this time, the parallel comparator will perform 4 comparison operations in parallel in one clock cycle.

[0106] The security-aided design includes a cache, a dedicated out-of-order architecture, a parallel comparator, a security rule table, and a rule bypass cache, which are devices for improving the performance of the device and are all non-essential devices. Devices without the security-aided design are also within the protection scope of the present invention.

[0107] Embodiment

[0108] In this embodiment, a 64-bit, in-order execution, 5-stage pipelined RISC-V processor and a ProMiSE hardware monitor are deployed on a Virtex-7 FPGA VC707 Evaluation Kit development board. The processor has 16KB instruction and data caches, 1GB of DDR4 memory, and 32 cache miss status handling registers (MSHRs). And LLVM is used as the compiler, and control analysis software (Reference: FastCFI GitHub Repository, https: / / github.com / flwave / FastCFI, 2019.) and SVF software (Reference: Sui Y, Xue J. SVF: interprocedural static value-flow analysis in LLVM [C] / / Proceedings of the 25th international conference on compiler construction. 2016: 265-266.) are used. The present invention performs performance tests using the SPEC CPU 2006 test suite.

[0109] The present invention has implemented a total of five security policies, including a shadow stack for recording the legitimate return addresses of functions, a white-list that only allows read instructions within the whitelist to read sensitive memory regions, control flow integrity (CFI) that restricts the transfer of the instruction flow to legitimate target addresses, lightweight dynamic information flow tracking (LW-DIFT) in HDFI (References: Song C, Moon H, Alam M, et al. HDFI: Hardware-assisted data-flow isolation [C] / / 2016 IEEE Symposium on Security and Privacy (SP). IEEE, 2016: 1-17.), and data flow integrity (DFI) that stipulates that the data read by each read instruction can only be written by specific legitimate write instructions. And the present invention summarizes the characteristics of these security policies implemented on ProMiSE. The characteristics of these security policies include security, security scope (for control flow data or non-control flow data), computational requirements, monitor mechanism (event-based or label-based), security rules (remaining unchanged or dynamically updated during software execution, for example, the legitimate return addresses of functions in the shadow stack are continuously updated according to function calls), and program instrumentation.

[0110] Table 2

[0111]

[0112] Figure 5a and Figure 5b shows the details of program instrumentation and the monitor program under the security policy of the white-list.

[0113] The Whilte-list is a security policy that monitors whether there are illegal read instructions reading data in sensitive areas through the sensitive memory regions and white-list read instructions specified by the user.

[0114] To implement various security policies, program instrumentation is carried out according to the user's requirements. For example, in the white-list, in order to obtain the memory region address that is not easily obtained before program execution, in this embodiment, ExInfo is inserted after the write instruction where the sensitive area is first written in the program to mark the information of the sensitive area. And, ExInfo is inserted after non-white-list read instructions to mark the read instructions that need to be monitored.

[0115] The monitor program is as Figure 5a and Figure 5bAs shown, various security policies can be achieved through appropriate user configuration. In the white-list, first, the memory addresses of read / write instructions and the memory of sensitive areas need to be obtained through Info-select. In this instruction, by configuring ExInfo as a request indicator, ExInfo data and memory addresses can be obtained (line 1), and the memory addresses are written into a high-bandwidth FIFO (line 2, because the data width exceeds the width of the low-bandwidth FIFO). In line 3, Info-split will decompose the composite information in ExInfo, such as region length and tags, into different monitor registers. If the Branch in line 4 determines that the tag is a reference access, it will jump to line 9 to initialize the start address of the sensitive area; otherwise, it will jump to the Branch in line 5. If it determines that the tag is the region length, it will jump to line 11 to initialize the end address. Otherwise, it will jump to line 6 to compare whether the memory address of this read instruction is within the sensitive area to determine whether an attack has occurred.

[0116] The implementation results show the comparison between the present invention and other flexible hardware monitors, as shown in Table 3:

[0117] Table 3

[0118]

[0119]

[0120] The "-" in Table 3 indicates that the corresponding information is not mentioned in the corresponding work. The performance overhead in the table is based on the respective articles. The negative performance overhead in the experimental results of the present invention is due to errors and the influence of random numbers during the experiment.

[0121] From the above table, it can be seen that compared with existing flexible monitors, ProMiSE proposed by the present invention can implement more types of security policies, covering security policies that can defend against control-flow data attacks and non-control-flow data attacks, and security policies with security levels from low to high. And ProMiSE can implement both tag-based monitoring and event-based monitoring. Similarly, compare the performance overhead of ProMiSE and the current most advanced dedicated hardware monitors, as shown in Table 4:

[0122] Table 4

[0123] Security Policy ProMiSE Performance Overhead State-of-the-Art Dedicated Monitor Performance Overhead Shadow Stack -0.2％ ～0％ White-List -0.1％ ～0％ CFI 2.9％ ～0％ LW-DIFT 19.7％ <2％ DFI 23.4％ ～17.8％

[0124] From Table 4, it can be seen that the performance overhead of ProMiSE is similar to that of the most advanced dedicated monitors.

[0125] The present invention conducts security tests on the system. The tools used include the RIPE test suite, fine-grained control data flow attacks (since the control data flow attacks in the RIPE test suite can be detected by many inaccurate security policies, the present invention uses fine-grained data flow attacks to test whether the system can accurately detect illegal indirect jump addresses), Heartbleed (a non-control flow data attack), Nullhttpd (a heap overflow vulnerability), and fine-grained non-control flow data attacks (in this attack, there are multiple illegal write instructions, requiring the monitor to have accurate monitoring capabilities). Table 5 shows the monitoring situations of different security policies implemented by ProMiSE for different attacks.

[0126] Table 5

[0127]

[0128]

[0129] The monitoring latency is defined as the number of clock cycles from when the monitor obtains the corresponding software execution information to when the information processing is completed.

[0130] As can be seen from the above table, all five security policies implemented by ProMiSE can accurately detect attacks, and the monitoring latencies of all five security policies are low enough.

[0131] The present invention provides a hardware monitor method and device applied to software security execution. There are many methods and ways to specifically implement this technical solution. The above is only the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention. Each component not clearly defined in this embodiment can be implemented using existing technologies.

Claims

1. A hardware monitor device for software security execution, characterized in that: Includes a modified core, information selector, dedicated out-of-order architecture, parallel comparators, monitor registers, data structures, caches, rule bypass caches, first-in-first-out buffers (FIFOs), and monitor instruction sets; The dedicated out-of-order architecture is used to improve performance; The parallel comparator is used to reduce monitoring delay; The data structure is used to record a security rule table containing security rules; The rule bypass cache is used to reduce redundant monitoring operations; The first-in-first-out buffer FIFO includes two types, namely a high-bandwidth FIFO with a bit width of 512 bits and a low-bandwidth FIFO with a bit width of 64 bits; The modified core is used to connect a program counter signal of a core counting instruction address to a monitor so that the monitor can obtain core instruction address information, and is also used to connect a memory controller signal of a functional unit of the core accessing memory to the monitor so that the monitor can obtain core memory access information; The dedicated out-of-order architecture includes a storage unit, a read unit, a check unit, and an arithmetic unit; The storage unit is used to store the monitor data into the memory, the reading unit is used to read the data from the memory, the checking unit is used to check whether the software execution information meets the security rules, and the arithmetic unit is used to perform simple arithmetic and logical operations; The information selector is used for the monitor to obtain the core signal; The monitor register is used to temporarily store monitor data; The cache is used to speed up the process of the monitor accessing the memory; The execution state of the core is called the core state. The 64-bit core state can be used to find legal information. The access mode of the security rule table can support any core state with a bit width of 64 bits. The 64-bit core state is evenly divided into four segments, each with 16 bits. There are four levels of security rule mapping. Each segment of the core state represents the entry of a level of security rule mapping. Except for the first-level security rule mapping which has only one mapping, the security rule mappings of other levels contain more than two mappings. When the security rule table needs to be queried, given a core state, the first segment will be used to query the first-level security rule mapping. When the highest bit of the searched value is 1, it indicates that the remaining 63 bits of the searched value record the length and address of the legal information. When the highest bit of the searched value is 0, the higher-level entry will be used to search for the next-level security rule mapping until the highest bit of the searched value is 1. The monitor instruction set includes read and write arithmetic instructions, control instructions, memory instructions, and security instructions. The length of instructions in the monitor instruction set is uniformly 64 bits, of which 6 bits are used as opcodes to distinguish different types of monitor instructions. The remaining parts of the instruction encoding are used as operands, and the operands include the immediate value imm that directly participates in the operation in the instruction, the source register rs to be operated, and the destination register rd to store the operation result. The rule bypass cache has two levels. The first level of the rule bypass cache records the core state and the execution information of the software being checked. When the check instruction starts to execute, the first level of the rule bypass cache will be searched. If the same core state and the same software execution information are found in the rule bypass cache, the check instruction will be removed. The second-level rule bypass cache records the memory address of the legal information and the software execution information being checked. When the same information has not been recorded in the first-level rule bypass cache, the second-level rule bypass cache will be queried. If there is legal information that is the same as that in the second-level rule bypass cache, and the legal information is used to check the same software execution information, this check instruction will be removed.

2. The hardware monitor device for software security execution according to claim 1, characterized in that: There are 64 monitor registers, each with a bit width of 64 bits.

3. The hardware monitor device for software security execution according to claim 2, characterized in that: The security rule table includes a continuous memory for storing legal information and security rule mapping, the legal information is used to identify whether the software execution is legal, and the security rule mapping is used to query the legal information.

4. The hardware monitor device for software security execution according to claim 3, characterized in that: The working mode of the monitor includes an offline phase before program execution and an online phase during program execution; The offline phase includes writing a monitor program and inserting a program according to the user's needs. The program insertion means inserting new instructions into the original program. The online phase includes obtaining software execution information and monitoring by a software runtime monitor.

5. The hardware monitor device for software security execution according to claim 4, characterized in that: In the offline phase, users write monitor programs through the monitor instruction set to implement operations of different security policies and select different software execution information; In the offline phase, for software programs that need to be monitored, a specific instruction ExInfo is inserted into the program to carry additional software execution information. The specific instruction ExInfo is executed in the kernel. In addition to the opcode used to distinguish different instructions, the instruction code in the specific instruction ExInfo can be defined by the user to carry additional information. Users can insert specific instructions ExInfo at any location in the monitored software program according to their needs.

6. The hardware monitor device for software security execution according to claim 5, characterized in that: The arithmetic instructions include addition, subtraction, AND, comparison instructions, and shift instructions. The addition, subtraction, and AND instructions are used to complete operations between registers and immediate values; the comparison instructions are used to complete four comparison modes, including greater than, less than, equal to, and not equal to; the shift instructions are used for shift operations, and are also used to combine left shift and right shift, as well as extract the high or low bits of data; The control instructions include unconditional control instructions and branch control instructions, the unconditional control instructions are used to directly modify the program counter, and the branch control instructions are used to modify the program counter according to the comparison result of the source register and the immediate value; The memory instructions include read instructions and write instructions. The user can choose whether to use the cache for memory read and write operations by configuring the cache-valid operand in the instruction code; the cache-valid operand is used to identify whether to use the monitor cache; The security instructions include an information selection instruction, an information waiting instruction, an information splitting instruction, a reset instruction, and a check instruction. The information selection instruction is used to select different software execution information as a request indication to obtain different software execution information data. After the selection signal is completed, the information waiting instruction is used to wait for valid software execution information. The information waiting instruction automatically blocks the execution of subsequent monitor instructions, waits for the first-in-first-out buffer FIFO until valid software execution information is received, and writes the software execution information to the destination register after successfully waiting for the software execution information. When the information waiting instruction waits for the high-bandwidth FIFO, the information waiting instruction automatically writes the data to the 56th to 63rd registers respectively within one clock cycle, and reads the first-in-first-out buffer FIFO as the start of another round of processing. The user clears all registers by setting the reg-clear operand in the instruction code to 1. The reg-clear operand is used to indicate clearing the monitor register. The information splitting instruction is used to split two or more information located in a 64-bit into 8 data bits in one clock cycle; The reset instruction is used to reset the security bypass cache; The inspection instruction is used to verify whether the software execution information is legal. The inspection instruction includes a series of operations for security rule checking, including reading the security rule table to obtain software legal execution information, comparing the software execution information and legal information, and completing more than two monitor instruction operations in one inspection instruction, thereby saving the time for the monitor to fetch instructions.

7. The hardware monitor device for software security execution according to claim 6, characterized in that: In the online phase, the core design is modified to send software execution information to the monitor in the form of physical signals; The security rule table can be automatically generated during the offline static analysis of the program. The security rule table can find the address and length of legal information in the intermediate level security rule mapping, and the security rule table will be optimized offline. When two or more core states correspond to the same legal information, the security rule mappings corresponding to the core states will store the same legal information address and length. When a check instruction is executed, the first-level rule bypass cache is searched. If a match is found, the check instruction is completed immediately. Otherwise, the second-level rule bypass cache is searched. If a match is found, the check instruction is also completed immediately. Otherwise, the unfinished check instructions continue to be executed. Both levels of the rule bypass cache are updated using a first-in-first-out mechanism, and the search and comparison of the rule bypass cache are performed in parallel. The dedicated out-of-order architecture means that only one instruction is issued for execution in one clock cycle, and the execution of the arithmetic instructions and control instructions only requires one clock cycle; for memory instructions, the user can configure the data dependency problem in the read instructions and write instructions by configuring the OoO-valid operand used to identify whether to use the out-of-order architecture; if OoO-valid is 1, the read instructions and write instructions will be executed out of order until the instruction ends; if the previous read instruction or write instruction has not been executed yet and a new read instruction or write instruction is fetched, the monitor will be automatically blocked; if OoO-valid is equal to 0, the execution of the read instruction and write instruction will block the monitor until the execution is completed; for special function monitor instructions, the monitor will be automatically blocked until the execution is completed; the execution of the check instruction is always out of order, and the read instruction and write instruction executed after the check instruction will be blocked; The parallel comparator can perform more than two comparison operations within one clock cycle. When checking instruction execution, the legal information that needs to be compared is read from the security rule table stored in the memory or cache. When the bit width of the legal information is 8 bytes, the parallel comparator can compare a total of 8 bytes of information. The user can configure the parallel comparator through the info-width operand used to identify the bit width of the legal information data.

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