Methods, systems, storage media, and electronic devices for very large scale integration

Abstract

The present disclosure relates to a method, system, storage medium and electronic device for very large scale integrated circuit; the method for very large scale integrated circuit obtains timing information TNS of the entire netlist of the very large scale integrated circuit; all nodes are sorted according to the topology structure of the integrated circuit, and nodes with the same serial number are placed in the same queue; all sorted nodes are traversed in reverse according to the number of queues; the size reduction preprocessing is performed on all nodes in the same queue, and the slack change value of the output pin of the current node and the next level node is obtained; the slack change value of the output pin of the current node and the next level node is checked, the current node with the slack change value of the output pin meeting the requirements is subjected to size reduction processing; the timing information of the current node and the next level node is updated, the timing information new_TNS of the entire netlist is reobtained; the timing information new_TNS and TNS are compared, and the area power consumption in the physical optimization of the very large scale integrated circuit is optimized according to the comparison result. The problem of excessive area power consumption in the physical optimization design process under the condition of unchanged timing can be solved.

Description

Technical Field

[0001] This invention belongs to the field of automation technology for physical design of very large-scale integrated circuits, and specifically relates to a method, system, storage medium and electronic device for very large-scale integrated circuits. Background Technology

[0002] With the development of modern very large-scale integrated circuits, the number of units contained on a chip is increasing. For example, as the performance of mobile phone chips improves, the number of transistors they contain is also increasing. The most advanced mobile phone chips have reached the level of tens of billions of transistors. The challenges that follow are the total area of ​​chip units and power consumption.

[0003] Currently, commonly used physical design optimization methods often focus more on timing optimization, which is usually accomplished by inserting buffers or replacing larger cells. This obviously leads to an excessively large total cell area, resulting in problems such as excessive area power consumption. Excessive power consumption is unacceptable in modern chip requirements.

[0004] While ensuring that the timing remains unchanged, how to reduce the area of ​​each cell as much as possible to reduce the total cell area and thus reduce power consumption is also one of the urgent problems to be solved.

[0005] The background description is provided for the purpose of understanding the relevant technologies in this field and is not intended as an admission of prior art. Summary of the Invention

[0006] This invention overcomes one of the shortcomings of the prior art and provides a method and related equipment for very large-scale integrated circuits. It can reduce the total area of ​​the integrated circuit by reducing the area of ​​each unit node, thereby solving the problem of excessive area power consumption caused by ensuring that the timing remains unchanged during the physical optimization design process.

[0007] According to one aspect of this disclosure, a method for very large-scale integrated circuits is proposed, the method comprising:

[0008] Obtain the timing information (TNS) of the entire netlist of the VLSI;

[0009] Based on the topology of the VLSI, all nodes in the entire netlist are sorted, and nodes with the same sequence number are placed in the same queue.

[0010] For all sorted nodes, perform a reverse traversal based on the queue number;

[0011] For all nodes in the same queue, a size reduction preprocessing is performed to obtain the slack change value of the output pin of the current node and the next level node;

[0012] Check the slack change value of the output pins of the current node and the next level node of the current node, and reduce the size of the current node whose slack change value of the output pins of the current node and the next level node of the current node meets the requirements.

[0013] Update the timing information of the current node and the next-level node of the current node, and reacquire the timing information new_TNS of the entire netlist;

[0014] The timing information new_TNS and timing information TNS of the entire netlist are compared, and the area and power consumption of the VLSI are optimized based on the comparison result.

[0015] In one possible implementation, sorting all nodes of the entire netlist according to the topology of the VLSI includes:

[0016] According to the topology of the VLSI, the sequence number of the starting node is set to 1, and the downstream nodes of the starting node are incremented by 1 in sequence until the end node of the VLSI.

[0017] In one possible implementation, the slack changes of the output pins of the current node and the next-level node meet the following requirements:

[0018] The slack change values ​​of the output pins of the current node and the next-level node of the current node conform to the size reduction rule, and the current node is subjected to size reduction processing.

[0019] In one possible implementation, the slack values ​​of the output pins of the current node and the next-level node of the current node conform to a size reduction rule, including:

[0020] If the slack value of the output pin of the current node is greater than 0, the slack value of the output pin after the size of the current node is reduced is still greater than 0;

[0021] Alternatively, if the slack value of the output pin of the current node is less than 0, then the slack value of the output pin after the current node size is reduced is greater than or equal to the initial slack value.

[0022] Furthermore, the slack value of the output pin of the next-level node of the current node did not deteriorate.

[0023] In one possible implementation, the slack value of the output pin of the next-level node of the current node does not deteriorate, including:

[0024] If the slack value of the output pin of the next level node of the current node is greater than 0, the slack value of the output pin of the next level node of the current node will still be greater than 0 after the size of the current node is reduced.

[0025] Alternatively, if the slack value of the output pin of the next-level node of the current node is less than 0, after the size of the current node is reduced, the slack value of the output pin of the next-level node of the current node is greater than or equal to the initial slack value of the next-level node of the current node before the size of the current node is reduced.

[0026] In one possible implementation, comparing the timing information new_TNS and the timing information TNS of the entire netlist, and optimizing the area and power consumption of the VLSI based on the comparison result, includes:

[0027] When the timing information new_TNS is greater than or equal to the timing information TNS, the current node undergoing size reduction processing is restored to its previous state until the timing information new_TNS is less than the timing information TNS, thereby optimizing the area and power consumption of the VLSI.

[0028] In one possible implementation, comparing the timing information new_TNS and the timing information TNS of the entire netlist, and optimizing the area and power consumption of the VLSI based on the comparison result, further includes:

[0029] When the timing information new_TNS is less than the timing information TNS, the current node that has undergone size reduction processing is restored to its previous state, thereby optimizing the area and power consumption of the VLSI.

[0030] According to another aspect of this disclosure, an area and power consumption optimization system for very large-scale integrated circuits is proposed, the system comprising:

[0031] The acquisition module is used to acquire the timing information (TNS) of the entire netlist of the VLSI;

[0032] The sorting module is used to sort all nodes in the entire netlist according to the topology of the VLSI, and place nodes with the same sequence number in the same queue.

[0033] The reverse traversal module is used to perform reverse traversal of all sorted nodes according to the number of queues.

[0034] The size reduction preprocessing module is used to perform size reduction preprocessing on all nodes in the same queue to obtain the slack change value of the output pin of the current node and the next level node;

[0035] The size reduction processing module is used to check the slack change value of the output pins of the current node and the next level node of the current node, and to perform size reduction processing on the current node whose slack change value of the output pins of the current node and the next level node of the current node meets the requirements;

[0036] The timing information update module is used to update the timing information of the current node and the next-level node of the current node, and to re-acquire the timing information new_TNS of the entire netlist;

[0037] The comparison module is used to compare the timing information new_TNS and the timing information TNS of the entire netlist, and optimize the area and power consumption of the VLSI based on the comparison result.

[0038] According to another aspect of this disclosure, a storage medium is provided on which a computer program is stored, which, when executed by a processor, implements the method described above.

[0039] According to another aspect of this disclosure, an electronic device is proposed, comprising: a processor and a memory storing a computer program, the processor being configured to implement the method described above when the computer program is executed.

[0040] The method disclosed herein for use in very large-scale integrated circuits (VLSI) includes: acquiring timing information (TNS) of the entire netlist of the VLSI; sorting all nodes of the entire netlist according to the topology of the VLSI, placing nodes with the same sequence number in the same queue; performing reverse traversal on all sorted nodes according to the queue number; performing size reduction preprocessing on all nodes in the same queue to obtain the slack change value of the output pins of the current node and the next-level node; checking the slack change value of the output pins of the current node and the next-level node, and performing size reduction processing on the current node whose slack change value of the output pins of the current node and the next-level node meets the requirements; updating the timing information of the current node and the next-level node, and reacquiring the timing information new_TNS of the entire netlist; comparing the timing information new_TNS of the entire netlist with the timing information TNS, and optimizing the area power consumption of the VLSI based on the comparison result. It can reduce the total area of ​​the integrated circuit by reducing the area of ​​each current node, thereby solving the problem of excessive area and power consumption in the physical optimization design process while ensuring that the timing remains unchanged.

[0041] Other optional features and technical effects of the embodiments of the present invention are partly described below and partly apparent from reading this document. Attached Figure Description

[0042] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The elements shown are not limited to the scale shown in the drawings, and the same or similar reference numerals in the drawings denote the same or similar elements, wherein:

[0043] Figure 1 A flowchart of a method for very large-scale integrated circuits according to an embodiment of the present disclosure is shown;

[0044] Figure 2 A schematic diagram of the topology of a very large-scale integrated circuit according to an embodiment of the present disclosure is shown;

[0045] Figure 3 A schematic diagram of the topology of a very large-scale integrated circuit according to another embodiment of the present disclosure is shown;

[0046] Figure 4 A system schematic diagram for a very large-scale integrated circuit according to another embodiment of the present disclosure is shown;

[0047] Figure 5 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings. Here, the illustrative embodiments and descriptions of this invention are used to explain the invention, but are not intended to limit the invention.

[0049] The term "comprising" and its variations as used herein signify open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0050] Furthermore, the steps illustrated in the flowcharts of the accompanying drawings can be executed in a computer, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in a different order than that presented here.

[0051] Figure 1 Flowcharts of a method for very large-scale integrated circuits according to an embodiment of the present disclosure are shown respectively; the method can be used in the field of physical optimization design automation of very large-scale integrated circuits, such as the field of area and power consumption optimization, and the method is specifically as follows. Figure 1As shown, it includes:

[0052] Step S1: Obtain the timing information TNS of the entire netlist of the VLSI.

[0053] The timing information TNS (total negative slack) can be the sum of the negative timing path slack values ​​in the entire netlist (design) of a VLSI, representing a performance range of the chip. The timing path slack value is the time margin, which is the result of subtracting the arrival time from the required time of the electronic circuit's timing path. The slack value can be positive, 0, or negative. A positive slack value indicates that the timing path delay meets the requirements, while a negative slack value indicates that the power consumption of the electronic components in the integrated circuit is too high, causing the time delay to not meet the requirements. Using the sum of all negative timing path slack values ​​in the integrated circuit's netlist as the timing information TNS of the timing netlist can better optimize the cell area problem for electronic components with excessive power consumption in physical optimization design.

[0054] Step S2: Sort all nodes in the entire netlist according to the topology of the VLSI, and place nodes with the same sequence number in the same queue.

[0055] Figure 2 A schematic diagram of the topology of a very large-scale integrated circuit according to an embodiment of the present disclosure is shown.

[0056] For example, such as Figure 2 As shown, the starting nodes startpointA and startpointB are set to 1. Based on the VLSI topology, the downstream nodes are sequentially incremented by 1, i.e., set to 2, 3, 4, ..., n, until the end node endpoint, where n is a positive integer. Intermediate nodes with the same index are placed in the same queue, and then the intermediate nodes in each queue are traversed based on the queue.

[0057] Step S3: Traverse all sorted nodes in reverse order based on the queue number. For example, access the queue array sequentially from back to front according to the queue number, i.e., queue n->…-> queue 5-> queue 4-> queue 3-> queue 2-> queue 1.

[0058] Step S4: Perform size reduction preprocessing on all nodes in the same queue to obtain the slack change value of the output pin of the current node and the next level node.

[0059] When accessing each queue, each intermediate node within it is accessed sequentially, such as... Figure 2As shown, the access order of queue 4 is: inst1->inst2->inst3.

[0060] Furthermore, when traversing all nodes in the queue, it is also necessary to obtain and record the group to which the cell library corresponding to the current node belongs. For example, nodes with the same area are placed in the same group. For instance, BUFX1, BUFX1_HVT, BUFX1_SVT, and BUFX1_LVT have the same area and belong to the same group (e.g., group 1), while BUFX2, BUFX2_HVT, BUFX2_SVT, and BUFX2_LVT have the same area and belong to the same group (e.g., group 2).

[0061] Step S5: Check the slack change value of the output pins of the current node and the next level node of the current node, and reduce the size of the current node whose slack change value of the output pins of the current node and the next level node of the current node meets the requirements.

[0062] One method for scaling down the current node is to replace the current node with the node corresponding to a cell library with a smaller area. Then, the slack and slew values ​​of the output pins of the scaled-down current node and its next-level node are checked. The current node can only be scaled down if the slack values ​​of the output pins of the current node and its next-level node meet the requirements.

[0063] In one example, the slack changes of the output pins of the current node and the next-level node of the current node meet the requirements, which may include:

[0064] The slack change values ​​of the output pins of the current node and the next-level node of the current node conform to the size reduction rule, and the current node is subjected to size reduction processing.

[0065] Specifically, it can be: if the slack value of the output pin of the current node is greater than 0, the slack value of the output pin after the size of the current node is reduced is still greater than 0; or, if the slack value of the output pin of the current node is less than 0, the slack value of the output pin after the size of the current node is reduced is greater than or equal to the initial slack value.

[0066] Furthermore, the slack value of the output pin of the next-level node of the current node does not deteriorate. That is, if the slack value of the output pin of the next-level node of the current node is greater than 0, the slack value of the output pin of the next-level node of the current node will still be greater than 0 after the size of the current node is reduced; or if the slack value of the output pin of the next-level node of the current node is less than 0, the slack value of the output pin of the next-level node of the current node will be greater than or equal to the initial slack value of the next-level node of the current node before the size of the current node is reduced.

[0067] The current node can only be shrunk if the slack values ​​of the output pins of the current node and the next-level node of the current node simultaneously meet the size reduction rules; otherwise, the current node is retained without any processing.

[0068] Figure 3 A schematic diagram of a topology for a very large-scale integrated circuit according to another embodiment of the present disclosure is shown.

[0069] For example, such as Figure 3 As shown, when attempting to shrink node inst1, the first step is to check the slack values ​​of output pins ZN and Y. If the slack of one of the output pins is less than 0, it is necessary to ensure that after shrinking node inst1, the slack of output pins ZN and Y does not deteriorate, and the slew does not deteriorate. Here, slew represents the signal transition time. A long rise and fall transition time indicates a slow internal circuit and a long delay. Therefore, the slack values ​​of the current node and its next-level node should be as large as possible, the slew signal transition time should be as large as possible, and the delay should be as small as possible.

[0070] If the slack values ​​of the output pins ZN and Y of node inst1 are both greater than 0, then it is necessary to ensure that the slack values ​​of the output pins ZN and Y of node inst1 remain greater than 0 after the current node size is reduced.

[0071] At the same time, it is also necessary to ensure that the next level node of the current node satisfies the size reduction rule, that is:

[0072] Case 1: If the slack of the output pins Z and Y of the next-level nodes inst2 and inst3 of the current node inst1 is less than 0, then it is necessary to ensure that the slack and slew of the output pins Z and Y of nodes inst2 and inst3 do not deteriorate. That is, the output pins Z and Y of nodes inst2 and inst3 are greater than or equal to the initial slack values ​​of the output pins Z and Y of nodes inst2 and inst3 before the current node inst1 was shrunk.

[0073] Case 2: If the slack of the output pins Z and Y of nodes inst2 and inst3 is greater than 0, then it is necessary to ensure that the slack of the output pins Z and Y of nodes inst2 and inst3 is still greater than 0.

[0074] Otherwise, if the current node size reduction process causes the output pin of the next level node to become slack and the slew value to also become worse, then the current node cannot be size-reduced.

[0075] Step S6: Update the timing information of the current node and its next-level node, and reacquire the timing information new_TNS for the entire netlist. Updating the timing information of the output pins of the current node's surrounding nodes ensures that when attempting to shrink the upstream node, the timing information of the current node and its surrounding nodes remains basically correct.

[0076] Step S7: Compare the timing information new_TNS and timing information TNS of the entire netlist, and optimize the area and power consumption of the VLSI based on the comparison result.

[0077] In one example, the step may include:

[0078] When the timing information new_TNS is greater than or equal to the timing information TNS, the current node undergoing size reduction processing will be restored to its previous state until the timing information new_TNS is less than the timing information TNS, thereby optimizing the area and power consumption of the VLSI.

[0079] When the timing information new_TNS is less than the timing information TNS, the current node that has undergone size reduction processing is restored to its previous state, thereby optimizing the area and power consumption of the VLSI.

[0080] Specifically, the values ​​of timing information new_TNS and timing information TNS are compared. When the timing information new_TNS is greater than or equal to the timing information TNS, it indicates that the area power consumption performance of the VLSI's cell node after size reduction processing has been optimized. Further optimization of the VLSI's area power consumption performance can be implemented until the timing information new_TNS is less than the timing information TNS. Since a time when the timing information new_TNS is less than the timing information TNS indicates that the area power consumption performance of the VLSI's cell node after size reduction processing has not been optimized and is even greater than the area power consumption before size reduction processing, the VLSI's cell node is restored to its previous state before size reduction processing, ending the VLSI's area power consumption performance optimization process.

[0081] The method disclosed herein for very large-scale integrated circuits (VLSI) involves: acquiring the timing information (TNS) of the entire netlist of the VLSI; sorting all nodes in the entire netlist according to the topology of the VLSI, placing nodes with the same sequence number in the same queue; performing a reverse traversal on all sorted nodes according to the queue number; performing size reduction preprocessing on all nodes in the same queue to obtain the slack change value of the output pins of the current node and the next-level node; checking the slack change value of the output pins of the current node and the next-level node, and performing size reduction processing on the current node whose slack change value meets the requirements; updating the timing information of the current node and the next-level node, and reacquiring the timing information new_TNS of the entire netlist; comparing the timing information new_TNS of the entire netlist with the timing information TNS, and optimizing the area and power consumption of the VLSI based on the comparison result. This approach can reduce the total area of ​​the integrated circuit by decreasing the area of ​​each current node, thereby solving the problem of excessive area power consumption during physical optimization design while maintaining timing consistency. Furthermore, it can achieve a 5%-15% reduction in area density while maintaining timing consistency.

[0082] The above describes an embodiment of the apparatus described in this application, which can be used to execute the method embodiments described in this application. For details not disclosed in the apparatus embodiments described in this application, please refer to the method embodiments described in this application.

[0083] Figure 4 A system principle block diagram for a very large-scale integrated circuit according to an embodiment of the present disclosure is shown. Figure 4 As shown, the system may include:

[0084] The acquisition module 501 is used to acquire the timing information TNS of the entire netlist of the VLSI;

[0085] The sorting module 502 is used to sort all nodes of the entire netlist according to the topology of the VLSI, and place nodes with the same sequence number in the same queue.

[0086] The reverse traversal module 503 is used to perform a reverse traversal of all sorted nodes according to the queue number.

[0087] The size reduction preprocessing module 504 is used to perform size reduction preprocessing on all nodes in the same queue to obtain the slack change value of the output pin of the current node and the next level node;

[0088] The size reduction processing module 505 is used to check the slack change value of the output pin of the current node and the next level node of the current node, and to perform size reduction processing on the current node whose slack change value of the output pin of the current node and the next level node of the current node meets the requirements.

[0089] The timing information update module 506 is used to update the timing information of the current node and the next-level node of the current node, and to re-acquire the timing information new_TNS of the entire netlist;

[0090] The comparison module 507 is used to compare the timing information new_TNS and the timing information TNS of the entire netlist, and optimize the area and power consumption of the VLSI based on the comparison result.

[0091] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0092] In some embodiments, the area power consumption optimization system apparatus for VLSI may incorporate the area power consumption optimization method features of any embodiment of VLSI, and vice versa, which will not be elaborated here.

[0093] In an embodiment of the present invention, an electronic device is provided, comprising: a processor and a memory storing a computer program, wherein the processor is configured to perform a method for area and power consumption optimization of a very large-scale integrated circuit according to any embodiment of the present invention when running the computer program.

[0094] Figure 5The diagram illustrates a method for implementing embodiments of the present invention or an electronic device 1000 for implementing embodiments of the present invention. In some embodiments, it may include more or fewer electronic devices than illustrated. In some embodiments, it may be implemented using a single or multiple electronic devices. In some embodiments, it may be implemented using cloud-based or distributed electronic devices.

[0095] Figure 5 This is a schematic diagram of the structure of the electronic device 10 provided in an embodiment of this application. Figure 5 As shown, the electronic device 1000 includes a processor 1001, which can perform various appropriate operations and processes based on programs and / or data stored in read-only memory (ROM) 1002 or programs and / or data loaded from storage portion 1008 into random access memory (RAM) 1003. The processor 1001 may be a multi-core processor or may contain multiple processors. In some embodiments, the processor 1001 may include a general-purpose main processor and one or more special coprocessors, such as a central processing unit (CPU), graphics processing unit (GPU), neural network processor (NPU), digital signal processor (DSP), etc. Various programs and data required for the operation of the electronic device 1000 are also stored in RAM 1003. The processor 1001, ROM 1002, and RAM 1003 are interconnected via bus 1004. An input / output (I / O) interface 1005 is also connected to bus 1004.

[0096] The processor and memory described above are used together to execute programs stored in the memory. When the program is executed by a computer, it can implement the methods, steps, or functions described in the above embodiments.

[0097] The following components are connected to I / O interface 1005: an input section 1006 including a keyboard, mouse, touchscreen, etc.; an output section 1007 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN card, modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to I / O interface 1005 as needed. A removable medium 1011, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 1010 as needed so that computer programs read from it can be installed into storage section 1008 as needed. Figure 5 The diagram only shows a portion of the components and does not imply that the computer system 1000 only includes... Figure 5 The components shown.

[0098] The systems, devices, modules, or units described in the above embodiments can be implemented by a computer or its associated components. The computer may be, for example, a mobile terminal, smartphone, personal computer, laptop computer, in-vehicle human-machine interface device, personal digital assistant, media player, navigation device, game console, tablet computer, wearable device, smart TV, Internet of Things system, smart home, industrial computer, server, or a combination thereof.

[0099] Although not shown, in this embodiment of the invention, a storage medium is provided storing a computer program configured to execute, when run, any file-difference-based compilation method of this embodiment of the invention.

[0100] Storage media in embodiments of the present invention include articles that are permanent and non-permanent, removable and non-removable, capable of storing information by any method or technology. Examples of storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0101] The methods, programs, systems, apparatuses, etc., in embodiments of the present invention can be executed or implemented in one or more networked computers, or practiced in a distributed computing environment. In the embodiments of this specification, in these distributed computing environments, tasks can be performed by remote processing devices connected via a communication network.

[0102] Those skilled in the art will understand that the embodiments described in this specification can be provided as methods, systems, or computer program products. Therefore, those skilled in the art will realize that the functional modules / units or controllers and related method steps described in the above embodiments can be implemented in software, hardware, or a combination of both.

[0103] Unless explicitly stated otherwise, the actions or steps of the methods and procedures described in the embodiments of the present invention do not necessarily have to be performed in a specific order and can still achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0104] This document describes several embodiments of the present invention; however, for the sake of brevity, the descriptions of the embodiments are not exhaustive, and identical or similar features or parts between the embodiments may be omitted. In this document, "one embodiment," "some embodiments," "example," "specific example," or "some examples" refers to embodiments applicable to at least one, but not all, of the present invention. The above terms do not necessarily refer to the same embodiments or examples. Without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of the different embodiments or examples.

[0105] The exemplary systems and methods of the present invention have been specifically shown and described with reference to the above embodiments, which are merely examples of the best mode for implementing the systems and methods. Those skilled in the art will understand that various changes can be made to the embodiments of the systems and methods described herein without departing from the spirit and scope of the invention as defined in the appended claims when implementing the systems and / or methods.

Claims

1. A method for very large-scale integrated circuits, characterized in that, The method includes: Obtain the timing information (TNS) of the entire netlist of the VLSI; Based on the topology of the VLSI, all nodes in the entire netlist are sorted, and nodes with the same sequence number are placed in the same queue. For all sorted nodes, perform a reverse traversal based on the queue number; Perform size reduction preprocessing on all nodes in the same queue to obtain the slack change value of the output pin of the current node and the next level node; Check the slack change value of the output pins of the current node and the next level node of the current node, and reduce the size of the current node whose slack change value of the output pins of the current node and the next level node of the current node meets the requirements. Update the timing information of the current node and the next-level node of the current node, and reacquire the timing information new_TNS of the entire netlist; The timing information new_TNS and timing information TNS of the entire netlist are compared, and the area and power consumption of the VLSI are optimized based on the comparison result.

2. The method according to claim 1, characterized in that, The step of sorting all nodes in the entire netlist according to the topology of the VLSI includes: According to the topology of the VLSI, the sequence number of the starting node is set to 1, and the downstream nodes of the starting node are incremented by 1 in sequence until the end node of the VLSI.

3. The method according to claim 1, characterized in that, The slack changes of the output pins of the current node and the next-level node meet the requirements, including: The slack change values ​​of the output pins of the current node and the next-level node of the current node conform to the size reduction rule, and the current node is subjected to size reduction processing.

4. The method according to claim 3, characterized in that, The slack values ​​of the output pins of the current node and the next-level node of the current node conform to the size reduction rules, including: If the slack value of the output pin of the current node is greater than 0, the slack value of the output pin after the size of the current node is reduced is still greater than 0; Alternatively, if the slack value of the output pin of the current node is less than 0, then the slack value of the output pin after the current node size is reduced is greater than or equal to the initial slack value. Furthermore, the slack value of the output pin of the next level node of the current node did not deteriorate.

5. The method according to claim 4, characterized in that, The slack value of the output pin of the next-level node of the current node has not deteriorated, including: If the slack value of the output pin of the next level node of the current node is greater than 0, the slack value of the output pin of the next level node of the current node will still be greater than 0 after the size of the current node is reduced. Alternatively, if the slack value of the output pin of the next-level node of the current node is less than 0, after the size of the current node is reduced, the slack value of the output pin of the next-level node of the current node is greater than or equal to the initial slack value of the next-level node of the current node before the size of the current node is reduced.

6. The method according to claim 1, characterized in that, The step of comparing the timing information new_TNS and the timing information TNS of the entire netlist, and optimizing the area and power consumption of the VLSI based on the comparison result, includes: When the timing information new_TNS is greater than or equal to the timing information TNS, the current node undergoing size reduction processing is restored to its previous state until the timing information new_TNS is less than the timing information TNS, thereby optimizing the area and power consumption of the VLSI.

7. The method according to claim 1, characterized in that, The step of comparing the timing information new_TNS and the timing information TNS of the entire netlist, and optimizing the area and power consumption of the VLSI based on the comparison result, further includes: When the timing information new_TNS is less than the timing information TNS, the current node that has undergone size reduction processing is restored to its previous state, thereby optimizing the area and power consumption of the VLSI.

8. An area and power consumption optimization system for very large-scale integrated circuits, characterized in that, The system includes: The acquisition module is used to acquire the timing information (TNS) of the entire netlist of the VLSI; The sorting module is used to sort all nodes in the entire netlist according to the topology of the VLSI, and place nodes with the same sequence number in the same queue. The reverse traversal module is used to perform reverse traversal of all sorted nodes according to the number of queues. The size reduction preprocessing module is used to perform size reduction preprocessing on all nodes in the same queue to obtain the slack change value of the output pin of the current node and the next level node; The size reduction processing module is used to check the slack change value of the output pins of the current node and the next level node of the current node, and to perform size reduction processing on the current node whose slack change value of the output pins of the current node and the next level node of the current node meets the requirements; The timing information update module is used to update the timing information of the current node and the next-level node of the current node, and to re-acquire the timing information new_TNS of the entire netlist; The comparison module is used to compare the timing information new_TNS and the timing information TNS of the entire netlist, and optimize the area and power consumption of the VLSI based on the comparison result.

9. A storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the method as described in any one of claims 1-7.

10. An electronic device, characterized in that, include: A processor and a memory storing a computer program, the processor being configured to implement the method of any one of claims 1-7 when the computer program is executed.

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