Display control circuit, method, display panel, and display device

Abstract

The application provides a display control circuit, a method, a display panel and a display device. The display control circuit comprises a pixel circuit, a driving integrated circuit and a picture generator; the picture generator judges whether a current picture is a dynamic picture or a static picture according to a current data voltage; after the end of a refresh frame, when the potential of a data supply instruction signal is a valid voltage, the display control circuit controls the potential of the compensation control signal to maintain as an invalid voltage before the next valid voltage period of the data supply instruction signal when the current picture is a static picture; and after the end of the refresh frame, when the potential of the data supply instruction signal is a valid voltage, the display control circuit controls the potential of the compensation control signal to be a valid voltage in at least part of the next invalid voltage period of the light-emitting control signal when the previous picture is a dynamic picture. The application can control the realization of delicate frequency reduction operation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display control circuit, method, display panel and display device. BACKGROUND

[0002] The related Frame Skip (frame skipping) frequency reduction can only reduce the frequency by an integer multiple of the base frequency (for example, when the base frequency is 120Hz, the refresh frequency can only be reduced to 120Hz / n, where n is a positive integer), and cannot achieve delicate frequency reduction operation. SUMMARY

[0003] The main purpose of the present application is to provide a display control circuit, method, display panel and display device, which solves the problem that delicate frequency reduction operation cannot be controlled in the prior art.

[0004] In one aspect, the embodiment of the present application provides a display control circuit, which is included in a display panel, the display panel further comprising a pixel circuit, a driving integrated circuit and a picture generator; the driving integrated circuit is used to provide a data providing indication signal; the pixel circuit is connected to a compensation control signal and a light emitting control signal, and is used to perform threshold voltage compensation under the control of the compensation control signal and light emitting control under the control of the light emitting control signal.

[0005] The display control circuit is used to control the frequency of the data providing indication signal to be a first frequency after the end of a refresh frame, the first frequency being 1 / n times of a light emitting control frequency, where n is a positive integer; the light emitting control frequency is the frequency of the light emitting control signal.

[0006] The picture generator is used to determine whether a current picture is a dynamic picture or a static picture according to a current data voltage, and provide the determination result to the display control circuit.

[0007] The display control circuit is used to, after the end of the refresh frame, when the potential of the data providing indication signal is a valid voltage, control the potential of the compensation control signal to maintain an invalid voltage before the next valid voltage period of the data providing indication signal when the determination result indicates that the current picture is a static picture, and is also used to, after the end of the refresh frame, when the potential of the data providing indication signal is a valid voltage, control the potential of the compensation control signal to be a valid voltage in at least part of the next invalid voltage period of the light emitting control signal when the determination result indicates that the current picture is a dynamic picture.

[0008] Optionally, the pixel circuit further connects a data write control signal, and the display control circuit is further configured to, after the end of the refresh frame, when the potential of the data providing indication signal is the valid voltage, control the potential of the data write control signal to maintain as the invalid voltage before a next valid voltage period of the data providing indication signal when the judgment result indicates that the current picture is the static picture, and control the potential of the data write control signal to be the valid voltage in at least part of a next invalid voltage period of the light emitting control signal when the judgment result indicates that the current picture is the dynamic picture.

[0009] Optionally, the pixel circuit further connects a data write control signal.

[0010] The display control circuit is configured to control the frequency of the data write control signal to be a second frequency, and the second frequency is a fixed frequency.

[0011] Optionally, the second frequency is 1 / m times of the light emitting control frequency, and m is a positive integer.

[0012] Optionally, the pixel circuit further connects a first initial control signal, and the first initial control signal is configured to control the potential of a control end of a driving circuit in the pixel circuit to be initialized.

[0013] The display control circuit is configured to, after the end of the refresh frame, when the potential of the data providing indication signal is the valid voltage, control the potential of the first initial control signal to maintain as the invalid voltage before a next valid voltage period of the data providing indication signal when the judgment result indicates that the current picture is the static picture, and control the potential of the first initial control signal to be the valid voltage in at least part of a next invalid voltage period of the light emitting control signal when the judgment result indicates that the current picture is the dynamic picture.

[0014] Optionally, the pixel circuit further connects a second initial control signal, and the second initial control signal is configured to control the potential of a first electrode of a light emitting element in the pixel circuit to be initialized.

[0015] The display control circuit is configured to control the frequency of the second initial control signal to be a third frequency, and the third frequency is a fixed frequency.

[0016] Optionally, the third frequency is 1 / a times of the light emitting control frequency, and m is a positive integer.

[0017] In a second aspect, the embodiments of the present application provide a display control method applied to the display control circuit, the display control method comprising:

[0018] The display control circuit controls the frequency of the data provision indication signal to be a first frequency, and the first frequency is 1 / n times of the light emission control frequency, where n is a positive integer;

[0019] The picture generator judges whether the current picture is a dynamic picture or a static picture according to the current data voltage, and provides the judgment result to the display control circuit;

[0020] When the potential of the data provision indication signal is the effective voltage, and the judgment result indicates that the current picture is a static picture, the display control circuit controls the potential of the compensation control signal to maintain the invalid voltage before the next effective voltage period of the data provision indication signal; when the potential of the data provision indication signal is the effective voltage, and the judgment result indicates that the current picture is a dynamic picture, the display control circuit controls the potential of the compensation control signal to be the effective voltage in at least part of the next invalid voltage period of the light emission control signal.

[0021] Optionally, the pixel circuit is further connected to a data write control signal, and the display control method further comprises:

[0022] When the potential of the data provision indication signal is the effective voltage, and the judgment result indicates that the current picture is a static picture, the display control circuit controls the potential of the data write control signal to maintain the invalid voltage before the next effective voltage period of the data provision indication signal;

[0023] When the potential of the data provision indication signal is the effective voltage, and the judgment result indicates that the current picture is a dynamic picture, the display control circuit controls the potential of the data write control signal to be the effective voltage in at least part of the next invalid voltage period of the light emission control signal.

[0024] In a third aspect, the embodiments of the present application provide a display panel comprising the display control circuit.

[0025] Optionally, the display panel according to at least one of the embodiments of the present application further comprises a pixel circuit, a driving integrated circuit and a picture generator;

[0026] The driving integrated circuit is configured to provide a data provision indication signal;

[0027] The picture generator is configured to judge whether the current picture is a dynamic picture or a static picture according to a current data voltage, and provide a judgment result to the display control circuit.

[0028] The pixel circuit comprises a light emitting element, a driving circuit, a compensation control circuit, a first light emitting control circuit and a second light emitting control circuit;

[0029] The control end of the driving circuit is electrically connected with the first node, the first end of the driving circuit is electrically connected with the second node, the second end of the driving circuit is electrically connected with the third node, and the driving circuit is used for controlling the communication between the second node and the third node under the control of the potential of the first node;

[0030] The control end of the compensation control circuit is electrically connected with a compensation control end, and the compensation control circuit is electrically connected with the first node and the third node respectively, and is used for controlling the communication between the first node and the third node under the control of a compensation control signal provided by the compensation control end;

[0031] The first light emitting control circuit is electrically connected with a light emitting control end, a power voltage end and the second node respectively, and is used for controlling the communication between the power voltage end and the second node under the control of a light emitting control signal provided by the light emitting control end;

[0032] The second light emitting control circuit is electrically connected with the light emitting control end, the third node and the first pole of the light emitting element respectively, and is used for controlling the communication between the third node and the first pole of the light emitting element under the control of the light emitting control signal;

[0033] The second pole of the light emitting element is electrically connected with a low voltage end.

[0034] Optionally, the pixel circuit further comprises a data writing circuit, a first initialization circuit and a second initialization circuit;

[0035] The data writing circuit is electrically connected with a writing control end, a data line and the second node respectively, and is used for writing a data voltage provided by the data line into the second node under the control of a data writing control signal provided by the writing control end;

[0036] The first initialization circuit is electrically connected with a first initial control end, a first initial voltage end and the first node respectively, and is used for writing a first initial voltage provided by the first initial voltage end into the first node under the control of a first initial control signal provided by the first initial control end;

[0037] The second initialization circuit is electrically connected with a second initial control end, a second initial voltage end and the first pole of the light emitting element respectively, and is used for writing a second initial voltage provided by the second initial voltage end into the first pole of the light emitting element under the control of a second initial control signal provided by the second initial control end.

[0038] In a fourth aspect, embodiments of the present invention provide a display device including the display panel described above.

[0039] Optionally, the pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initialization circuit, and a second initialization circuit; the display device includes a first GOA module and a second GOA module.

[0040] The first GOA module is used to provide a compensation control signal for the compensation control circuit and a first initial control signal for the first initialization circuit;

[0041] The second GOA module is used to provide a data writing control signal for the data writing circuit and a second initial control signal for the second initialization circuit.

[0042] Optionally, the pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initialization circuit, and a second initialization circuit; the display device includes a first GOA module, a second GOA module, and a third GOA module.

[0043] The first GOA module is used to provide a compensation control signal for the compensation control circuit and a first initial control signal for the first initialization circuit;

[0044] The second GOA module is used to provide data writing control signals for the data writing circuit;

[0045] The third GOA module provides a second initial control signal to the second initialization circuit.

[0046] Compared with the prior art, the display control circuit, method, display panel and display device described in the embodiments of the present invention can control and achieve fine frequency reduction operation. Attached Figure Description

[0047] Figure 1 This is a structural diagram of the display panel according to at least one embodiment of the present invention;

[0048] Figure 2 This is a structural diagram of the display panel according to at least one embodiment of the present invention;

[0049] Figure 3 This is a circuit diagram of at least one embodiment of the pixel circuit in at least one embodiment of the present invention;

[0050] Figure 4 yes Figure 3 The timing diagram of at least one embodiment of the pixel circuit shown;

[0051] Figure 5This is a circuit diagram of at least one embodiment of the pixel circuit in at least one embodiment of the present invention;

[0052] Figure 6 yes Figure 5 The timing diagram of at least one embodiment of the pixel circuit shown;

[0053] Figure 7 This is a circuit diagram of at least one embodiment of the pixel circuit in at least one embodiment of the present invention;

[0054] Figure 8 yes Figure 7 The timing diagram of at least one embodiment of the pixel circuit shown;

[0055] Figure 9 This is a circuit diagram of at least one embodiment of the pixel circuit in at least one embodiment of the present invention;

[0056] Figure 10 yes Figure 9 The timing diagram of at least one embodiment of the pixel circuit shown;

[0057] Figure 11 This is the timing diagram for generating data and providing the indication signal TE.

[0058] Figure 12 It is used to implement Figure 11 A structural diagram of at least one embodiment of the AND gate corresponding to the working timing. Detailed Implementation

[0059] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode, and the other as the second electrode.

[0061] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0062] The display control circuit described in this embodiment of the invention is included in the display panel, such as... Figure 1As shown, the display panel also includes a pixel circuit P1, a driver integrated circuit D0, and an image generator S1; the driver integrated circuit D0 is used to provide a data provision indication signal TE; the pixel circuit P1 is connected to a compensation control signal SC and a light emission control signal EM, and is used to perform threshold voltage compensation under the control of the compensation control signal SC and to perform light emission control under the control of the light emission control signal EM.

[0063] The display control circuit 10 is used to control the frequency of the data providing indication signal TE to a first frequency after the refresh frame ends. The first frequency is 1 / n times the light emission control frequency, where n is a positive integer. The light emission control frequency is the frequency of the light emission control signal EM.

[0064] The image generator S1 is used to determine whether the current image is a dynamic image or a static image based on the current data voltage, and provides the determination result to the display control circuit 10.

[0065] The display control circuit 10 is configured to, after the refresh frame ends, when the potential of the data providing indication signal TE is an effective voltage, and when the judgment result indicates that the current screen is a static screen, control the potential of the compensation control signal SC to remain an ineffective voltage before the next effective voltage time period of the data providing indication signal TE. It is also configured to, after the refresh frame ends, when the potential of the data providing indication signal TE is an effective voltage, and when the judgment result indicates that the current screen is a dynamic screen, control the potential of the compensation control signal SC to be an effective voltage during at least a portion of the next ineffective voltage time period of the light emission control signal EM, so as to refresh the potential of the control terminal of the driving circuit in the pixel circuit.

[0066] In at least one embodiment of the present invention, the effective voltage of the data providing indication signal TE can mean that the potential of TE is a high voltage;

[0067] The effective voltage time period of the indicator signal TE provided by the data can refer to the time period during which the potential of TE is maintained at a high voltage.

[0068] The fact that the potential of the compensation control signal SC is maintained at an invalid voltage can mean that: when the transistor controlled by the compensation control signal SC is an n-type transistor, the potential of SC is low; when the transistor controlled by the compensation control signal SC is a p-type transistor, the potential of SC is high.

[0069] The fact that the potential of the compensation control signal SC is maintained at an effective voltage can mean that: when the transistor controlled by the compensation control signal SC is an n-type transistor, the potential of SC is high; when the transistor controlled by the compensation control signal SC is a p-type transistor, the potential of SC is low.

[0070] When the transistor controlled by the light emission control signal EM is a p-type transistor, the invalid voltage period of the light emission control signal EM can refer to the period during which the light emission control signal EM is continuously a high voltage signal.

[0071] When the transistor controlled by the light emission control signal EM is an n-type transistor, the invalid voltage period of the light emission control signal EM can refer to the period during which the light emission control signal EM is continuously at a low voltage.

[0072] This invention relates to a timing design scheme that enables fine-grained frequency reduction. Compared to related Frame Skip frequency reduction, which can only be based on integer multiples of the base frequency (e.g., when the base frequency is 120Hz, the refresh rate can only be reduced to 120Hz / n, where n is a positive integer), the display control circuit described in this invention can control and implement more fine-grained frequency reduction operations. For example, when the base frequency is 120Hz, using the display control circuit described in this invention, the refresh rate can be reduced to 240Hz / b, where b can be an integer greater than 2. That is, the refresh rate can be reduced to 80Hz, 60Hz, 48Hz, or 40Hz. Alternatively, the refresh rate can be reduced to 360Hz / c, where c can be an integer greater than 3. For example, the refresh rate can be reduced to 90Hz, 72Hz, 60Hz, or 51.4Hz.

[0073] When the display control circuit of this embodiment of the invention is working, after the refresh frame ends, it enters the holding frame stage. During the holding frame stage, data voltage refresh can be performed during any time period when the potential of the light emission control signal is an invalid voltage. The higher the frequency of the light emission control signal, the better the fineness of the frequency reduction. For example, when the base frequency is 120Hz, the frequency of the light emission control signal can be 240Hz, 360Hz or 480Hz.

[0074] The display control circuit described in this embodiment of the invention is applicable to both LTPO (low-temperature polycrystalline oxide) display products and LTPS (low-temperature polycrystalline silicon) display products.

[0075] The embodiments of the present invention can achieve a fine frequency reduction function, which can make the screen refresh of the terminal product more timely, and the GPU (graphics processing unit) of the whole machine can display the image rendering more promptly, resulting in better screen continuity and a better user experience.

[0076] In at least one embodiment of the present invention, the pixel circuit is further connected to a data writing control signal, and the display control circuit is further configured to, after the refresh frame ends, when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a static screen, control the potential of the data writing control signal to remain an invalid voltage before the next effective voltage time period of the data providing indication signal. The circuit is also configured to, after the refresh frame ends, when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a dynamic screen, control the potential of the data writing control signal to be an effective voltage during at least a portion of the next invalid voltage time period of the light emission control signal, so as to perform data voltage writing.

[0077] In at least one embodiment of the present invention, maintaining the potential of the data writing control signal as an invalid voltage may refer to:

[0078] When the transistor controlled by the data write control signal is an n-type transistor, the potential of the data write control signal is low; when the transistor controlled by the data write control signal is a p-type transistor, the potential of the data write control signal is high; maintaining the potential of the data write control signal at an effective voltage can mean:

[0079] When the transistor controlled by the data write control signal is an n-type transistor, the potential of the data write control signal is high voltage; when the transistor controlled by the data write control signal is a p-type transistor, the potential of the data write control signal is low voltage.

[0080] Optionally, the pixel circuit is also connected to a data writing control signal;

[0081] The display control circuit is used to control the frequency of the data writing control signal to a second frequency, which is a fixed frequency.

[0082] Optionally, the second frequency is 1 / m times the light emission control frequency, where m is a positive integer.

[0083] In at least one embodiment of the present invention, the pixel circuit is further connected to a first initial control signal, which is used to control the initialization of the potential of the control terminal of the driving circuit in the pixel circuit under the control of the first initial control signal;

[0084] The display control circuit is configured to, after the refresh frame ends, when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a static screen, control the potential of the first initial control signal to remain at an invalid voltage before the next effective voltage time period of the data providing indication signal. It is also configured to, after the refresh frame ends, when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a dynamic screen, control the potential of the first initial control signal to be an effective voltage during at least a portion of the next invalid voltage time period of the light emission control signal.

[0085] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the display control circuit shown, the pixel circuit P1 is further connected to a first initial control signal SI1, which is used to control the initialization of the potential of the control terminal of the driving circuit in the pixel circuit P1 under the control of the first initial control signal SI1.

[0086] The display control circuit 10 is configured to, after the refresh frame ends, when the potential of the data providing indication signal TE is an effective voltage, and when the judgment result indicates that the current screen is a static screen, control the potential of the first initial control signal SI1 to remain at an invalid voltage before the next effective voltage time period of the data providing indication signal TE. It is also configured to, after the refresh frame ends, when the potential of the data providing indication signal T3 is an effective voltage, and when the judgment result indicates that the current screen is a dynamic screen, control the potential of the first initial control signal SI1 to be an effective voltage during at least a portion of the next invalid voltage time period of the light emission control signal EM.

[0087] Optionally, the pixel circuit is further connected to a second initial control signal, which is used to control the initialization of the potential of the first electrode of the light-emitting element in the pixel circuit under the control of the second initial control signal;

[0088] The display control circuit is used to control the frequency of the second initial control signal to a third frequency, wherein the third frequency is a fixed frequency.

[0089] Optionally, the third frequency is 1 / a times the light emission control frequency, where m is a positive integer.

[0090] like Figure 3 As shown, in at least one embodiment of the present invention, the pixel circuit may include a light-emitting element, a driving circuit, a data writing circuit, a compensation control circuit, a first light-emitting control circuit, a second light-emitting control circuit, a first initialization circuit, a second initialization circuit, and an energy storage circuit; the light-emitting element may be an organic light-emitting diode (OLED).

[0091] The first initialization circuit includes a first transistor T1, the compensation control circuit includes a second transistor, the driving circuit includes a driving transistor T3, the data writing circuit includes a fourth transistor T4, the first light-emitting control circuit includes a fifth transistor T5, the second light-emitting control circuit includes a sixth transistor T6, the second initialization circuit includes a seventh transistor T7, and the energy storage circuit includes a storage capacitor Cst.

[0092] The gate of T1 is electrically connected to the first initial control terminal, and the first initial control signal input to the first initial control terminal is the first drive signal GateN(N) of the (N-1)th stage; the source of T1 is electrically connected to the first initial voltage terminal I1, and the drain of T1 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1; N is a positive integer;

[0093] The gate of T2 is electrically connected to the compensation control terminal, and the initial control signal connected to the initial control terminal is the first drive signal GateN(N+1) of the Nth stage; the source of T2 is electrically connected to the first node N1, and the drain of T2 is electrically connected to the third node N3.

[0094] The gate of T3 is electrically connected to the first node N1, the source of T3 is electrically connected to the second node N2, and the drain of T3 is electrically connected to the third node N3.

[0095] The gate of T4 is electrically connected to the write control terminal, the source of T4 is electrically connected to the data line Data, and the drain of T4 is electrically connected to the second node N2; the data write control signal accessed by the write control terminal is the second drive signal GateP(N+1) of the N+1th stage.

[0096] The gate of T5 is electrically connected to the light-emitting control terminal, which is connected to the light-emitting control signal EM; the source of T5 is electrically connected to the power supply voltage terminal VDD, and the drain of T5 is electrically connected to the second node N2.

[0097] The gate of T6 is electrically connected to the light-emitting control terminal, the source of T6 is electrically connected to the third node N3, the drain of T6 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of the organic light-emitting diode O1 is electrically connected to the low voltage terminal VSS.

[0098] The gate of T7 is electrically connected to the second initial control terminal, and the second initial control signal input to the second initial control terminal is the Nth stage second drive signal GateP(N); the source of T7 is electrically connected to the second initial voltage terminal I2, and the drain of T7 is electrically connected to the anode of O1; the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2;

[0099] The first terminal of Cst is electrically connected to the first node N1, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0100] exist Figure 3 In at least one embodiment of the pixel circuit shown, T1 and T2 are n-type transistors, and T3, T4, T5, T6 and T7 are all p-type transistors.

[0101] exist Figure 3 In at least one embodiment of the pixel circuit shown, a first GOA module can provide a compensation control signal to the compensation control circuit and a first initial control signal to the first initialization circuit; a second GOA module can provide a data writing control signal to the data writing circuit and a second initial control signal to the second initialization circuit; and a light emission control signal generation module can provide light emission control signals to the first light emission control circuit and the second light emission control circuit.

[0102] exist Figure 4 In the diagram, the signal labeled TE is the TE signal. The TE signal provides an indication signal for data. When the TE signal is provided to the motherboard by the driver integrated circuit, an upward pulse in the TE signal indicates that the motherboard can provide data voltage to the driver integrated circuit. The motherboard contains an MCU (microcontroller), and the MCU contains an image generator. The image generator determines whether the image to be displayed is a dynamic or static image. If it is a static image, no data refresh is required; if it is a dynamic image, the data refresh is required.

[0103] like Figure 4 As shown, Figure 3 In at least one embodiment of the pixel circuit shown, the base frequency is 120Hz, the first refresh frame is labeled Ts1, and the frequency of the light emission control signal EM is 240Hz; in the first refresh frame Ts1, the frequency of the TE signal is 120Hz.

[0104] After the first refresh frame Ts1 ends, the frequency of the TE signal changes to 240Hz. During the second upward pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image, so the second frame is also a refresh frame.

[0105] In the second refresh frame Ts2, during the first high-level maintenance period of EM, the potentials of GateN(N) and GateN(N+1) are raised successively to first control T1 to open to initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time included in the time period when T2 is open, under the control of GateP(N+1), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst. Before T4 is turned on, T7 is turned on to initialize the anode of O1 through Vinit2.

[0106] In the second refresh frame Ts2, the frequency of the TE signal is 120Hz;

[0107] After the second refresh frame Ts2 ends, the frequency of the TE signal becomes 240Hz. During the third upward pulse of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed with data voltage. At this time, it is in the first hold frame Tb1.

[0108] After the second refresh frame Ts2 ends, on the fourth upward pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image, and then enters the third refresh frame Ts3.

[0109] In the third refresh frame Ts3, during the first high-level maintenance period of EM, the potentials of GateN(N) and GateN(N+1) are raised successively to first control T1 to open to initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time included in the time period when T2 is open, under the control of GateP(N+1), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst. Before T4 is turned on, T7 is turned on to initialize the anode of O1 through Vinit2.

[0110] After the third refresh frame Ts3 ends, the frequency of the TE signal becomes 240Hz. During the fifth and sixth pulses of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed with data voltage. At this time, it is in the second hold frame Tb2. During the seventh pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image and then enters the fourth refresh frame Ts4.

[0111] In the fourth refresh frame Ts4, during the first high-level maintenance period of EM, the potentials of GateN(N) and GateN(N+1) are raised successively to first control T1 to open and initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time included in the time period when T2 is open, under the control of GateP(N+1), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst. Before T4 is turned on, T7 is turned on to initialize the anode of O1 through Vinit2.

[0112] After the fourth refresh frame Ts4 ends, the frequency of the TE signal becomes 240Hz. During the eighth, ninth, tenth, eleventh, twelfth and thirteenth pulses of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed by data voltage. This period is the third hold frame Tb3.

[0113] Within each hold frame, both GateN(N+1) and GateN(N) are low voltage signals.

[0114] like Figure 4 As shown, the refresh rates of the pixel circuit are 120Hz, 80Hz and 60Hz respectively.

[0115] exist Figure 4 In the diagram, the signal labeled MIPI is the communication interface control signal. When MIPI is a clock signal, it indicates that data voltage can be transmitted through the communication interface.

[0116] like Figure 4 As shown, the frequencies of GateP(N) and GateP(N+1) are both 240Hz, in order to control T7 to turn on at high frequency, perform high-frequency reset of the anode of O1, and improve the flickering phenomenon.

[0117] like Figure 5 As shown, in at least one embodiment of the present invention, the pixel circuit may include a light-emitting element, a driving circuit, a data writing circuit, a compensation control circuit, a first light-emitting control circuit, a second light-emitting control circuit, a first initialization circuit, a second initialization circuit, and an energy storage circuit; the light-emitting element may be an organic light-emitting diode (OLED).

[0118] The first initialization circuit includes a first transistor T1, the compensation control circuit includes a second transistor, the driving circuit includes a driving transistor T3, the data writing circuit includes a fourth transistor T4, the first light-emitting control circuit includes a fifth transistor T5, the second light-emitting control circuit includes a sixth transistor T6, the second initialization circuit includes a seventh transistor T7, and the energy storage circuit includes a storage capacitor Cst.

[0119] The gate of T1 is electrically connected to the first initial control terminal, and the first initial control signal input to the first initial control terminal is the Nth level first drive signal GateN(N); the source of T1 is electrically connected to the first initial voltage terminal I1, and the drain of T1 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1; N is a positive integer;

[0120] The gate of T2 is electrically connected to the compensation control terminal, and the initial control signal connected to the initial control terminal is the first drive signal GateN(N+1) of the N+1th stage; the source of T2 is electrically connected to the first node N1, and the drain of T2 is electrically connected to the third node N3.

[0121] The gate of T3 is electrically connected to the first node N1, the source of T3 is electrically connected to the second node N2, and the drain of T3 is electrically connected to the third node N3.

[0122] The gate of T4 is electrically connected to the write control terminal, the source of T4 is electrically connected to the data line Data, and the drain of T4 is electrically connected to the second node N2; the data write control signal accessed by the write control terminal is the Nth level second drive signal GateP(N).

[0123] The gate of T5 is electrically connected to the light-emitting control terminal, which is connected to the light-emitting control signal EM; the source of T5 is electrically connected to the power supply voltage terminal VDD, and the drain of T5 is electrically connected to the second node N2.

[0124] The gate of T6 is electrically connected to the light-emitting control terminal, the source of T6 is electrically connected to the third node N3, the drain of T6 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of the organic light-emitting diode O1 is electrically connected to the low voltage terminal VSS.

[0125] The gate of T7 is electrically connected to the second initial control terminal, and the second initial control signal input to the second initial control terminal is the Nth level first reset signal ResetP(N); the source of T7 is electrically connected to the second initial voltage terminal I2, and the drain of T7 is electrically connected to the anode of O1; the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2;

[0126] The first terminal of Cst is electrically connected to the first node N1, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0127] exist Figure 5 In at least one embodiment of the pixel circuit shown, T1 and T2 are n-type transistors, and T3, T4, T5, T6 and T7 are all p-type transistors.

[0128] exist Figure 5 In at least one embodiment of the pixel circuit shown, a first GOA module can provide a compensation control signal to the compensation control circuit and a first initial control signal to the first initialization circuit; a second GOA module can provide a data writing control signal to the data writing circuit; a third GOA module can provide a second initial control signal to the second initialization circuit; and a light emission control signal generation module can provide light emission control signals to the first light emission control circuit and the second light emission control circuit.

[0129] likeFigure 6 As shown, the frequency of the first reset signal ResetP(N) of the Nth stage can be 240Hz to control T7 to turn on at high frequency, perform high-frequency reset on the anode of O1, and improve the flickering phenomenon.

[0130] like Figure 6 As shown, Figure 5 In at least one embodiment of the pixel circuit shown, the base frequency is 120Hz, the first refresh frame is labeled Ts1, and the frequency of the light emission control signal EM is 240Hz; in the first refresh frame Ts1, the frequency of the TE signal is 120Hz.

[0131] After the first refresh frame Ts1 ends, the frequency of the TE signal changes to 240Hz. During the second upward pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image, so the second frame is also a refresh frame.

[0132] In the second refresh frame Ts2, during the first high-level maintenance period of EM, the potentials of GateN(N) and GateN(N+1) rise successively to first control T1 to open to initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time that T2 is open, under the control of GateP(N), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst.

[0133] In the second refresh frame Ts2, the frequency of the TE signal is 120Hz;

[0134] After the second refresh frame Ts2 ends, the frequency of the TE signal becomes 240Hz. During the third upward pulse of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed with data voltage. At this time, it is in the first hold frame Tb1.

[0135] After the second refresh frame Ts2 ends, on the fourth upward pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image, and then enters the third refresh frame Ts3.

[0136] In the third refresh frame Ts3, during the first high-level maintenance period of EM, the potentials of GateN(N) and GateN(N+1) rise successively to first control T1 to open to initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time that T2 is open, under the control of GateP(N), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst.

[0137] After the third refresh frame Ts3 ends, the frequency of the TE signal becomes 240Hz. During the fifth and sixth pulses of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed with data voltage. At this time, it is in the second hold frame Tb2. During the seventh pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image and then enters the fourth refresh frame Ts4.

[0138] In the fourth refresh frame Ts4, during the first high-level maintenance period of EM, the potentials of GateN(N) and GateN(N+1) rise successively to first control T1 to open to initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time that T2 is open, under the control of GateP(N), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst.

[0139] After the fourth refresh frame Ts4 ends, the frequency of the TE signal becomes 240Hz. During the eighth, ninth, tenth, eleventh, twelfth and thirteenth pulses of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed by data voltage. This period is the third hold frame Tb3.

[0140] Within each hold frame, both GateN(N+1) and GateN(N) are low voltage signals.

[0141] like Figure 6 As shown, the refresh rates of the pixel circuit are 120Hz, 80Hz and 60Hz respectively.

[0142] like Figure 7As shown, in at least one embodiment of the present invention, the pixel circuit may include a light-emitting element, a driving circuit, a data writing circuit, a compensation control circuit, a first light-emitting control circuit, a second light-emitting control circuit, a first initialization circuit, a second initialization circuit, and an energy storage circuit; the light-emitting element may be an organic light-emitting diode (OLED).

[0143] The first initialization circuit includes a first transistor T1, the compensation control circuit includes a second transistor, the driving circuit includes a driving transistor T3, the data writing circuit includes a fourth transistor T4, the first light-emitting control circuit includes a fifth transistor T5, the second light-emitting control circuit includes a sixth transistor T6, the second initialization circuit includes a seventh transistor T7, and the energy storage circuit includes a storage capacitor Cst.

[0144] The gate of T1 is electrically connected to the first initial control terminal, and the first initial control signal input to the first initial control terminal is the first drive signal GateN(N-1) of the (N-1)th stage; the source of T1 is electrically connected to the first initial voltage terminal I1, and the drain of T1 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1; N is a positive integer;

[0145] The gate of T2 is electrically connected to the compensation control terminal, and the initial control signal connected to the initial control terminal is the first drive signal GateN(N) of the Nth stage; the source of T2 is electrically connected to the first node N1, and the drain of T2 is electrically connected to the third node N3.

[0146] The gate of T3 is electrically connected to the first node N1, the source of T3 is electrically connected to the second node N2, and the drain of T3 is electrically connected to the third node N3.

[0147] The gate of T4 is electrically connected to the write control terminal, the source of T4 is electrically connected to the data line Data, and the drain of T4 is electrically connected to the second node N2; the data write control signal accessed by the write control terminal is the second drive signal GateP(N+1) of the N+1th stage.

[0148] The gate of T5 is electrically connected to the light-emitting control terminal, which is connected to the light-emitting control signal EM; the source of T5 is electrically connected to the power supply voltage terminal VDD, and the drain of T5 is electrically connected to the second node N2.

[0149] The gate of T6 is electrically connected to the light-emitting control terminal, the source of T6 is electrically connected to the third node N3, the drain of T6 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of the organic light-emitting diode O1 is electrically connected to the low voltage terminal VSS.

[0150] The gate of T7 is electrically connected to the second initial control terminal, and the second initial control signal input to the second initial control terminal is the Nth stage second drive signal GateP(N); the source of T7 is electrically connected to the second initial voltage terminal I2, and the drain of T7 is electrically connected to the anode of O1; the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2;

[0151] The first terminal of Cst is electrically connected to the first node N1, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0152] exist Figure 7 In at least one embodiment of the pixel circuit shown, T1 and T2 are n-type transistors, and T3, T4, T5, T6 and T7 are all p-type transistors.

[0153] exist Figure 7 In at least one embodiment of the pixel circuit shown, a first GOA module can provide a compensation control signal to the compensation control circuit and a first initial control signal to the first initialization circuit; a second GOA module can provide a data writing control signal to the data writing circuit and a second initial control signal to the second initialization circuit; and a light emission control signal generation module can provide light emission control signals to the first light emission control circuit and the second light emission control circuit.

[0154] like Figure 8 As shown, Figure 7 In at least one embodiment of the pixel circuit shown, the base frequency is 120Hz, the first refresh frame is labeled Ts1, and the frequency of the light emission control signal EM is 240Hz; in the first refresh frame Ts1, the frequency of the TE signal is 120Hz.

[0155] After the first refresh frame Ts1 ends, the frequency of the TE signal changes to 240Hz. During the second upward pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image, so the second frame is also a refresh frame.

[0156] In the second refresh frame Ts2, during the first high-level maintenance period of EM, the potentials of GateN(N-1) and GateN(N) are raised successively to first control T1 to open to initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time included in the time period when T2 is open, under the control of GateP(N+1), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst. Before T4 is turned on, T7 is turned on to initialize the anode of O1 through Vinit2.

[0157] In the second refresh frame Ts2, the frequency of the TE signal is 120Hz;

[0158] After the second refresh frame Ts2 ends, the frequency of the TE signal becomes 240Hz. During the third upward pulse of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed with data voltage. At this time, it is in the first hold frame Tb1.

[0159] After the second refresh frame Ts2 ends, on the fourth upward pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image, and then enters the third refresh frame Ts3.

[0160] In the third refresh frame Ts3, during the first high-level maintenance period of EM, the potentials of GateN(N-1) and GateN(N) are raised successively to first control T1 to open to initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time included in the time period when T2 is open, under the control of GateP(N+1), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst. Before T4 is turned on, T7 is turned on to initialize the anode of O1 through Vinit2.

[0161] After the third refresh frame Ts3 ends, the frequency of the TE signal becomes 240Hz. During the fifth and sixth pulses of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed with data voltage. At this time, it is in the second hold frame Tb2. During the seventh pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image and then enters the fourth refresh frame Ts4.

[0162] In the fourth refresh frame Ts4, during the first high-level maintenance period of EM, the potentials of GateN(N-1) and GateN(N) are raised successively to first control T1 to open and initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time included in the time period when T2 is open, under the control of GateP(N+1), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst. Before T4 is turned on, T7 is turned on to initialize the anode of O1 through Vinit2.

[0163] After the fourth refresh frame Ts4 ends, the frequency of the TE signal becomes 240Hz. During the eighth, ninth, tenth, eleventh, twelfth and thirteenth pulses of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed by data voltage. This period is the third hold frame Tb3.

[0164] Within each hold frame, both GateN(N-1) and GateN(N) are low voltage signals.

[0165] like Figure 8 As shown, the refresh rates of the pixel circuit are 120Hz, 80Hz and 60Hz respectively.

[0166] exist Figure 8 In the diagram, the signal labeled MIPI is the communication interface control signal. When MIPI is a clock signal, it indicates that data voltage can be transmitted through the communication interface.

[0167] like Figure 8 As shown, the frequencies of GateP(N) and GateP(N+1) are both 240Hz, in order to control T7 to turn on at high frequency, perform high-frequency reset of the anode of O1, and improve the flickering phenomenon.

[0168] like Figure 9 As shown, in at least one embodiment of the present invention, the pixel circuit may include a light-emitting element, a driving circuit, a data writing circuit, a compensation control circuit, a first light-emitting control circuit, a second light-emitting control circuit, a first initialization circuit, a second initialization circuit, and an energy storage circuit; the light-emitting element may be an organic light-emitting diode (OLED).

[0169] The first initialization circuit includes a first transistor T1, the compensation control circuit includes a second transistor, the driving circuit includes a driving transistor T3, the data writing circuit includes a fourth transistor T4, the first light-emitting control circuit includes a fifth transistor T5, the second light-emitting control circuit includes a sixth transistor T6, the second initialization circuit includes a seventh transistor T7, and the energy storage circuit includes a storage capacitor Cst.

[0170] The gate of T1 is electrically connected to the first initial control terminal, and the first initial control signal input to the first initial control terminal is the first drive signal GateN(N-1) of the (N-1)th stage; the source of T1 is electrically connected to the first initial voltage terminal I1, and the drain of T1 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1; N is a positive integer;

[0171] The gate of T2 is electrically connected to the compensation control terminal, and the initial control signal connected to the initial control terminal is the first drive signal GateN(N) of the Nth stage; the source of T2 is electrically connected to the first node N1, and the drain of T2 is electrically connected to the third node N3.

[0172] The gate of T3 is electrically connected to the first node N1, the source of T3 is electrically connected to the second node N2, and the drain of T3 is electrically connected to the third node N3.

[0173] The gate of T4 is electrically connected to the write control terminal, the source of T4 is electrically connected to the data line Data, and the drain of T4 is electrically connected to the second node N2; the data write control signal accessed by the write control terminal is the Nth level second drive signal GateP(N).

[0174] The gate of T5 is electrically connected to the light-emitting control terminal, which is connected to the light-emitting control signal EM; the source of T5 is electrically connected to the power supply voltage terminal VDD, and the drain of T5 is electrically connected to the second node N2.

[0175] The gate of T6 is electrically connected to the light-emitting control terminal, the source of T6 is electrically connected to the third node N3, the drain of T6 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of the organic light-emitting diode O1 is electrically connected to the low voltage terminal VSS.

[0176] The gate of T7 is electrically connected to the second initial control terminal, and the second initial control signal input to the second initial control terminal is the Nth level first reset signal ResetP(N); the source of T7 is electrically connected to the second initial voltage terminal I2, and the drain of T7 is electrically connected to the anode of O1; the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2;

[0177] The first terminal of Cst is electrically connected to the first node N1, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0178] exist Figure 9 In at least one embodiment of the pixel circuit shown, T1 and T2 are n-type transistors, and T3, T4, T5, T6 and T7 are all p-type transistors.

[0179] exist Figure 9 In at least one embodiment of the pixel circuit shown, a first GOA module can provide a compensation control signal to the compensation control circuit and a first initial control signal to the first initialization circuit; a second GOA module can provide a data writing control signal to the data writing circuit; a third GOA module can provide a second initial control signal to the second initialization circuit; and a light emission control signal generation module can provide light emission control signals to the first light emission control circuit and the second light emission control circuit.

[0180] likeFigure 10 As shown, the frequency of the first reset signal ResetP(N) of the Nth stage can be 240Hz to control T7 to turn on at high frequency, perform high-frequency reset on the anode of O1, and improve the flickering phenomenon.

[0181] like Figure 10 As shown, Figure 9 In at least one embodiment of the pixel circuit shown, the base frequency is 120Hz, the first refresh frame is labeled Ts1, and the frequency of the light emission control signal EM is 240Hz; in the first refresh frame Ts1, the frequency of the TE signal is 120Hz.

[0182] After the first refresh frame Ts1 ends, the frequency of the TE signal changes to 240Hz. During the second upward pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image, so the second frame is also a refresh frame.

[0183] In the second refresh frame Ts2, during the first high-level maintenance period of EM, the potentials of GateN(N-1) and GateN(N) rise successively to first control T1 to open to initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time that T2 is open, under the control of GateP(N), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst.

[0184] In the second refresh frame Ts2, the frequency of the TE signal is 120Hz;

[0185] After the second refresh frame Ts2 ends, the frequency of the TE signal becomes 240Hz. During the third upward pulse of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed with data voltage. At this time, it is in the first hold frame Tb1.

[0186] After the second refresh frame Ts2 ends, on the fourth upward pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image, and then enters the third refresh frame Ts3.

[0187] In the third refresh frame Ts3, during the first high-level maintenance period of EM, the potentials of GateN(N-1) and GateN(N) rise successively to first control T1 to open to initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time that T2 is open, under the control of GateP(N), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst.

[0188] After the third refresh frame Ts3 ends, the frequency of the TE signal becomes 240Hz. During the fifth and sixth pulses of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed with data voltage. At this time, it is in the second hold frame Tb2. During the seventh pulse of the TE signal, the image generator determines that the current image to be displayed is a dynamic image and then enters the fourth refresh frame Ts4.

[0189] In the fourth refresh frame Ts4, during the first high-level maintenance period of EM, the potentials of GateN(N-1) and GateN(N) rise successively to first control T1 to open to initialize the potential of the first node N1, and then control T2 to open to control the connection between the first node N1 and the third node N3. During at least part of the time that T2 is open, under the control of GateP(N), T4 is turned on to write the data voltage Vdata provided by the data line Data to the second node, and write it to the first node N1 through the opened T2 to charge Cst.

[0190] After the fourth refresh frame Ts4 ends, the frequency of the TE signal becomes 240Hz. During the eighth, ninth, tenth, eleventh, twelfth and thirteenth pulses of the TE signal, the image generator determines that the current image to be displayed is a static image and does not need to be refreshed by data voltage. This period is the third hold frame Tb3.

[0191] Within each hold frame, both GateN(N-1) and GateN(N) are low voltage signals.

[0192] like Figure 10 As shown, the refresh rates of the pixel circuit are 120Hz, 80Hz and 60Hz respectively.

[0193] like Figure 11 As shown, the first control signal TE1 and the second control signal TE2 can be used to generate data to provide the indication signal TE;

[0194] The second control signal TE2 can be a clock signal with a fixed frequency, which can be 240Hz, 360Hz or 480Hz.

[0195] TE1 can provide a high voltage signal in the hold frame, and in the refresh frame, the frequency of TE1 is the base frequency, for example, 120Hz.

[0196] like Figure 12 As shown, the first input terminal of the AND gate ADC is connected to TE1, the second input terminal of the AND gate ADC is connected to TE2, and the AND gate ADC outputs TE.

[0197] The display control method described in this embodiment of the invention is applied to the aforementioned display control circuit. The display control method includes: after the refresh frame ends,

[0198] The display control circuit controls the frequency at which the data provides the indication signal to be a first frequency, which is 1 / n times the light emission control frequency, where n is a positive integer;

[0199] The image generator determines whether the current image is a dynamic or static image based on the current data voltage and provides the determination result to the display control circuit.

[0200] When the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a static screen, the display control circuit controls the potential of the compensation control signal to remain an ineffective voltage before the next effective voltage time period of the data providing indication signal; when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a dynamic screen, the display control circuit controls the potential of the compensation control signal to be an effective voltage during at least a portion of the next ineffective voltage time period of the light emission control signal, so as to refresh the potential of the control terminal of the driving circuit in the pixel circuit.

[0201] The embodiments of the present invention can achieve a fine frequency reduction function, which can make the screen refresh of the terminal product more timely, and the GPU (graphics processing unit) of the whole machine can display the image rendering more promptly, resulting in better screen continuity and a better user experience.

[0202] In at least one embodiment of the present invention, the pixel circuit is further connected to a data writing control signal, and the display control method further includes: after the refresh frame ends,

[0203] When the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a static screen, before the next effective voltage time period of the data providing indication signal, the display control circuit controls the potential of the data writing control signal to remain an invalid voltage;

[0204] When the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a dynamic screen, during at least a portion of the next invalid voltage period of the light emission control signal, the display control circuit controls the potential of the data writing control signal to be an effective voltage so as to perform data voltage writing.

[0205] The display panel described in at least one embodiment of the present invention includes the display control circuit described above.

[0206] The display panel described in at least one embodiment of the present invention further includes a pixel circuit, a driving integrated circuit, and an image generator;

[0207] The driver integrated circuit is used to provide data and provide indication signals;

[0208] The image generator is used to determine whether the current image is a dynamic image or a static image based on the current data voltage, and provides the determination result to the display control circuit.

[0209] The pixel circuit includes a light-emitting element, a driving circuit, a compensation control circuit, a first light-emitting control circuit, and a second light-emitting control circuit.

[0210] The control terminal of the drive circuit is electrically connected to the first node, the first terminal of the drive circuit is electrically connected to the second node, and the second terminal of the drive circuit is electrically connected to the third node. The drive circuit is used to control the connection between the second node and the third node under the control of the potential of the first node.

[0211] The control terminal of the compensation control circuit is electrically connected to the compensation control terminal, and the compensation control circuit is electrically connected to the first node and the third node respectively, and is used to control the connection between the first node and the third node under the control of the compensation control signal provided by the compensation control terminal;

[0212] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0213] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal;

[0214] The second electrode of the light-emitting element is electrically connected to the low-voltage terminal.

[0215] In at least one embodiment of the present invention, the pixel circuit further includes a data writing circuit, a first initialization circuit, and a second initialization circuit;

[0216] The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line to the second node under the control of the data writing control signal provided by the write control terminal;

[0217] The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal, and the first node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first initial control signal provided by the first initial control terminal.

[0218] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

[0219] The display device described in this embodiment of the invention includes the display panel described above.

[0220] In at least one embodiment of the present invention, the pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initialization circuit, and a second initialization circuit; the display device includes a first GOA (Gate On Array, array substrate row drive) module and a second GOA module.

[0221] The first GOA module is used to provide a compensation control signal for the compensation control circuit and a first initial control signal for the first initialization circuit;

[0222] The second GOA module is used to provide a data writing control signal for the data writing circuit and a second initial control signal for the second initialization circuit.

[0223] In at least one embodiment of the present invention, the pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initialization circuit, and a second initialization circuit; the display device includes a first GOA module, a second GOA module, and a third GOA module;

[0224] The first GOA module is used to provide a compensation control signal for the compensation control circuit and a first initial control signal for the first initialization circuit;

[0225] The second GOA module is used to provide data writing control signals for the data writing circuit;

[0226] The third GOA module provides a second initial control signal to the second initialization circuit.

[0227] The display device provided in this embodiment of the invention can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0228] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A display control circuit, included in a display panel, the display panel further comprising a pixel circuit, a driving integrated circuit, and an image generator; the driving integrated circuit is used to provide data and an indication signal; the pixel circuit receives a compensation control signal and a light emission control signal, and is used to perform threshold voltage compensation under the control of the compensation control signal, and to perform light emission control under the control of the light emission control signal; characterized in that, The display control circuit is used to control the frequency of the data providing indication signal to a first frequency after the refresh frame ends. The first frequency is 1 / n times the light emission control frequency, where n is a positive integer. The light emission control frequency is the frequency of the light emission control signal. The image generator is used to determine whether the current image is a dynamic image or a static image based on the current data voltage, and provides the determination result to the display control circuit. The display control circuit is configured to, after the refresh frame ends, when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a static screen, control the potential of the compensation control signal to remain an invalid voltage before the next effective voltage time period of the data providing indication signal; it is also configured to, after the refresh frame ends, when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a dynamic screen, control the potential of the compensation control signal to be an effective voltage during at least a portion of the next invalid voltage time period of the light emission control signal. The pixel circuit is also connected to a data write control signal. The display control circuit is further configured to, after the refresh frame ends, when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a static screen, control the potential of the data write control signal to remain an invalid voltage before the next effective voltage time period of the data providing indication signal. It is also configured to, after the refresh frame ends, when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a dynamic screen, control the potential of the data write control signal to be an effective voltage in at least a portion of the next invalid voltage time period of the light emission control signal.

2. The display control circuit as described in claim 1, characterized in that, The pixel circuit is also connected to a data writing control signal; The display control circuit is used to control the frequency of the data writing control signal to a second frequency, which is a fixed frequency.

3. The display control circuit as described in claim 2, characterized in that, The second frequency is 1 / m times the light emission control frequency, where m is a positive integer.

4. The display control circuit as described in claim 1, characterized in that, The pixel circuit is also connected to a first initial control signal, which is used to control the initialization of the potential of the control terminal of the driving circuit in the pixel circuit under the control of the first initial control signal. The display control circuit is configured to, after the refresh frame ends, when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a static screen, control the potential of the first initial control signal to remain at an invalid voltage before the next effective voltage time period of the data providing indication signal. It is also configured to, after the refresh frame ends, when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a dynamic screen, control the potential of the first initial control signal to be an effective voltage during at least a portion of the next invalid voltage time period of the light emission control signal.

5. The display control circuit as described in claim 1, characterized in that, The pixel circuit is also connected to a second initial control signal, which is used to control the initialization of the potential of the first electrode of the light-emitting element in the pixel circuit under the control of the second initial control signal; The display control circuit is used to control the frequency of the second initial control signal to a third frequency, wherein the third frequency is a fixed frequency.

6. The display control circuit as described in claim 5, characterized in that, The third frequency is 1 / a times the light emission control frequency, and m is a positive integer.

7. A display control method, applied to the display control circuit as described in any one of claims 1 to 6, characterized in that, The display control method includes: after the refresh frame ends... The display control circuit controls the frequency at which the data provides the indication signal to be a first frequency, which is 1 / n times the light emission control frequency, where n is a positive integer; The image generator determines whether the current image is a dynamic or static image based on the current data voltage and provides the determination result to the display control circuit. When the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a static screen, the display control circuit controls the potential of the compensation control signal to remain an ineffective voltage before the next effective voltage time period of the data providing indication signal; when the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a dynamic screen, the display control circuit controls the potential of the compensation control signal to be an effective voltage during at least a portion of the next ineffective voltage time period of the light emission control signal. The pixel circuit is also connected to a data write control signal, and the display control method further includes: after the refresh frame ends... When the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a static screen, before the next effective voltage time period of the data providing indication signal, the display control circuit controls the potential of the data writing control signal to remain an invalid voltage; When the potential of the data providing indication signal is an effective voltage, and when the judgment result indicates that the current screen is a dynamic screen, the display control circuit controls the potential of the data writing control signal to be an effective voltage during at least a portion of the next invalid voltage period of the light emission control signal.

8. A display panel, characterized in that, Includes the display control circuit as described in any one of claims 1 to 6.

9. The display panel as described in claim 8, characterized in that, It also includes pixel circuits, driver integrated circuits, and image generators; The driver integrated circuit is used to provide data and provide indication signals; The image generator is used to determine whether the current image is a dynamic image or a static image based on the current data voltage, and provides the determination result to the display control circuit. The pixel circuit includes a light-emitting element, a driving circuit, a compensation control circuit, a first light-emitting control circuit, and a second light-emitting control circuit. The control terminal of the drive circuit is electrically connected to the first node, the first terminal of the drive circuit is electrically connected to the second node, and the second terminal of the drive circuit is electrically connected to the third node. The drive circuit is used to control the connection between the second node and the third node under the control of the potential of the first node. The control terminal of the compensation control circuit is electrically connected to the compensation control terminal, and the compensation control circuit is electrically connected to the first node and the third node respectively, and is used to control the connection between the first node and the third node under the control of the compensation control signal provided by the compensation control terminal; The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal. The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal; The second electrode of the light-emitting element is electrically connected to the low-voltage terminal.

10. The display panel as claimed in claim 9, characterized in that, The pixel circuit also includes a data writing circuit, a first initialization circuit, and a second initialization circuit. The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line to the second node under the control of the data writing control signal provided by the write control terminal; The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal, and the first node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first initial control signal provided by the first initial control terminal. The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

11. A display device, characterized in that, Includes the display panel as described in any one of claims 8 to 10.

12. The display device as claimed in claim 11, characterized in that, The pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initialization circuit, and a second initialization circuit; the display device includes a first GOA module and a second GOA module. The first GOA module is used to provide a compensation control signal for the compensation control circuit and a first initial control signal for the first initialization circuit; The second GOA module is used to provide a data writing control signal for the data writing circuit and a second initial control signal for the second initialization circuit.

13. The display device as claimed in claim 11, characterized in that, The pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initialization circuit, and a second initialization circuit; the display device includes a first GOA module, a second GOA module, and a third GOA module. The first GOA module is used to provide a compensation control signal for the compensation control circuit and a first initial control signal for the first initialization circuit; The second GOA module is used to provide data writing control signals for the data writing circuit; The third GOA module provides a second initial control signal to the second initialization circuit.

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