Delta modulation baseline recovery for photon counting computed tomography

Abstract

One embodiment is a baseline restoration ("BLR") circuit for a non-imaging counting computed tomography ("PCCT") signal chain, the BLR circuit comprising: a comparator to compare a shaper voltage output from a shaper component of the PCCT signal chain to a baseline voltage, the comparator outputting a single bit indicating whether the shaper voltage is above or below the baseline voltage; a low pass filter connected to filter a voltage signal output from the comparator; and a transconductor connected to receive the filtered voltage signal output from the low pass filter, convert the filtered voltage signal to a current signal, and feed back the current signal to an input of the PCCT signal chain.

Description

[0001] Related Applications

[0002] This disclosure claims priority to U.S. Provisional Patent Application No. 63 / 080,315, filed September 18, 2020, entitled “Delta Modulation Baseline Recovery for Photon Counting Computed Tomography,” the disclosure of which is incorporated in its entirety by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of photon counting computed tomography (PCCT), and more specifically to delta modulation baseline recovery (BLR) techniques for PCCT. BRIEF DESCRIPTION OF DRAWINGS

[0004] For a more complete understanding of the present disclosure, and the features and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numerals indicate like parts, and in which:

[0005] Figure 1 is a schematic block diagram of a typical PCCT signal chain including a linear BLR circuit in accordance with features of certain embodiments described herein;

[0006] Figure 2 is a plot of example count curves for a PCCT signal chain enabled with linear BLR in accordance with features of certain embodiments described herein; Figure 1

[0007] Figure 3 is a plot of example undershoot effects for linear BLR of a PCCT in accordance with features of certain embodiments described herein; Figure 1

[0008] Figure 4 is a plot of idealized shaper voltages with different peak heights in accordance with features of certain embodiments described herein;

[0009] Figure 5 is a plot of idealized shaper voltages with different peak heights after linear BLR is applied in accordance with features of certain embodiments described herein;

[0010] Figure 6 is a plot of waveforms for a linear and slew rate limited BLR method in accordance with features of certain embodiments described herein;

[0011] Figure 7 is a plot of example count curves for a PCCT signal chain implementing slew rate limited BLR in accordance with features of certain embodiments described herein;

[0012] Figure 8 ​​is a plot illustrating the operating principle of a delta-sigma modulator according to features of certain embodiments described herein;

[0013] Figure 9 is a schematic block diagram of a PCCT signal chain including a delta-modulated BLR circuit according to features of certain embodiments described herein;

[0014] Figure 10 is a plot illustrating the internal waveforms of a delta-modulated BLR according to features of certain embodiments described herein; Figure 9

[0015] Figure 11 is a plot illustrating example count curves of a PCCT signal chain enabling non-linear BLR according to features of certain embodiments described herein; Figure 9

[0016] Figure 12A is a schematic block diagram of a delta-modulated BLR circuit employing clock time constant reduction and chopper stabilization according to features of certain embodiments described herein;

[0017] Figure 12B is a timing diagram of key waveforms of a delta-modulated BLR circuit according to features of certain embodiments described herein; Figure 12A

[0018] Figure 13A is a schematic block diagram of a delta-modulated BLR circuit including an auto-zero capability according to features of embodiments described herein;

[0019] Figure 13B is a timing diagram of key waveforms of a delta-modulated BLR circuit according to features of certain embodiments described herein; Figure 13A

[0020] Figure 14A is a schematic block diagram of a delta-modulated BLR circuit including chopper stabilization according to features of embodiments described herein.

[0021] Figure 14B is a timing diagram of key waveforms of a delta-modulated BLR circuit according to features of certain embodiments described herein; Figure 14A

[0022] Figure 15 is a simplified illustration of a PCCT scanning system according to features of certain embodiments described herein; and

[0023] Figure 16 is a block diagram of a computer system that can be used to implement all or part of a photon counting CT scanning system according to features of certain embodiments described herein. DETAILED DESCRIPTION​​​​​

[0024] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between" when used in relation to a measurement range includes the ends of the measurement range. The notation "A / B / C" as used herein means (A), (B), and / or (C).

[0025] This specification uses the phrases "in an embodiment" or "in embodiments," which can each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," and "having" and the like as used with respect to this disclosure are synonymous, and are used inclusively, in a manner that covers also the expressions "consisting of," "consisting essentially of," and the like. The disclosure can use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used for convenience only, and are not intended in any way to convey positional dependence or orientation. The drawings are not necessarily to scale. Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third," etc., to describe a common object, merely indicate a difference between analogous objects, and do not necessarily mean an absolute difference between the objects.

[0026] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration embodiments that can be practiced. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0027] The following disclosure describes various illustrative embodiments and examples for implementing features and functions of the present disclosure. Although specific components, arrangements and / or features are described below to illustrate the embodiments, these should not be taken as limiting the present disclosure. It will be apparent, for example, that the logical sequences of the various process steps described need not necessarily be the only sequences or sequences of steps, and that they can be supplemented, modified, or rearranged in a variety of ways. Additionally, it will be apparent that the various steps could be implemented by hardware, software, firmware, or combination thereof, and various hardware and software components could be used to implement the disclosed features and functions. Also, it will be apparent that the functionality of the disclosed embodiments could be spread across more than one component, or could be combined into a single component. Moreover, it will be apparent that the functionality of the disclosed embodiments could be implemented by a combination of components, or could be implemented by a combination of hardware and software components.

[0028] In the description, reference can be made to spatial relationships between various components and to the spatial orientation of various aspects of components as shown in the figures. However, as will be appreciated by those skilled in the art upon reading and comprehending this disclosure, the devices, components, members, devices, etc. described herein can be positioned in any desired orientation. Thus, the use of terms such as "above", "below", "upper", "lower", "top", "bottom", and other like terms to describe a spatial relationship between various components or to describe the spatial orientation of aspects of the components should be understood to describe a relative relationship between the components or a spatial orientation of aspects of the components as they can be oriented in any desired direction. The phrase "between X and Y" when used in the context of a range of dimensions or other characteristics (e.g., time, pressure, temperature, length, width, etc.) to describe an element, operation, and / or condition means that the range includes X and Y.

[0029] Furthermore, reference numerals and / or letters in the various examples can be repeated in this disclosure in order to more easily illustrate similar or related components, features, and / or structures. Such repetition of reference numerals and / or letters is in itself not to be taken as indicating a particular relationship between the various embodiments and / or configurations discussed. Example embodiments that can be employed to implement features and functionality of this disclosure will now be described in greater detail with reference to the drawings.

[0030] In a conventional computed tomography (CT) scanning system, X-rays are generated by an X-ray source, pass through an object of interest, and are converted by a collimator into light that is captured by a detector implemented as an array of photodiodes. The array of photodiodes converts the light into an analog electrical signal and converts it into a digital signal using an analog-to-digital (A / D) converter. The digital signal output from the A / D converter is used to produce a gray scale image known as a CT scan.

[0031] Photon-counting CT (PCCT) imaging is a relatively new technology that can provide significant advantages and improvements over existing CT imaging techniques as described above. A photon-counting CT system employs a photon-counting detector (PCD) that includes a semiconductor layer for implementing an array of detector pixels that record individual photon interactions with the PCD. By tracking the deposited energy of each interaction, the detector pixels of the PCD record an approximate energy spectrum as well as the intensity of the photons, making photon-counting CT a spectral or energy-resolving CT technique. In contrast, a conventional CT scanner uses an energy-integrating detector (EID) in which the total energy from one or more photons is recorded along with electronic noise deposited in the pixel over a fixed time period. Thus, the EID only records the intensity of the photons, similar to black-and-white photography. By contrast, the PCD records the intensity and spectral information of the photons, similar to color photography.

[0032] Photon-counting CT imaging turns the above three-step process into a more streamlined direct conversion from X-ray to charge through a semiconductor layer that includes PCDs. In particular, the semiconductor material used to implement the PCDs effectively turns each X-ray photon into a burst of charge proportional to the energy of the X-ray. The benefits of this technology include improved signal-to-noise, reduced X-ray dose to the patient since the same X-ray dose can achieve higher resolution, improved spatial resolution, and the ability to differentiate between multiple contrast agents and multiple types of materials / tissues by using several "energy bins."

[0033] When photons interact in a PCD, the height of the resulting electrical pulse is roughly proportional to the energy of the photon. By comparing each pulse generated in a pixel to a suitable low-energy threshold, the contribution of low-energy events (generated by photon interactions and electronic noise) can be filtered out. As a result, PCDs have a higher signal-to-noise and contrast-to-noise ratio compared to EIDs, enabling improved image quality at the same X-ray exposure level, or reduced patient X-ray dose at the same image quality.

[0034] Introducing more energy thresholds above the low-energy threshold enables the PCD to be divided into several discrete energy bins. Each registered photon is assigned to a particular bin according to its energy, such that each pixel measures a histogram of the incident X-ray spectrum. This spectral information enables a qualitative determination of the material composition of each pixel in the reconstructed CT image compared to the estimated average linear attenuation coefficient obtained in a conventional CT scan. Furthermore, using more than two energy bins enables the differentiation between dense bone and calcification and the heavier elements typically used as contrast agents, reducing the need for a reference scan prior to contrast agent injection, further reducing the X-ray dose to the patient.

[0035] Figure 1 is a schematic block diagram of an example signal processing architecture for a PCCT system 100. The system 100 includes a photon-counting detector (PCD) that includes a plurality of detector pixels, in Figure 1The forward signal path 102 from the sensor 104 includes a charge sensitive amplifier (CSA) 106 and a pulse shaper (PS) 108, followed by a counting circuit 109 that includes a set of N discriminators 110 and counters 112. In operation, X-rays impinging on the sensor 104 cause current pulses (or charge packets) to be injected into the forward signal path 102, which converts them to voltage pulses at the inputs of the discriminators 110. In particular, the current pulses are amplified by the CSA 106 and shaped by the PS 108 before being output as voltage pulses to the discriminators 110. The discriminators 110 quantize the current pulses according to their energies, and these quantized pulses are in turn counted by the counters 112. In certain embodiments, the N discriminators (or comparators) 110 each compare the pulses to N increasing voltage thresholds. This set of discriminators 110 creates a digital output of the pulses in a "thermometer code." The counters 112 can count the pulses at each level or threshold, resulting in a count that indicates how many X-ray irradiations occurred at each of the N thresholds. It will be appreciated that the thresholds are set to match different voltages corresponding to different energy photons.

[0036] It will be appreciated that the sensor 104 includes a significant component of slowly varying leakage current. If uncompensated, this leakage current would pass through the forward signal chain and create an offset at the inputs of the discriminators 110, thereby distorting the measured spectrum. To counteract this effect, a baseline restorer (BLR) 114 is provided in the system 100. The BLR 114 creates a slow negative feedback loop around the CSA 106 and PS 108 that adjusts the long-term value of the PS output to some desired voltage by injecting a slowly varying current at the CSA 106 input. This BLR circuit uses a linear voltage gain stage 116 referenced to a baseline voltage V bl The BLR 114 will adjust the average shaper output voltage (shapper_out) if implemented with linear circuitry. If the flux rate is low, meaning that the input signal current due to X-ray flux is small compared to the leakage current, this is equivalent to adjusting the baseline voltage of the shaper 108 output.

[0037] Conversely, if the flux rate is high, meaning that the input signal current due to X-ray flux is significant compared to the leakage current, a problem commonly referred to as "droop" can occur. In particular, in response to high flux rate conditions, the BLR 114 will successfully cancel the leakage current; however, due to the average stimulus current I stim The fact that it will include a significant contribution from the input signal current, the baseline of the shaper output voltage will be significantly less than the baseline voltage (Vbl The BLR circuit has no way of distinguishing between the leakage current and the input signal current, so it effectively eliminates both. The resulting measured spectrum includes a shift to lower energies, because each charge pulse (if it can be distinguished from other pulses) starts from a lower baseline.

[0038] The effect of undershooting can be observed in Figure 2 , Figure 2 shows a plot of the counter output for each of the five counter bins of an example frame illustrating the actual generated events for each bin (i.e., the "energy ground truth" or "EGT"). As Figure 2 shown in the example, waveforms 200A and 200B correspond to the EGT and counter output for bin 0, respectively. Waveforms 202A and 202B correspond to the EGT and counter output for bin 1, respectively. Waveforms 204A and 204B correspond to the EGT and counter output for bin 2, respectively. Waveforms 206A and 206B correspond to the EGT and counter output for bin 3, respectively. Single waveform 208 corresponds to the EGT and counter output for bin 4. Waveforms 210A and 210B correspond to the total EGT and counter output for all bins, respectively. An increase in counts of approximately 10-20 Mega counts per second (Mcps) relative to the ground truth can be observed in bins 0 and 1, which serves as evidence that undershooting causes the miscounting of higher energy events in lower energy bins.

[0039] In general, the BLR is effective enough at eliminating leakage current that the difference between the count results for a 50 nA leakage current and a 0 nA leakage current can be negligible, and the undershooting effect is practically the same in both cases.

[0040] Table 1 below illustrates the effectiveness of the BLR in eliminating leakage current, as well as the undershooting problem. Each column in Table 1 represents a simulation of a single frame at high flux (30 Mcps) at different delay times (ps) after a zero flux step change. In other words, each column effectively represents the same X-ray sequence superimposed on different leakage currents from near zero to 30 nA. The changes between columns in Table 1 are minimal, indicating that the leakage current elimination is successful. Without the BLR, the counts would have shifted significantly to higher bins and increased delay; however, a significant spectral shift toward lower bins can be observed in all columns due to the overshooting effect.

[0041]

[0042] Table 1

[0043] Reference is now made to Figure 3 where the waveforms shown illustrate the results of another experiment demonstrating the BLR undershooting effect. In particular, Figure 3The waveforms shown in FIG. 6 are the results of a series of example simulations using a 10 Mcps, 50 kiloelectron-volt (keV) periodic tone superimposed on a real spectrum at varying flux rates. A threshold scan was used to capture the output spectrum. The spectral flux was kept low so that the tone was clearly visible in the output spectrum.

[0044] Waveform 300A represents the observed tone at 1 nA flux with the BLR off. In contrast, waveform 300B represents the observed tone at 1 nA flux with the BLR on. It is apparent from a visual comparison of waveforms 300A and 300B that there is no observable difference in the spectrum at 1 nA flux whether the BLR is on (waveform 300B) or off (waveform 300A). Waveform 302A represents the observed tone at 10 nA flux with the BLR off. In contrast, waveform 302B represents the observed tone at 10 nA flux with the BLR on. It is apparent from a visual comparison of waveforms 302A and 302B that there is a shift in the observed tone to lower energies when the BLR is on. There is no shift in the observed tone at 10 nA flux with the BLR off. Waveform 304A represents the observed tone at 10 nA flux and 50 nA leakage current with the BLR on. In contrast, waveform 304B represents the observed tone at 10 nA flux and 50 nA leakage current and is identical to waveform 302B. As Figure 3 As shown in the comparison of waveforms 304A and 304B, once leakage current is applied, the energy spectrum of the observed tone shifts significantly higher with the BLR off and remains at the same energy level with the BLR on. This result is summarized in Table 2 below.

[0045]

[0046] Table 2

[0047] While undershoot is undesirable, the benefits of using a BLR to eliminate leakage current far outweigh the cost. The undershoot effect is a response to flux changes, which are deterministic. There is an opportunity to correct for this in post-processing. Leakage current can also vary from frame to frame even if the flux remains constant. In addition, leakage current can vary from pixel to pixel or as the sensor ages or temperature changes. Therefore, eliminating leakage current is much more important than avoiding the undershoot effect. Thus, it is desirable to use a BLR loop and the BLR loop must have sufficient loop gain to offset a significant portion of the leakage current.

[0048] It can be shown that undershoot is unavoidable in a linear BLR circuit, but nonlinear feedback can be used to ameliorate undershoot to some extent. Consider Figure 4The idealized example shown in FIG. 6 illustrates shaper voltages without BLR for two events (cases 1 and 2, respectively) with the same baseline voltage and timing but different peak energies. If a linear BLR method is applied to attempt to restore the baseline voltage to zero, one obtains Figure 5 the shaper voltages shown. Case 2 undershoots much more than case 1 because the event contributes more to the average; however, the BLR circuit can simply clip the event in case 2 to make it look like case 1. This demonstrates that a nonlinear gain function can effectively reduce undershoot.

[0049] According to a feature of prior art embodiments, the BLR circuit can include a slew rate limiter that suppresses feedback in response to large positive pulses. This approach can reduce undershoot. A slew rate limited BLR circuit can be implemented by simply modifying linear BLR to include a limiter on the output of the initial gain stage. Figure 6 Operation of an example slew rate limited BLR with a stimulus flux of 18.75 Mcps is shown. Waveforms 600A and 600B <blr>v(e0_pout) and -l: <blr>v(e0_pout) corresponds to the output of the initial voltage gain stage in a circuit employing non- slew-rate limited BLR and a circuit employing slew-rate limited BLR, respectively. In the representation of the slew-rate limited variant (-l: <blr>In the waveform 600B of v(e0_pout), the charging event is truncated to 0.2V. Waveforms 602A and 602B (( <blr>v(filt) and -l: <blr>v(filt) represents the internal voltage after the integrator in a circuit using a non-slew rate limited BLR and a line using a slew rate limited BLR, respectively. Waveforms 604A and 604B (v(shaper_out) and -l:v(shaper_out)) represent the shaper voltage in a circuit using a non-slew rate limited BLR and a line using a slew rate limited BLR, respectively. Figure 6 As shown, the undershoot is reduced by the slew rate limiting version of the BLR. It can be proven that the response to leakage current is equivalent to that of a linear BLR.

[0050] Figure 7 This demonstrates the use of BLRs with limited conversion rates. Figure 2 The same example frame of PCCT data illustrates a graph of the actual generated events (i.e., "Energy Surface Reality" or "EGT") for each of the five counters relative to the counter outputs of each of the five counters. Figure 7 As shown in the example, waveforms 700A and 700B correspond to the EGT and counter output of bin 0, respectively. Waveforms 702A and 702B correspond to the EGT and counter output of bin 1, respectively. Waveforms 704A and 704B correspond to the EGT and counter output of bin 2, respectively. Waveforms 706A and 706B correspond to the EGT and counter output of bin 3, respectively. A single waveform 708 corresponds to the EGT and counter output of bin 4. Waveforms 710A and 710B correspond to the total EGT and counter output of all bins, respectively. Figure 7 The curve shown is Figure 2 The comparison of the curves shown demonstrates that the reduction in downslip achieved by the rate-limited BLR improves the correspondence between the count curve and the ground truth; however, a significant increase in counts relative to the ground truth can still be observed in bins 0 and 1.

[0051] As is evident from the example described above with a BLR that references a slew rate limitation, limiting the range of the feedback can provide some suppression of the signal current. Therefore, a feedback loop with infinite gain but a finite range before the integrator would be equivalent to replacing the initial gain stage with a comparator plus a one-bit DAC. A Δ pulse width modulator (ΔPWM) or a simple Δ modulator produces an output that tracks the input with 1-bit feedback; such a modulator only cares whether the output is above or below the input. The result is a nonlinear gain function when the loop goes out of control, which may be advantageous for the embodiments described herein.

[0052] Figure 8 The operating principle of the Δ modulator is illustrated. For example... Figure 8 As shown, the analog output signal 800 is compared to upper and lower limits 802A, 802B, which correspond to the reference signal 804 offset by a given value. Each time the output signal 800 reaches one of the limits 802A, 802B, the delta modulator changes state, as shown by the waveform 806.

[0053] By replacing the linear gain stage 116 with a comparator, the BLR loop of the circuit 100 Figure 1 can be modified to behave like a delta modulator. In this configuration, the low pass filter acts as an integrator in the delta modulator. Figure 9 A schematic block diagram of an example signal processing architecture for a PCCT system 900 having a BLR loop modified to function as a delta modulator in accordance with features of the embodiments described herein is shown. The system 900 includes a photon counting detector (PCD) including a plurality of detector pixels, represented in Figure 9 by detector pixels 901. The forward signal path 902 from the sensor 904 includes a CSA 906 and a PS 908 followed by a counting circuit 909 including a set of N discriminators 910 and counters 912. In operation, X-rays emitted from an X-ray source pass through an object of interest and impinge on the sensor 904, causing current pulses (or charge packets) to be injected into the forward signal path 902, which converts them to voltage pulses at the inputs of the discriminators 910. In particular, the current pulses are amplified by the CSA 906 and shaped by the PS 908 before being output as voltage pulses to the discriminators 910. The discriminators 910 quantize the current pulses according to their energies, and these quantized pulses are in turn counted by the counters 912. In certain embodiments, the N discriminators (or comparators) 910 each compare the pulses to N increasing voltage thresholds. This set of discriminators 910 creates a pulse digital output in a "thermometer code.” The counters 912 can count the pulses at each level or threshold, resulting in a count value that represents how many X-ray irradiations occurred at each of the N thresholds. It will be appreciated that the thresholds are set to match different voltages corresponding to different energy photons.

[0054] For the reasons detailed above, a BLR 914 is provided in the system 900. The BLR 914 creates a slow negative feedback loop around the CSA 906 and PS 908 that adjusts the long-term value of the PS output to some desired voltage by injecting a slowly varying current to the CSA 906 input. This BLR circuit 914 is a delta modulated BLR circuit in accordance with features of the embodiments described herein. As such, instead of a linear voltage gain stage 116 Figure 1 , the BLR 914 includes a reference to a desired baseline voltage V bl to a comparator 916. The comparator 916 is followed by a low pass filter 918 and finally a transconductor 920. In this configuration, the low pass filter 918 acts as an integrator for the delta modulator.

[0055] The behavior simulation described above with respect to the linear BLR can be modified to use such a delta modulated BLR with the same time constant as the original linear BLR. Figure 10 Figures such as Figure 9 The internal waveforms of the delta modulated BLR are shown. The comparison between the shaper output (shapper_out) 1000 and the baseline setpoint (vbl) 1002 produces a 1-bit feedback (pout) 1004 (vbl - shapper_out) 1002 Figure 9 at node pout in 1000. The feedback voltage pout is integrated to produce the filter voltage (filt) 1006. The feedback current is linearly proportional to the integrated voltage.

[0056] Figure 11 A plot of the count curve is shown, which shows for the same example frame of PCCT data Figure 2 and Figure 7 BLR using delta modulation, e.g., as shown in Figure 9 For each of the five counter bins, the actual generated events (i.e., "energy ground truth" or "EGT") for each bin are shown in relation to the counter output. As shown in the example shown in Figure 11 Waveforms 1100A and 1100B correspond to the EGT and counter output for bin 0, respectively. Waveforms 1102A and 1102B correspond to the EGT and counter output for bin 1, respectively. Waveforms 1104A and 104B correspond to the EGT and counter output for bin 2, respectively. Waveforms 1106A and 1106B correspond to the EGT and counter output for bin 3, respectively. Single waveform 1108 corresponds to the EGT and counter output for bin 4. Waveforms 1110A and 1110B correspond to the total EGT and counter output for all bins, respectively. As shown in Figure 11 The plots shown in Figure 2 and Figure 7 The reduction in undershoot achieved by the slew rate limited BLR improves the correspondence of the count curve to ground truth. In particular, it will be noted that the performance of the delta modulated BLR is significantly better than the corresponding linear BLR and slew rate limited BLR in medium to high throughputs.

[0057] It will be recognized that there are two practical problems with implementing BLR circuits on an IC. One is that the offset of the CMOS amplifier itself will cause baseline variation and drift because it defines the virtual ground of the system. Second, the passive components (resistors or current sources and capacitors) required to define the BLR low-pass pole can be very large when implemented on a chip. The Δ-modulated BLR circuit described in this paper provides a solution to both of these problems.

[0058] The clock circuit can be implemented to slow down the time constant without increasing the size of the on-chip passive components. Once the BLR circuit is timing, a chopper stabilization can be applied to bring the input comparator offset to zero. Alternatively, an auto-zero function can be applied to bring the input comparator offset to zero. It will be noted that applying these techniques to a linear BLR circuit without introducing glitches or noise at the comparator input is difficult.

[0059] Figure 12A A schematic block diagram of a clock BLR circuit 1200, featuring features according to an embodiment described herein, is shown. Comparator 1202 generates a digital signal POUT based on a comparison of the input signals SHAPER_OUT and VBL. Signal POUT is processed using an AND gate 1204 along with a clock signal CLK to generate signal UP. This signal is asserted with the same timing as the CLK signal when the feedback circuit indicates that IBLR should be increased to bring SHAPER_OUT closer to VBL. A pulse is generated on the UP signal, causing switch 1206 to conduct for a period of time. This, in turn, causes a current pulse from current source 1208 to be conducted to filter capacitor 1214. The current pulse increases voltage FILT by an amount determined by the timing and value of the pulse from current source 1208. Similarly, the inversion of POUT is processed using an AND gate 1207 along with CLK to generate signal DN. This signal is asserted with the same timing as the CLK signal when the feedback circuit indicates that IBLR should be decreased to bring SHAPER_OUT closer to VBL. A pulse is generated on the DN signal, causing switch 1210 to conduct for a period of time. This causes a current pulse from current source 1212 to be conducted to filter capacitor 1214. The current pulse reduces voltage FILT by an amount determined by the pulse timing and value of current source 1208.

[0060] Figure 12B As shown Figure 12A The timing diagram of the key waveforms of the BLR circuit 1200 is shown. The current integrates only over the capacitor with the duty cycle defined by CLK, which allows the same time constant to be achieved using a smaller capacitor. Since the comparator only needs to sample once per CLK pulse, the dead time can be used to achieve chopper stabilization controlled by the signal Φ.

[0061] Figure 13A A schematic block diagram of a delta-modulation BLR circuit 1300 including auto-zero capability according to features of embodiments described herein is shown. The auto-zero capability allows the comparator or amplifier 1302 to periodically measure its own offset using a first auto-zero phase and store the offset in order to cancel its influence during a second measurement phase. Many examples of auto-zero functionality for comparators and amplifiers are well known. In order to use auto-zero functionality for a delta-modulation BLR circuit, a second timing signal AZ is generated. AZ is asserted during the periods when CLK is not asserted. Thus, during the periods when the output of the comparator will be ignored, the comparator offset can be calibrated out. Note that these unused periods are not available in a conventional linear BLR. Figure 13B A timing diagram of key waveforms for the BLR circuit 1300 as Figure 13A shown is shown.

[0062] Figure 14A A schematic block diagram of a delta-modulation BLR circuit 1400 including chopper stabilization according to features of embodiments described herein is shown. Chopper stabilization is a technique used to cancel amplifier offset. In a conventional chopper stabilization scheme, the input signal is first inverted and then applied to the amplifier. The output of the amplifier is again inverted and passed through a low-pass filter that rejects signals at the chopper frequency. For the signal applied to the amplifier, these two inversions cancel and there is no net effect. But the offset in the amplifier is modulated to the chopper frequency and removed by the low-pass filter. Thus, a chopper-stabilized amplifier can appear to have no offset. In order to implement a chopper stabilization scheme for a delta-modulation BLR, a chopper signal PHI is generated that has twice the period of CLK. The input signals SHAPER_OUT and VBL are applied to a crosspoint switch 1401 that passes them directly to a comparator 1403 for the first digital value of PHI and crosses them for the second digital value of PHI. The output POUT of the comparator 1402 and PHI are applied to an XOR gate 1403 that inverts the output signal. Thus, the result of the comparison has no DC contribution from the comparator offset. Note that a linear BLR circuit does not provide the opportunity to activate the crosspoint switch 1401 and XOR gate 1403 without potentially introducing glitches and / or artifacts on the BLR output signal IBLR. Figure 14B A timing diagram of key waveforms for the BLR circuit 1400 as Figure 14A shown is shown.

[0063] Figure 15 A PCCT 1500 including an X-ray source 1502 that generates X-rays 1504 that pass through an object of interest 1506 and impinge on a system 1508 that can use the system 900 Figure 9 ) to be implemented, e.g., including a PCD for converting received X-rays and processing the converted signals, as described herein.

[0064] Figure 16 is a block diagram illustrating an example system 1700 that can be configured to implement at least a portion of the techniques in accordance with the embodiments described herein, and more specifically, as shown in the figures described above. As shown, the system 1700 can include at least one processor 1702, e.g., a hardware processor 1702, coupled to a memory element 1704 by a system bus 1706. As such, the system can store program code and / or data within memory element 1704. Further, processor 1702 can execute the program code and / or data accessed from memory element 1704 via system bus 1706. In one aspect, the system can be implemented as a computer suitable for storing and / or executing program code. However, it should be appreciated that the system 1700 can be implemented in the form of any system including a processor and memory that enables it to perform the functions described in the present disclosure. Figure 16

[0065] In some embodiments, the processor 1702 can execute software or an algorithm to perform the activities discussed in this specification; in particular, the activities related to the embodiments described herein. The processor 1702 can include any combination of hardware, software, or firmware providing programmable logic, including, as non-limiting examples, a microprocessor, a DSP, a field-programmable gate array (FPGA), a programmable logic array (PLA), an integrated circuit (IC), an application-specific IC (ASIC), or a virtual machine processor. The processor 1702 can be communicatively coupled to the memory element 1704, e.g., in a direct memory access (DMA) configuration, such that the processor 1702 can read from or write to the memory element 1704.

[0066] ​Generally, memory elements 1704 can include any suitable volatile or non-volatile storage, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash memory, read-only memory (ROM), optical media, virtual memory, magnetic or tape memory, or any other suitable technology. Unless otherwise specified, any memory elements discussed herein should be interpreted as including a broad "memory" in the general sense of the term. Information measured, processed, tracked, or transmitted to or from any component of system 1700 can be provided in any database, register, control list, cache, or storage structure, all of which can be referenced at any suitable period of time. Any such storage options can be included in the broad "memory" used herein. Similarly, any potential processing elements, modules, and machines described herein should be interpreted as including a broad "processor" in the general sense of the term. Each element shown in this figure can also include suitable interfaces for receiving, transmitting, and / or otherwise communicating data or information in a network environment, such as a system having similar or identical hardware to another one of these elements.

[0067] In certain example implementations, mechanisms for implementing the embodiments outlined herein can be realized by logic encoded in one or more tangible media (e.g., embedded logic provided in an ASIC, software programming at least partially implemented by a processor, or software (potentially inclusive of object code and source code) that is stored on a non-transitory medium and executed by a processor or a similar machine, in some of these instances, such as the memory elements 1704 shown in FIG. 17, can be used to store the data or information necessary to perform the activities described herein. Figure 16 Memory elements, such as the memory elements 1704 shown in FIG. 17, can store data or information used by the operations described herein. This includes the memory elements being able to store software, logic, code, or processor instructions that are executed to carry out the activities described herein. A processor can execute any type of instructions associated with the data or information to achieve the operations detailed herein. In one example, the processor, such as the processor 1702 shown in FIG. 17, could transform an element or an article (e.g., data) from one state or thing to another state or thing. Figure 16 In another example, the activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software / computer instructions executed by a processor) and the identified elements can be some type of programmable processor, programmable digital logic (e.g., a FPGA, DSP, an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM)) or an ASIC that includes digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0068] Memory element 1704 may include one or more physical memory devices, such as local memory 1708 and one or more mass storage devices 1170. Local memory may refer to RAM or other non-persistent memory devices typically used during the actual execution of program code. Mass storage devices may be implemented as hard disk drives or other persistent data storage devices. Processing system 1700 may also include one or more cache memories (not shown) that provide temporary storage for at least some program code to reduce the number of times program code must be retrieved from mass storage device 1170 during execution.

[0069] like Figure 16 As shown, memory element 1704 can store the energy storage event counting module 1720. In various embodiments, module 1720 can be stored in local memory 1708, one or more mass storage devices 1170, or separately from local memory and mass storage devices. It should be understood that system 1700 can further execute an operating system (…). Figure 16 (Not shown in the image), the operating system can facilitate the execution of module 1720. Module 1720, implemented in the form of executable program code and / or data, can be read, written to, and / or executed by system 1700, for example, by processor 1702. In response to reading from, writing to, and / or executing module 1720, system 1700 can be configured to perform one or more of the operational or method steps described herein.

[0070] Optionally, the input / output (I / O) devices depicted as input device 1712 and output device 1714 may be coupled to the system. Examples of input devices may include, but are not limited to, a keyboard, a pointing device such as a mouse, etc. Examples of output devices may include, but are not limited to, a monitor or display, a speaker, etc. In some implementations, the system may include a device driver (not shown) for output device 1714. Input and / or output devices 1712, 1714 may be coupled to system 1700 directly or via an intervening I / O controller. Furthermore, sensor 1715 may be coupled to system 1700 directly or via an intervening controller and / or driver.

[0071] In one embodiment, the input and output devices can be implemented as a combined input / output device (in... Figure 16 (Input device 1712 and output device 1714 are shown surrounded by dashed lines). An example of such a combined device is a touch-sensitive display, sometimes also called a "touchscreen display" or simply a "touchscreen". In such embodiments, input to the device can be provided by moving a physical object (e.g., a user's stylus or finger) on or near the touchscreen display.

[0072] Optionally, a network adapter 1716 can also be coupled to the system 1700 to enable it to become coupled to other systems, computer systems, remote network devices, and / or remote storage devices through intervening private or public networks. The network adapter can comprise a data receiver for receiving data that is transmitted to the system 1700 by the systems, devices, and / or networks, and a data transmitter for transmitting data from the system 1700 to the systems or networks. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that can be used with the system 1700.

[0073] As previously described, when the average of the signal current is high enough, undershoot occurs such that the cancellation of it by the BLR circuit results in a significant negative shift in the baseline. Although the BLR does distort the measured spectrum by undershoot, the benefits of the BLR in canceling the leakage current outweigh the distortion effects. In accordance with the features of the above-described embodiments, the non-linear BLR circuit, which behaves like a delta modulator, reduces the impact of large shaper peaks, resulting in less undershoot. The use of a hybrid signal delta modulator enables a clocked version of the BLR circuit, which can achieve smaller silicon area and eliminate amplifier offset.

[0074] Example 1 is a baseline restoration ("BLR") circuit for a photon counting computed tomography ("PCCT") signal chain, the BLR circuit comprising: an input comparator to compare a shaper voltage output from a shaper component of the PCCT signal chain to a baseline voltage, the input comparator outputting a single bit indicating whether the shaper voltage is higher or lower than the baseline voltage; and a low pass filter connected to filter a voltage signal output from the input comparator.

[0075] In Example 2, the BLR circuit of Example 1 can further comprise: a transconductor connected to receive the filtered voltage signal output from the low pass filter, convert the filtered voltage signal to a current signal, and feed back the current signal to an input of the PCCT signal chain.

[0076] In Example 3, the BLR circuit of any of Examples 1-2 can further comprise: a delta modulator circuit to provide a non-linear BLR.

[0077] In Example 4, the BLR circuit of Example 3 can further comprise: the low pass filter comprises an integrator of the delta modulator circuit.

[0078] In Example 5, the BLR circuit of any of Examples 1-4 can further comprise: the BLR circuit comprises a feedback loop that acts as a delta modulator.

[0079] In Example 6, the BLR circuit of any of Examples 1-5 can further comprise: the BLR circuit is clocked.

[0080] In Example 7, the BLR circuit of any of Examples 1-6 can further include that chopper stabilization is applied to zero out an offset of the input comparator.

[0081] In Example 8, the BLR circuit of any of Examples 1-7 can further include that an auto-zeroing technique is applied to zero out an offset of the input comparator.

[0082] In Example 9, the BLR circuit of any of Examples 1-8 can further include that the BLR circuit is clocked and chopper stabilization is applied to zero out an offset of the input comparator.

[0083] In Example 10, the BLR circuit of any of Examples 1-9 can further include that the BLR circuit is clocked and an auto-zeroing technique is applied to zero out an offset of the input comparator.

[0084] Example 11 is a method for implementing non-linear baseline restoration ("BLR") in conjunction with a photo-counting computed tomography ("PCCT") signal chain, the method comprising: comparing a shaper voltage output from a shaper component of the PCCT signal chain to a baseline voltage to produce a comparator voltage indicative of whether the shaper voltage is above or below the baseline voltage at a given time; filtering the comparator voltage; and converting the filtered voltage signal to a current signal.

[0085] In Example 12, the method of Example 11 can further include feeding back the current signal to an input of the PCCT signal chain.

[0086] In Example 13, the method of any of Examples 11-12 can further include that the comparing, filtering, converting, and feeding are performed by a delta modulation circuit.

[0087] In Example 14, the method of any of Examples 11-13 can further include that the comparing and filtering are clocked.

[0088] In Example 15, the method of any of Examples 11-14 can further include applying chopper stabilization to zero out an offset of an input comparator of the PCCT signal chain.

[0089] In Example 16, the method of any of Examples 11-15 can further include applying an auto-zeroing technique to zero out an offset of an input comparator of the PCCT signal chain.

[0090] In Example 17, the method of any of Examples 11-16 can further include that the comparing and filtering are clocked and chopper stabilization is applied to zero out an offset of an input comparator of the PCCT signal chain.

[0091] In Example 18, the method of any of Examples 11-17 can further include that the filtering is performed using a low-pass filter.

[0092] In Example 19, the method of any of Examples 11-18 can further include applying a low duty cycle clock signal to the low-pass filter to increase a value of a time constant.

[0093] Example 20 is a photon counting detector ("PCD") comprising: a sensor to record an interaction with a photon received at the PCD and to forward a pulse indicative of the interaction to a signal chain; and a baseline restoration ("BLR") circuit connected to the signal chain, the BLR circuit comprising an input comparator to compare a voltage pulse output from the signal chain to a baseline voltage, the input comparator outputting a single bit indicating whether the shaper voltage is above or below the baseline voltage; and a low-pass filter connected to filter a voltage signal output from the input comparator.

[0094] In Example 21, the PCD of Example 20 can further include that the BLR circuit further comprises a transconductor connected to receive a filtered voltage signal output from the low-pass filter, to convert the filtered voltage signal to a current signal, and to feed back the current signal to an input of the signal chain.

[0095] In Example 22, the PCD of any of Examples 20-21 can further include that the BLR circuit comprises delta modulator circuitry to provide a non-linear BLR.

[0096] In Example 23, the PCD of any of Examples 20-22 can further include that the signal chain comprises: a charge sense amplifier ("CSA") to amplify a pulse received from the sensor and output an amplified pulse; and a pulse shaper ("PS") to shape the amplified pulse and produce a voltage pulse output from the signal chain.

[0097] In Example 24, the PCD of any of Examples 20-23 can further include a counting circuit to classify and count the voltage pulses output from the signal chain.

[0098] In Example 25, the PCD of any of Examples 20-24 can further include that the BLR circuit comprises a feedback loop that functions as a delta modulator.

[0099] In Example 26, the PCD of any of Examples 20-25 can further include that the BLR circuit is timed.

[0100] In Example 27, the PCD of any of Examples 20-26 can further include applying chopper stabilization in the BLR circuit to zero the offset of the input comparator.

[0101] In Example 28, the PCD of any of Examples 20-27 can further include applying an auto-zeroing technique in the BLR circuit to zero the offset of the input comparator.

[0102] In Example 29, the PCD of any of Examples 20-28 can further include that the BLR circuit is timed, and chopper stabilization is applied to zero the offset of the input comparator.

[0103] Example 30 is a photon counting computed tomography ("PCCT") system, comprising an x-ray source to generate x-ray photons; and a photon counting detector ("PCD") comprising a sensor to record an interaction with an x-ray photon received at the PCD after passing through an object of interest and to forward a pulse indicative of the interaction to a signal chain; and a baseline restoration ("BLR") circuit connected to the signal chain, the BLR circuit comprising an input comparator to compare a voltage pulse output from the signal chain to a baseline voltage, the input comparator outputting a single bit indicating whether the shaper voltage is above or below the baseline voltage; and a low pass filter connected to filter a voltage signal output from the input comparator.

[0104] In Example 31, the PCCT system of Example 30 can further include that the BLR circuit further comprises a transconductor connected to receive the filtered voltage signal output from the low pass filter, to convert the filtered voltage signal to a current signal, and to feed back the current signal to an input of the signal chain.

[0105] In Example 32, the PCCT system of any of Examples 30-31 can further include that the BLR circuit comprises a delta modulator circuit to provide a non-linear BLR.

[0106] In Example 33, the PCCT system of any of Examples 30-32 can further include that the signal chain comprises a charge sense amplifier ("CSA") to amplify a pulse received from the sensor and output an amplified pulse; and a pulse shaper ("PS") to shape the amplified pulse and generate the voltage pulse output from the signal chain.

[0107] In Example 34, the PCCT system of any of Examples 30-33 can further include a counting circuit to classify and count the voltage pulses output from the signal chain.

[0108] In Example 35, the PCCT system of any of Examples 30-34 can further include that the BLR circuit includes a feedback loop that functions as a delta modulator.

[0109] In Example 36, the PCCT system of any of Examples 30-35 can further include that the BLR circuit is timed.

[0110] In Example 37, the PCCT system of any of Examples 30-36 can further include that a chopper stabilization is applied in the BLR circuit to zero out the offset of the input comparator.

[0111] In Example 38, the PCCT system of any of Examples 30-37 can further include that an auto-zeroing technique is applied in the BLR circuit to zero out the offset of the input comparator.

[0112] In Example 39, the PCCT system of any of Examples 30-38 can further include that the BLR circuit is timed and a chopper stabilization is applied to zero out the offset of the input comparator.

[0113] It should be noted that all specifications, dimensions and relationships (e.g., number of elements, operations, steps, etc.) outlined herein are for example and instructional purposes only. Such information can be varied significantly without departing from the spirit of the disclosure or the scope of the appended claims. The present specification is applicable to one non-limiting example only, and as such, should be construed as a non-limiting example. In the foregoing description, example embodiments have been described with reference to particular arrangements of parts. Various modifications and changes can be made to such embodiments without departing from the scope of the appended claims. The description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

[0114] Note that in the numerous examples provided herein, interactions can be described in terms of two, three, four, or more electrical components. However, this has only been for purposes of clarity and example, and is not intended to limit the application to a particular number of electrical components as such. It should be understood that the system can be combined in any suitable manner. According to similar design alternatives, any of the components, modules, and elements shown in the drawings can be combined in various possible configurations, all of which are clearly within the broad scope of the specification. In certain cases, it can be easier to describe one or more functions and features of a given set of flows by only referencing a limited number of electrical components. It should be appreciated that the circuits of the figures and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated / sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as potentially applied to a myriad of other architectures.

[0115] It should also be noted that reference to various features, e.g., elements, structures, modules, components, steps, operations, characteristics, etc., that are included in "one embodiment", "an example embodiment", "one specific embodiment", and "another embodiment", etc., is intended to mean that any such features are included in one or more embodiments of the present disclosure, but can or can not be combined in the same embodiment.

[0116] It should also be noted that the functions related to the circuit architecture only show some possible circuit architecture functions that can be performed by or within the systems shown in the figures. Some of these operations can be deleted or removed where appropriate, or new operations can be added or changed significantly, without departing from the scope of the present disclosure. Also, the order in which the operations are described is not necessarily the order in which the operations are performed. The preceding operations flow is provided for ease of discussion and explanation. Embodiments described herein provide significant flexibility, as any suitable arrangement, chronology, configuration and timing mechanism can be provided without departing from the teachings of the present disclosure.

[0117] Many other changes, substitutions, variations, alterations, and modifications can be ascertained to one of ordinary skill in the art and it is the intent, therefore, to encompass all such changes, substitutions, variations, alterations, and modifications as fall within the scope of the appended claims.

[0118] Note that all optional features of the devices and systems described above can also be implemented with respect to the methods or processes described herein, and the details of the examples can be used anywhere in one or more embodiments.

[0119] "Means" in these instances (as above) can include, but are not limited to, using any suitable components discussed herein, as well as any suitable software, circuitry, hubs, computer code, logic, algorithms, hardware, controllers, interfaces, links, buses, communication paths, etc.

[0120] Note that for the examples provided above, as well as many other examples provided herein, the interactions can be described in terms of two, three, or four network elements. However, this is done for clarity and illustration only. In some cases, it can be easier to describe one or more functions of a given flow set by referring to only a limited number of network elements. It should be understood that the topologies shown in the drawings (and their teachings) are easily scalable and can accommodate a large number of components as well as more complex / complicated arrangements and configurations. Thus, the examples provided should not limit the scope of the topology shown or detract from its broad teachings, as it can apply to innumerable other architectures.

[0121] It is also important to note that the steps in the preceding flowcharts illustrate some possible signaling scenarios and patterns that can be performed by or within the communication system shown in the figures. Some of these steps can be deleted or removed where appropriate, or these steps can be modified or changed considerably, without departing from the scope of the present disclosure. In addition, many of the operations have been described as occurring simultaneously or in parallel with one another. However, the timing of these operations can be varied considerably. The preceding operational flows are provided for purposes of example and discussion. The communication system shown in the figures provides a great deal of flexibility, as any suitable arrangement, chronology, configuration, and timing mechanism can be provided without deviating from the teachings of the present disclosure.

[0122] Although the present disclosure has been described in detail with reference to particular arrangements and configurations, these exemplary configurations and arrangements can be changed significantly without departing from the scope of the present disclosure. For example, although the present disclosure has been described with reference to particular communication switches, the embodiments described herein can be applied to other architectures.

[0123] Those skilled in the art can determine many other changes, substitutions, variations, alterations, and modifications to the examples described herein and comprise all such changes, substitutions, variations, alterations, and modifications that fall within the scope of the appended claims. To assist the United States Patent and Trademark Office (USPTO) and additionally any readers of this application, Applicant hereby states as follows: (a) that Applicant does not intend to "invade" 35 U.S.C. § 112, paragraph 6, as it existed on the date of submission of the application hereof, unless "means or step- plus function" claims are specifically used therein; and (b) that Applicant does not intend to invoke 35 U.S.C. § 112, paragraph 6, as it exists on the date of submission of the application hereof, unless the words "means" or "step- plus function" are expressly used in the particular claim.< / blr> < / blr> < / blr> < / blr> < / blr>

Claims

1. A baseline restoration (BLR) circuit for a photon counting computed tomography (PCCT) signal chain, the BLR circuit comprising: an input comparator for comparing a shaper voltage output from a shaper component of the PCCT signal chain to a baseline voltage, the input comparator outputting a single bit indicating whether the shaper voltage is above or below the baseline voltage; and a low pass filter connected to filter a voltage signal output from the input comparator, wherein the BLR circuit comprises a feedback loop functioning as a delta modulator circuit.

2. The BLR circuit of claim 1, further comprising a transconductor connected to receive a filtered voltage signal output from the low pass filter, convert the filtered voltage signal to a current signal, and feed the current signal back to an input of the PCCT signal chain.

3. The BLR circuit of claim 2, wherein the input comparator, the low pass filter, and the transconductor comprise a delta modulator circuit for providing non-linear BLR.

4. The BLR circuit of claim 3, wherein the low pass filter comprises an integrator of the delta modulator circuit.

5. The BLR circuit of any one of claims 1 or 2, wherein the BLR circuit is clocked.

6. The BLR circuit of any one of claims 1 or 2, wherein chopper stabilization is applied to zero offset of the input comparator.

7. The BLR circuit of any one of claims 1 or 2, wherein auto-zeroing techniques are applied to zero offset of the input comparator.

8. The BLR circuit of any one of claims 1 or 2, wherein the BLR circuit is clocked and chopper stabilization is applied to zero offset of the input comparator.

9. The BLR circuit of any one of claims 1 or 2, wherein the BLR circuit is clocked and auto-zeroing techniques are applied to zero offset of the input comparator.

10. A method for implementing non-linear baseline restoration (BLR) in conjunction with a photon counting computed tomography (PCCT) signal chain, the method comprising: comparing, by an input comparator, a shaper voltage output from a shaper component of the PCCT signal chain to a baseline voltage to produce a comparator voltage indicating whether the shaper voltage is above or below the baseline voltage at a given time; filtering, by a low pass filter, the comparator voltage; and converting, by a transconductor, the filtered voltage signal to a current signal, wherein the input comparator, the low pass filter, and the transconductor comprise a feedback loop functioning as a delta modulator circuit.

11. The method of claim 10, further comprising feeding the current signal back to an input of the PCCT signal chain.

12. The method of any one of claims 10 or 11, further comprising clocking the comparing and filtering. ​ 13. The method of any one of claims 10 or 11, further comprising applying chopper stabilization to zero out an offset of an input comparator of the PCCT signal chain.

14. The method of any one of claims 10 or 11, further comprising applying an auto-zero technique to zero out an offset of an input comparator of the PCCT signal chain.

15. The method of any one of claims 10 or 11, further comprising: clocking the comparing and filtering; and applying chopper stabilization to zero out an offset of an input comparator of the PCCT signal chain.

16. The method of any one of claims 10 or 11, wherein the filtering is performed using a low pass filter.

17. The method of claim 16, further comprising applying a low duty cycle clock signal to the low pass filter to increase a value of a time constant.

18. A photon counting detector (PCD), comprising: a sensor to record an interaction with a photon received at the PCD and to forward a pulse indicative of the interaction to a signal chain; and a baseline restoration (BLR) circuit connected to the signal chain, the BLR circuit comprising: an input comparator to compare a voltage pulse output from the signal chain to a baseline voltage, the input comparator outputting a single bit indicating whether the voltage pulse is above or below the baseline voltage; and a low pass filter connected to filter a voltage signal output from the input comparator, wherein the BLR circuit comprises a feedback loop that functions as a delta modulator circuit.

19. The PCD of claim 18, wherein the BLR circuit further comprises a transconductor connected to receive a filtered voltage signal output from the low pass filter, to convert the filtered voltage signal to a current signal, and to feed back the current signal to an input of the signal chain.

20. The PCD of claim 19, wherein the input comparator, the low pass filter, and the transconductor comprise a delta modulator circuit to provide a non-linear BLR.

21. The PCD of any one of claims 18 or 19, wherein the signal chain comprises: a charge sense amplifier (CSA) to amplify a pulse received from the sensor and output an amplified pulse; and a pulse shaper (PS) to shape the amplified pulse and produce the voltage pulse output from the signal chain.

22. The PCD of any one of claims 18 or 19, further comprising a counting circuit to classify and count the voltage pulse output from the signal chain.

23. The PCD of any one of claims 18 or 19, wherein the BLR circuit is clocked.

24. The PCD of any one of claims 18 or 19, wherein chopper stabilization is applied in the BLR circuit to zero out an offset of the input comparator.

25. The PCD of any one of claims 18 or 19, wherein an auto-zero technique is applied in the BLR circuit to zero out an offset of the input comparator. ​ ​ ​ 26. The PCD of any one of claims 18 or 19, wherein the BLR circuit is timed and chopper stabilization is applied to zero out the offset of the input comparator.

27. A photon counting computed tomography (PCCT) system, comprising: an x-ray source for producing x-ray photons; and a photon counting detector (PCD) comprising: a sensor for recording an interaction with an x-ray photon received at the PCD after passing through an object of interest and forwarding a pulse indicative of the interaction to a signal chain; and a baseline restoration (BLR) circuit connected to the signal chain, the BLR circuit comprising: an input comparator for comparing a voltage pulse output from the signal chain to a baseline voltage, the input comparator outputting a single bit indicating whether the voltage pulse is above or below the baseline voltage; and a low pass filter connected to filter a voltage signal output from the input comparator, wherein the BLR circuit comprises a feedback loop that functions as a delta modulator circuit.

28. The PCCT system of claim 27, wherein the BLR circuit further comprises a transconductor connected to receive a filtered voltage signal output from the low pass filter, convert the filtered voltage signal to a current signal, and feed the current signal back to an input of the signal chain.

29. The PCCT system of claim 28, wherein the input comparator, the low pass filter, and the transconductor comprise a delta modulator circuit for providing a non-linear BLR.

30. The PCCT system of any one of claims 27 or 28, wherein the signal chain comprises: a charge sense amplifier (CSA) for amplifying a pulse received from the sensor and outputting an amplified pulse; and a pulse shaper (PS) for shaping the amplified pulse and generating the voltage pulse output from the signal chain.

31. The PCCT system of any one of claims 27 or 28, wherein the PCCT further comprises a counting circuit for classifying and counting the voltage pulses output from the signal chain.

32. The PCCT system of any one of claims 27 or 28, wherein the BLR circuit is timed.

33. The PCCT system of any one of claims 27 or 28, wherein chopper stabilization is applied in the BLR circuit to zero out the offset of the input comparator.

34. The PCCT system of any one of claims 27 or 28, wherein an auto-zeroing technique is applied in the BLR circuit to zero out the offset of the input comparator.

35. The PCCT system of any one of claims 27 or 28, wherein the BLR circuit is timed and chopper stabilization is applied to zero out the offset of the input comparator. ​ ​ ​ ​

Images